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0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/err.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <dt-bindings/sound/sc7180-lpass.h>
0016 #include <sound/pcm.h>
0017 #include <sound/soc.h>
0018
0019 #include "lpass-lpaif-reg.h"
0020 #include "lpass.h"
0021
0022 static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
0023 {
0024 .id = MI2S_PRIMARY,
0025 .name = "Primary MI2S",
0026 .playback = {
0027 .stream_name = "Primary Playback",
0028 .formats = SNDRV_PCM_FMTBIT_S16,
0029 .rates = SNDRV_PCM_RATE_48000,
0030 .rate_min = 48000,
0031 .rate_max = 48000,
0032 .channels_min = 2,
0033 .channels_max = 2,
0034 },
0035 .capture = {
0036 .stream_name = "Primary Capture",
0037 .formats = SNDRV_PCM_FMTBIT_S16 |
0038 SNDRV_PCM_FMTBIT_S32,
0039 .rates = SNDRV_PCM_RATE_48000,
0040 .rate_min = 48000,
0041 .rate_max = 48000,
0042 .channels_min = 2,
0043 .channels_max = 2,
0044 },
0045 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0046 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0047 }, {
0048 .id = MI2S_SECONDARY,
0049 .name = "Secondary MI2S",
0050 .playback = {
0051 .stream_name = "Secondary Playback",
0052 .formats = SNDRV_PCM_FMTBIT_S16,
0053 .rates = SNDRV_PCM_RATE_48000,
0054 .rate_min = 48000,
0055 .rate_max = 48000,
0056 .channels_min = 2,
0057 .channels_max = 2,
0058 },
0059 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0060 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0061 .pcm_new = lpass_cpu_pcm_new,
0062 }, {
0063 .id = LPASS_DP_RX,
0064 .name = "Hdmi",
0065 .playback = {
0066 .stream_name = "Hdmi Playback",
0067 .formats = SNDRV_PCM_FMTBIT_S24,
0068 .rates = SNDRV_PCM_RATE_48000,
0069 .rate_min = 48000,
0070 .rate_max = 48000,
0071 .channels_min = 2,
0072 .channels_max = 2,
0073 },
0074 .ops = &asoc_qcom_lpass_hdmi_dai_ops,
0075 },
0076 };
0077
0078 static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata,
0079 int direction, unsigned int dai_id)
0080 {
0081 struct lpass_variant *v = drvdata->variant;
0082 int chan = 0;
0083
0084 if (dai_id == LPASS_DP_RX) {
0085 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0086 chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
0087 v->hdmi_rdma_channels);
0088
0089 if (chan >= v->hdmi_rdma_channels)
0090 return -EBUSY;
0091 }
0092 set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
0093 } else {
0094 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0095 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
0096 v->rdma_channels);
0097
0098 if (chan >= v->rdma_channels)
0099 return -EBUSY;
0100 } else {
0101 chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
0102 v->wrdma_channel_start +
0103 v->wrdma_channels,
0104 v->wrdma_channel_start);
0105
0106 if (chan >= v->wrdma_channel_start + v->wrdma_channels)
0107 return -EBUSY;
0108 }
0109
0110 set_bit(chan, &drvdata->dma_ch_bit_map);
0111 }
0112 return chan;
0113 }
0114
0115 static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
0116 {
0117 if (dai_id == LPASS_DP_RX)
0118 clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
0119 else
0120 clear_bit(chan, &drvdata->dma_ch_bit_map);
0121
0122 return 0;
0123 }
0124
0125 static int sc7180_lpass_init(struct platform_device *pdev)
0126 {
0127 struct lpass_data *drvdata = platform_get_drvdata(pdev);
0128 struct lpass_variant *variant = drvdata->variant;
0129 struct device *dev = &pdev->dev;
0130 int ret, i;
0131
0132 drvdata->clks = devm_kcalloc(dev, variant->num_clks,
0133 sizeof(*drvdata->clks), GFP_KERNEL);
0134 drvdata->num_clks = variant->num_clks;
0135
0136 for (i = 0; i < drvdata->num_clks; i++)
0137 drvdata->clks[i].id = variant->clk_name[i];
0138
0139 ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
0140 if (ret) {
0141 dev_err(dev, "Failed to get clocks %d\n", ret);
0142 return ret;
0143 }
0144
0145 ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
0146 if (ret) {
0147 dev_err(dev, "sc7180 clk_enable failed\n");
0148 return ret;
0149 }
0150
0151 return 0;
0152 }
0153
0154 static int sc7180_lpass_exit(struct platform_device *pdev)
0155 {
0156 struct lpass_data *drvdata = platform_get_drvdata(pdev);
0157
0158 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
0159
0160 return 0;
0161 }
0162
0163 static struct lpass_variant sc7180_data = {
0164 .i2sctrl_reg_base = 0x1000,
0165 .i2sctrl_reg_stride = 0x1000,
0166 .i2s_ports = 3,
0167 .irq_reg_base = 0x9000,
0168 .irq_reg_stride = 0x1000,
0169 .irq_ports = 3,
0170 .rdma_reg_base = 0xC000,
0171 .rdma_reg_stride = 0x1000,
0172 .rdma_channels = 5,
0173 .hdmi_rdma_reg_base = 0x64000,
0174 .hdmi_rdma_reg_stride = 0x1000,
0175 .hdmi_rdma_channels = 4,
0176 .dmactl_audif_start = 1,
0177 .wrdma_reg_base = 0x18000,
0178 .wrdma_reg_stride = 0x1000,
0179 .wrdma_channel_start = 5,
0180 .wrdma_channels = 4,
0181
0182 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
0183 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
0184 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
0185 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
0186 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
0187 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
0188 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
0189 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
0190 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
0191
0192 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
0193 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
0194 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
0195 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
0196 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
0197 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
0198
0199 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
0200 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
0201 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
0202 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
0203 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
0204 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
0205
0206 .hdmi_tx_ctl_addr = 0x1000,
0207 .hdmi_legacy_addr = 0x1008,
0208 .hdmi_vbit_addr = 0x610c0,
0209 .hdmi_ch_lsb_addr = 0x61048,
0210 .hdmi_ch_msb_addr = 0x6104c,
0211 .ch_stride = 0x8,
0212 .hdmi_parity_addr = 0x61034,
0213 .hdmi_dmactl_addr = 0x61038,
0214 .hdmi_dma_stride = 0x4,
0215 .hdmi_DP_addr = 0x610c8,
0216 .hdmi_sstream_addr = 0x6101c,
0217 .hdmi_irq_reg_base = 0x63000,
0218 .hdmi_irq_ports = 1,
0219
0220 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
0221 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
0222 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
0223 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
0224 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
0225 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
0226 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
0227 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
0228
0229 .sstream_en = REG_FIELD(0x6101c, 0, 0),
0230 .dma_sel = REG_FIELD(0x6101c, 1, 2),
0231 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
0232 .layout = REG_FIELD(0x6101c, 4, 4),
0233 .layout_sp = REG_FIELD(0x6101c, 5, 8),
0234 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
0235 .dp_audio = REG_FIELD(0x6101c, 11, 11),
0236 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
0237 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
0238
0239 .mute = REG_FIELD(0x610c8, 0, 0),
0240 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
0241 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
0242 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
0243 .frequency = REG_FIELD(0x610c8, 16, 21),
0244 .mst_index = REG_FIELD(0x610c8, 28, 29),
0245 .dptx_index = REG_FIELD(0x610c8, 30, 31),
0246
0247 .soft_reset = REG_FIELD(0x1000, 31, 31),
0248 .force_reset = REG_FIELD(0x1000, 30, 30),
0249
0250 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
0251 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
0252 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
0253 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
0254
0255 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
0256 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
0257
0258 .legacy_en = REG_FIELD(0x1008, 0, 0),
0259 .calc_en = REG_FIELD(0x61034, 0, 0),
0260 .lsb_bits = REG_FIELD(0x61048, 0, 31),
0261 .msb_bits = REG_FIELD(0x6104c, 0, 31),
0262
0263
0264 .clk_name = (const char*[]) {
0265 "pcnoc-sway-clk",
0266 "audio-core",
0267 "pcnoc-mport-clk",
0268 },
0269 .num_clks = 3,
0270 .dai_driver = sc7180_lpass_cpu_dai_driver,
0271 .num_dai = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver),
0272 .dai_osr_clk_names = (const char *[]) {
0273 "mclk0",
0274 "null",
0275 },
0276 .dai_bit_clk_names = (const char *[]) {
0277 "mi2s-bit-clk0",
0278 "mi2s-bit-clk1",
0279 },
0280 .init = sc7180_lpass_init,
0281 .exit = sc7180_lpass_exit,
0282 .alloc_dma_channel = sc7180_lpass_alloc_dma_channel,
0283 .free_dma_channel = sc7180_lpass_free_dma_channel,
0284 };
0285
0286 static const struct of_device_id sc7180_lpass_cpu_device_id[] __maybe_unused = {
0287 {.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data},
0288 {}
0289 };
0290 MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id);
0291
0292 static struct platform_driver sc7180_lpass_cpu_platform_driver = {
0293 .driver = {
0294 .name = "sc7180-lpass-cpu",
0295 .of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id),
0296 },
0297 .probe = asoc_qcom_lpass_cpu_platform_probe,
0298 .remove = asoc_qcom_lpass_cpu_platform_remove,
0299 .shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
0300 };
0301
0302 module_platform_driver(sc7180_lpass_cpu_platform_driver);
0303
0304 MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
0305 MODULE_LICENSE("GPL v2");
