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0008 #include <linux/dma-mapping.h>
0009 #include <linux/export.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <sound/pcm_params.h>
0014 #include <linux/regmap.h>
0015 #include <sound/soc.h>
0016 #include "lpass-lpaif-reg.h"
0017 #include "lpass.h"
0018
0019 #define DRV_NAME "lpass-platform"
0020
0021 #define LPASS_PLATFORM_BUFFER_SIZE (24 * 2 * 1024)
0022 #define LPASS_PLATFORM_PERIODS 2
0023 #define LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE (8 * 1024)
0024 #define LPASS_VA_CDC_DMA_LPM_BUFF_SIZE (12 * 1024)
0025 #define LPASS_CDC_DMA_REGISTER_FIELDS_MAX 15
0026
0027 static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
0028 .info = SNDRV_PCM_INFO_MMAP |
0029 SNDRV_PCM_INFO_MMAP_VALID |
0030 SNDRV_PCM_INFO_INTERLEAVED |
0031 SNDRV_PCM_INFO_PAUSE |
0032 SNDRV_PCM_INFO_RESUME,
0033 .formats = SNDRV_PCM_FMTBIT_S16 |
0034 SNDRV_PCM_FMTBIT_S24 |
0035 SNDRV_PCM_FMTBIT_S32,
0036 .rates = SNDRV_PCM_RATE_8000_192000,
0037 .rate_min = 8000,
0038 .rate_max = 192000,
0039 .channels_min = 1,
0040 .channels_max = 8,
0041 .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
0042 .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
0043 LPASS_PLATFORM_PERIODS,
0044 .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
0045 LPASS_PLATFORM_PERIODS,
0046 .periods_min = LPASS_PLATFORM_PERIODS,
0047 .periods_max = LPASS_PLATFORM_PERIODS,
0048 .fifo_size = 0,
0049 };
0050
0051 static const struct snd_pcm_hardware lpass_platform_rxtx_hardware = {
0052 .info = SNDRV_PCM_INFO_MMAP |
0053 SNDRV_PCM_INFO_MMAP_VALID |
0054 SNDRV_PCM_INFO_INTERLEAVED |
0055 SNDRV_PCM_INFO_PAUSE |
0056 SNDRV_PCM_INFO_RESUME,
0057 .formats = SNDRV_PCM_FMTBIT_S16 |
0058 SNDRV_PCM_FMTBIT_S24 |
0059 SNDRV_PCM_FMTBIT_S32,
0060 .rates = SNDRV_PCM_RATE_8000_192000,
0061 .rate_min = 8000,
0062 .rate_max = 192000,
0063 .channels_min = 1,
0064 .channels_max = 8,
0065 .buffer_bytes_max = LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE,
0066 .period_bytes_max = LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE /
0067 LPASS_PLATFORM_PERIODS,
0068 .period_bytes_min = LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE /
0069 LPASS_PLATFORM_PERIODS,
0070 .periods_min = LPASS_PLATFORM_PERIODS,
0071 .periods_max = LPASS_PLATFORM_PERIODS,
0072 .fifo_size = 0,
0073 };
0074
0075 static const struct snd_pcm_hardware lpass_platform_va_hardware = {
0076 .info = SNDRV_PCM_INFO_MMAP |
0077 SNDRV_PCM_INFO_MMAP_VALID |
0078 SNDRV_PCM_INFO_INTERLEAVED |
0079 SNDRV_PCM_INFO_PAUSE |
0080 SNDRV_PCM_INFO_RESUME,
0081 .formats = SNDRV_PCM_FMTBIT_S16 |
0082 SNDRV_PCM_FMTBIT_S24 |
0083 SNDRV_PCM_FMTBIT_S32,
0084 .rates = SNDRV_PCM_RATE_8000_192000,
0085 .rate_min = 8000,
0086 .rate_max = 192000,
0087 .channels_min = 1,
0088 .channels_max = 8,
0089 .buffer_bytes_max = LPASS_VA_CDC_DMA_LPM_BUFF_SIZE,
0090 .period_bytes_max = LPASS_VA_CDC_DMA_LPM_BUFF_SIZE /
0091 LPASS_PLATFORM_PERIODS,
0092 .period_bytes_min = LPASS_VA_CDC_DMA_LPM_BUFF_SIZE /
0093 LPASS_PLATFORM_PERIODS,
0094 .periods_min = LPASS_PLATFORM_PERIODS,
0095 .periods_max = LPASS_PLATFORM_PERIODS,
0096 .fifo_size = 0,
0097 };
0098
0099 static int lpass_platform_alloc_rxtx_dmactl_fields(struct device *dev,
0100 struct regmap *map)
0101 {
0102 struct lpass_data *drvdata = dev_get_drvdata(dev);
0103 struct lpass_variant *v = drvdata->variant;
0104 struct lpaif_dmactl *rd_dmactl, *wr_dmactl;
0105 int rval;
0106
0107 rd_dmactl = devm_kzalloc(dev, sizeof(*rd_dmactl), GFP_KERNEL);
0108 if (!rd_dmactl)
0109 return -ENOMEM;
0110
0111 wr_dmactl = devm_kzalloc(dev, sizeof(*wr_dmactl), GFP_KERNEL);
0112 if (!wr_dmactl)
0113 return -ENOMEM;
0114
0115 drvdata->rxtx_rd_dmactl = rd_dmactl;
0116 drvdata->rxtx_wr_dmactl = wr_dmactl;
0117
0118 rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
0119 &v->rxtx_rdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
0120 if (rval)
0121 return rval;
0122
0123 return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
0124 &v->rxtx_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
0125 }
0126
0127 static int lpass_platform_alloc_va_dmactl_fields(struct device *dev,
0128 struct regmap *map)
0129 {
0130 struct lpass_data *drvdata = dev_get_drvdata(dev);
0131 struct lpass_variant *v = drvdata->variant;
0132 struct lpaif_dmactl *wr_dmactl;
0133
0134 wr_dmactl = devm_kzalloc(dev, sizeof(*wr_dmactl), GFP_KERNEL);
0135 if (!wr_dmactl)
0136 return -ENOMEM;
0137
0138 drvdata->va_wr_dmactl = wr_dmactl;
0139 return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
0140 &v->va_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
0141 }
0142
0143
0144 static int lpass_platform_alloc_dmactl_fields(struct device *dev,
0145 struct regmap *map)
0146 {
0147 struct lpass_data *drvdata = dev_get_drvdata(dev);
0148 struct lpass_variant *v = drvdata->variant;
0149 struct lpaif_dmactl *rd_dmactl, *wr_dmactl;
0150 int rval;
0151
0152 drvdata->rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
0153 GFP_KERNEL);
0154 if (drvdata->rd_dmactl == NULL)
0155 return -ENOMEM;
0156
0157 drvdata->wr_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
0158 GFP_KERNEL);
0159 if (drvdata->wr_dmactl == NULL)
0160 return -ENOMEM;
0161
0162 rd_dmactl = drvdata->rd_dmactl;
0163 wr_dmactl = drvdata->wr_dmactl;
0164
0165 rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
0166 &v->rdma_intf, 6);
0167 if (rval)
0168 return rval;
0169
0170 return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
0171 &v->wrdma_intf, 6);
0172 }
0173
0174 static int lpass_platform_alloc_hdmidmactl_fields(struct device *dev,
0175 struct regmap *map)
0176 {
0177 struct lpass_data *drvdata = dev_get_drvdata(dev);
0178 struct lpass_variant *v = drvdata->variant;
0179 struct lpaif_dmactl *rd_dmactl;
0180
0181 rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl), GFP_KERNEL);
0182 if (rd_dmactl == NULL)
0183 return -ENOMEM;
0184
0185 drvdata->hdmi_rd_dmactl = rd_dmactl;
0186
0187 return devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->bursten,
0188 &v->hdmi_rdma_bursten, 8);
0189 }
0190
0191 static int lpass_platform_pcmops_open(struct snd_soc_component *component,
0192 struct snd_pcm_substream *substream)
0193 {
0194 struct snd_pcm_runtime *runtime = substream->runtime;
0195 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0196 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0197 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0198 struct lpass_variant *v = drvdata->variant;
0199 int ret, dma_ch, dir = substream->stream;
0200 struct lpass_pcm_data *data;
0201 struct regmap *map;
0202 unsigned int dai_id = cpu_dai->driver->id;
0203
0204 component->id = dai_id;
0205 data = kzalloc(sizeof(*data), GFP_KERNEL);
0206 if (!data)
0207 return -ENOMEM;
0208
0209 data->i2s_port = cpu_dai->driver->id;
0210 runtime->private_data = data;
0211
0212 if (v->alloc_dma_channel)
0213 dma_ch = v->alloc_dma_channel(drvdata, dir, dai_id);
0214 else
0215 dma_ch = 0;
0216
0217 if (dma_ch < 0) {
0218 kfree(data);
0219 return dma_ch;
0220 }
0221
0222 switch (dai_id) {
0223 case MI2S_PRIMARY ... MI2S_QUINARY:
0224 map = drvdata->lpaif_map;
0225 drvdata->substream[dma_ch] = substream;
0226 break;
0227 case LPASS_DP_RX:
0228 map = drvdata->hdmiif_map;
0229 drvdata->hdmi_substream[dma_ch] = substream;
0230 break;
0231 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0232 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0233 map = drvdata->rxtx_lpaif_map;
0234 drvdata->rxtx_substream[dma_ch] = substream;
0235 break;
0236 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0237 map = drvdata->va_lpaif_map;
0238 drvdata->va_substream[dma_ch] = substream;
0239 break;
0240 default:
0241 break;
0242 }
0243
0244 data->dma_ch = dma_ch;
0245 switch (dai_id) {
0246 case MI2S_PRIMARY ... MI2S_QUINARY:
0247 case LPASS_DP_RX:
0248 ret = regmap_write(map, LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0);
0249 if (ret) {
0250 kfree(data);
0251 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n", ret);
0252 return ret;
0253 }
0254 snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
0255 runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
0256 break;
0257 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0258 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0259 snd_soc_set_runtime_hwparams(substream, &lpass_platform_rxtx_hardware);
0260 runtime->dma_bytes = lpass_platform_rxtx_hardware.buffer_bytes_max;
0261 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
0262 break;
0263 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0264 snd_soc_set_runtime_hwparams(substream, &lpass_platform_va_hardware);
0265 runtime->dma_bytes = lpass_platform_va_hardware.buffer_bytes_max;
0266 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
0267 break;
0268 default:
0269 break;
0270 }
0271 ret = snd_pcm_hw_constraint_integer(runtime,
0272 SNDRV_PCM_HW_PARAM_PERIODS);
0273 if (ret < 0) {
0274 kfree(data);
0275 dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
0276 ret);
0277 return -EINVAL;
0278 }
0279
0280 return 0;
0281 }
0282
0283 static int lpass_platform_pcmops_close(struct snd_soc_component *component,
0284 struct snd_pcm_substream *substream)
0285 {
0286 struct snd_pcm_runtime *runtime = substream->runtime;
0287 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0288 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0289 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0290 struct lpass_variant *v = drvdata->variant;
0291 struct lpass_pcm_data *data;
0292 unsigned int dai_id = cpu_dai->driver->id;
0293
0294 data = runtime->private_data;
0295
0296 switch (dai_id) {
0297 case MI2S_PRIMARY ... MI2S_QUINARY:
0298 drvdata->substream[data->dma_ch] = NULL;
0299 break;
0300 case LPASS_DP_RX:
0301 drvdata->hdmi_substream[data->dma_ch] = NULL;
0302 break;
0303 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0304 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0305 drvdata->rxtx_substream[data->dma_ch] = NULL;
0306 break;
0307 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0308 drvdata->va_substream[data->dma_ch] = NULL;
0309 break;
0310 default:
0311 break;
0312 }
0313
0314 if (v->free_dma_channel)
0315 v->free_dma_channel(drvdata, data->dma_ch, dai_id);
0316
0317 kfree(data);
0318 return 0;
0319 }
0320
0321 static struct lpaif_dmactl *__lpass_get_dmactl_handle(const struct snd_pcm_substream *substream,
0322 struct snd_soc_component *component)
0323 {
0324 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0325 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0326 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0327 struct lpaif_dmactl *dmactl = NULL;
0328
0329 switch (cpu_dai->driver->id) {
0330 case MI2S_PRIMARY ... MI2S_QUINARY:
0331 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0332 dmactl = drvdata->rd_dmactl;
0333 else
0334 dmactl = drvdata->wr_dmactl;
0335 break;
0336 case LPASS_DP_RX:
0337 dmactl = drvdata->hdmi_rd_dmactl;
0338 break;
0339 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0340 dmactl = drvdata->rxtx_rd_dmactl;
0341 break;
0342 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0343 dmactl = drvdata->rxtx_wr_dmactl;
0344 break;
0345 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0346 dmactl = drvdata->va_wr_dmactl;
0347 break;
0348 }
0349
0350 return dmactl;
0351 }
0352
0353 static int __lpass_get_id(const struct snd_pcm_substream *substream,
0354 struct snd_soc_component *component)
0355 {
0356 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0357 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0358 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0359 struct snd_pcm_runtime *rt = substream->runtime;
0360 struct lpass_pcm_data *pcm_data = rt->private_data;
0361 struct lpass_variant *v = drvdata->variant;
0362 int id;
0363
0364 switch (cpu_dai->driver->id) {
0365 case MI2S_PRIMARY ... MI2S_QUINARY:
0366 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0367 id = pcm_data->dma_ch;
0368 else
0369 id = pcm_data->dma_ch - v->wrdma_channel_start;
0370 break;
0371 case LPASS_DP_RX:
0372 id = pcm_data->dma_ch;
0373 break;
0374 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0375 id = pcm_data->dma_ch;
0376 break;
0377 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0378 id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
0379 break;
0380 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0381 id = pcm_data->dma_ch - v->va_wrdma_channel_start;
0382 break;
0383 }
0384
0385 return id;
0386 }
0387
0388 static struct regmap *__lpass_get_regmap_handle(const struct snd_pcm_substream *substream,
0389 struct snd_soc_component *component)
0390 {
0391 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0392 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0393 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0394 struct regmap *map = NULL;
0395
0396 switch (cpu_dai->driver->id) {
0397 case MI2S_PRIMARY ... MI2S_QUINARY:
0398 map = drvdata->lpaif_map;
0399 break;
0400 case LPASS_DP_RX:
0401 map = drvdata->hdmiif_map;
0402 break;
0403 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0404 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0405 map = drvdata->rxtx_lpaif_map;
0406 break;
0407 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0408 map = drvdata->va_lpaif_map;
0409 break;
0410 }
0411
0412 return map;
0413 }
0414
0415 static int lpass_platform_pcmops_hw_params(struct snd_soc_component *component,
0416 struct snd_pcm_substream *substream,
0417 struct snd_pcm_hw_params *params)
0418 {
0419 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0420 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0421 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0422 struct snd_pcm_runtime *rt = substream->runtime;
0423 struct lpass_pcm_data *pcm_data = rt->private_data;
0424 struct lpass_variant *v = drvdata->variant;
0425 snd_pcm_format_t format = params_format(params);
0426 unsigned int channels = params_channels(params);
0427 unsigned int regval;
0428 struct lpaif_dmactl *dmactl;
0429 int id;
0430 int bitwidth;
0431 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
0432 unsigned int dai_id = cpu_dai->driver->id;
0433
0434 dmactl = __lpass_get_dmactl_handle(substream, component);
0435 id = __lpass_get_id(substream, component);
0436
0437 bitwidth = snd_pcm_format_width(format);
0438 if (bitwidth < 0) {
0439 dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
0440 bitwidth);
0441 return bitwidth;
0442 }
0443
0444 ret = regmap_fields_write(dmactl->bursten, id, LPAIF_DMACTL_BURSTEN_INCR4);
0445 if (ret) {
0446 dev_err(soc_runtime->dev, "error updating bursten field: %d\n", ret);
0447 return ret;
0448 }
0449
0450 ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
0451 if (ret) {
0452 dev_err(soc_runtime->dev, "error updating fifowm field: %d\n", ret);
0453 return ret;
0454 }
0455
0456 switch (dai_id) {
0457 case LPASS_DP_RX:
0458 ret = regmap_fields_write(dmactl->burst8, id,
0459 LPAIF_DMACTL_BURSTEN_INCR4);
0460 if (ret) {
0461 dev_err(soc_runtime->dev, "error updating burst8en field: %d\n", ret);
0462 return ret;
0463 }
0464 ret = regmap_fields_write(dmactl->burst16, id,
0465 LPAIF_DMACTL_BURSTEN_INCR4);
0466 if (ret) {
0467 dev_err(soc_runtime->dev, "error updating burst16en field: %d\n", ret);
0468 return ret;
0469 }
0470 ret = regmap_fields_write(dmactl->dynburst, id,
0471 LPAIF_DMACTL_BURSTEN_INCR4);
0472 if (ret) {
0473 dev_err(soc_runtime->dev, "error updating dynbursten field: %d\n", ret);
0474 return ret;
0475 }
0476 break;
0477 case MI2S_PRIMARY:
0478 case MI2S_SECONDARY:
0479 case MI2S_TERTIARY:
0480 case MI2S_QUATERNARY:
0481 case MI2S_QUINARY:
0482 ret = regmap_fields_write(dmactl->intf, id,
0483 LPAIF_DMACTL_AUDINTF(dma_port));
0484 if (ret) {
0485 dev_err(soc_runtime->dev, "error updating audio interface field: %d\n",
0486 ret);
0487 return ret;
0488 }
0489
0490 break;
0491 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0492 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0493 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0:
0494 break;
0495 default:
0496 dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai_id);
0497 break;
0498 }
0499 switch (bitwidth) {
0500 case 16:
0501 switch (channels) {
0502 case 1:
0503 case 2:
0504 regval = LPAIF_DMACTL_WPSCNT_ONE;
0505 break;
0506 case 4:
0507 regval = LPAIF_DMACTL_WPSCNT_TWO;
0508 break;
0509 case 6:
0510 regval = LPAIF_DMACTL_WPSCNT_THREE;
0511 break;
0512 case 8:
0513 regval = LPAIF_DMACTL_WPSCNT_FOUR;
0514 break;
0515 default:
0516 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
0517 bitwidth, channels);
0518 return -EINVAL;
0519 }
0520 break;
0521 case 24:
0522 case 32:
0523 switch (channels) {
0524 case 1:
0525 regval = LPAIF_DMACTL_WPSCNT_ONE;
0526 break;
0527 case 2:
0528 regval = (dai_id == LPASS_DP_RX ?
0529 LPAIF_DMACTL_WPSCNT_ONE :
0530 LPAIF_DMACTL_WPSCNT_TWO);
0531 break;
0532 case 4:
0533 regval = (dai_id == LPASS_DP_RX ?
0534 LPAIF_DMACTL_WPSCNT_TWO :
0535 LPAIF_DMACTL_WPSCNT_FOUR);
0536 break;
0537 case 6:
0538 regval = (dai_id == LPASS_DP_RX ?
0539 LPAIF_DMACTL_WPSCNT_THREE :
0540 LPAIF_DMACTL_WPSCNT_SIX);
0541 break;
0542 case 8:
0543 regval = (dai_id == LPASS_DP_RX ?
0544 LPAIF_DMACTL_WPSCNT_FOUR :
0545 LPAIF_DMACTL_WPSCNT_EIGHT);
0546 break;
0547 default:
0548 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
0549 bitwidth, channels);
0550 return -EINVAL;
0551 }
0552 break;
0553 default:
0554 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
0555 bitwidth, channels);
0556 return -EINVAL;
0557 }
0558
0559 ret = regmap_fields_write(dmactl->wpscnt, id, regval);
0560 if (ret) {
0561 dev_err(soc_runtime->dev, "error writing to dmactl reg: %d\n",
0562 ret);
0563 return ret;
0564 }
0565
0566 return 0;
0567 }
0568
0569 static int lpass_platform_pcmops_hw_free(struct snd_soc_component *component,
0570 struct snd_pcm_substream *substream)
0571 {
0572 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0573 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0574 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0575 struct snd_pcm_runtime *rt = substream->runtime;
0576 struct lpass_pcm_data *pcm_data = rt->private_data;
0577 struct lpass_variant *v = drvdata->variant;
0578 unsigned int reg;
0579 int ret;
0580 struct regmap *map;
0581 unsigned int dai_id = cpu_dai->driver->id;
0582
0583 if (is_cdc_dma_port(dai_id))
0584 return 0;
0585 map = __lpass_get_regmap_handle(substream, component);
0586
0587 reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream, dai_id);
0588 ret = regmap_write(map, reg, 0);
0589 if (ret)
0590 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
0591 ret);
0592
0593 return ret;
0594 }
0595
0596 static int lpass_platform_pcmops_prepare(struct snd_soc_component *component,
0597 struct snd_pcm_substream *substream)
0598 {
0599 struct snd_pcm_runtime *runtime = substream->runtime;
0600 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0601 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0602 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0603 struct snd_pcm_runtime *rt = substream->runtime;
0604 struct lpass_pcm_data *pcm_data = rt->private_data;
0605 struct lpass_variant *v = drvdata->variant;
0606 struct lpaif_dmactl *dmactl;
0607 struct regmap *map;
0608 int ret, id, ch, dir = substream->stream;
0609 unsigned int dai_id = cpu_dai->driver->id;
0610
0611 ch = pcm_data->dma_ch;
0612
0613 dmactl = __lpass_get_dmactl_handle(substream, component);
0614 id = __lpass_get_id(substream, component);
0615 map = __lpass_get_regmap_handle(substream, component);
0616
0617 ret = regmap_write(map, LPAIF_DMABASE_REG(v, ch, dir, dai_id),
0618 runtime->dma_addr);
0619 if (ret) {
0620 dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
0621 ret);
0622 return ret;
0623 }
0624
0625 ret = regmap_write(map, LPAIF_DMABUFF_REG(v, ch, dir, dai_id),
0626 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
0627 if (ret) {
0628 dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
0629 ret);
0630 return ret;
0631 }
0632
0633 ret = regmap_write(map, LPAIF_DMAPER_REG(v, ch, dir, dai_id),
0634 (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
0635 if (ret) {
0636 dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
0637 ret);
0638 return ret;
0639 }
0640
0641 if (is_cdc_dma_port(dai_id)) {
0642 ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
0643 if (ret) {
0644 dev_err(soc_runtime->dev, "error writing fifowm field to dmactl reg: %d, id: %d\n",
0645 ret, id);
0646 return ret;
0647 }
0648 }
0649 ret = regmap_fields_write(dmactl->enable, id, LPAIF_DMACTL_ENABLE_ON);
0650 if (ret) {
0651 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
0652 ret);
0653 return ret;
0654 }
0655
0656 return 0;
0657 }
0658
0659 static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,
0660 struct snd_pcm_substream *substream,
0661 int cmd)
0662 {
0663 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0664 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0665 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0666 struct snd_pcm_runtime *rt = substream->runtime;
0667 struct lpass_pcm_data *pcm_data = rt->private_data;
0668 struct lpass_variant *v = drvdata->variant;
0669 struct lpaif_dmactl *dmactl;
0670 struct regmap *map;
0671 int ret, ch, id;
0672 unsigned int reg_irqclr = 0, val_irqclr = 0;
0673 unsigned int reg_irqen = 0, val_irqen = 0, val_mask = 0;
0674 unsigned int dai_id = cpu_dai->driver->id;
0675
0676 ch = pcm_data->dma_ch;
0677 dmactl = __lpass_get_dmactl_handle(substream, component);
0678 id = __lpass_get_id(substream, component);
0679 map = __lpass_get_regmap_handle(substream, component);
0680
0681 switch (cmd) {
0682 case SNDRV_PCM_TRIGGER_START:
0683 case SNDRV_PCM_TRIGGER_RESUME:
0684 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0685 ret = regmap_fields_write(dmactl->enable, id,
0686 LPAIF_DMACTL_ENABLE_ON);
0687 if (ret) {
0688 dev_err(soc_runtime->dev,
0689 "error writing to rdmactl reg: %d\n", ret);
0690 return ret;
0691 }
0692 switch (dai_id) {
0693 case LPASS_DP_RX:
0694 ret = regmap_fields_write(dmactl->dyncclk, id,
0695 LPAIF_DMACTL_DYNCLK_ON);
0696 if (ret) {
0697 dev_err(soc_runtime->dev,
0698 "error writing to rdmactl reg: %d\n", ret);
0699 return ret;
0700 }
0701 reg_irqclr = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
0702 val_irqclr = (LPAIF_IRQ_ALL(ch) |
0703 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
0704 LPAIF_IRQ_HDMI_METADONE |
0705 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
0706
0707 reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
0708 val_mask = (LPAIF_IRQ_ALL(ch) |
0709 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
0710 LPAIF_IRQ_HDMI_METADONE |
0711 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
0712 val_irqen = (LPAIF_IRQ_ALL(ch) |
0713 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
0714 LPAIF_IRQ_HDMI_METADONE |
0715 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
0716 break;
0717 case MI2S_PRIMARY:
0718 case MI2S_SECONDARY:
0719 case MI2S_TERTIARY:
0720 case MI2S_QUATERNARY:
0721 case MI2S_QUINARY:
0722 reg_irqclr = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0723 val_irqclr = LPAIF_IRQ_ALL(ch);
0724
0725
0726 reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
0727 val_mask = LPAIF_IRQ_ALL(ch);
0728 val_irqen = LPAIF_IRQ_ALL(ch);
0729 break;
0730 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0731 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0732 ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_ON);
0733 if (ret) {
0734 dev_err(soc_runtime->dev,
0735 "error writing to rdmactl reg field: %d\n", ret);
0736 return ret;
0737 }
0738 reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0739 val_irqclr = LPAIF_IRQ_ALL(ch);
0740
0741 reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
0742 val_mask = LPAIF_IRQ_ALL(ch);
0743 val_irqen = LPAIF_IRQ_ALL(ch);
0744 break;
0745 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0746 ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_ON);
0747 if (ret) {
0748 dev_err(soc_runtime->dev,
0749 "error writing to rdmactl reg field: %d\n", ret);
0750 return ret;
0751 }
0752 reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0753 val_irqclr = LPAIF_IRQ_ALL(ch);
0754
0755 reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
0756 val_mask = LPAIF_IRQ_ALL(ch);
0757 val_irqen = LPAIF_IRQ_ALL(ch);
0758 break;
0759 default:
0760 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
0761 return -EINVAL;
0762 }
0763
0764 ret = regmap_write_bits(map, reg_irqclr, val_irqclr, val_irqclr);
0765 if (ret) {
0766 dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret);
0767 return ret;
0768 }
0769 ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
0770 if (ret) {
0771 dev_err(soc_runtime->dev, "error writing to irqen reg: %d\n", ret);
0772 return ret;
0773 }
0774 break;
0775 case SNDRV_PCM_TRIGGER_STOP:
0776 case SNDRV_PCM_TRIGGER_SUSPEND:
0777 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0778 ret = regmap_fields_write(dmactl->enable, id,
0779 LPAIF_DMACTL_ENABLE_OFF);
0780 if (ret) {
0781 dev_err(soc_runtime->dev,
0782 "error writing to rdmactl reg: %d\n", ret);
0783 return ret;
0784 }
0785 switch (dai_id) {
0786 case LPASS_DP_RX:
0787 ret = regmap_fields_write(dmactl->dyncclk, id,
0788 LPAIF_DMACTL_DYNCLK_OFF);
0789 if (ret) {
0790 dev_err(soc_runtime->dev,
0791 "error writing to rdmactl reg: %d\n", ret);
0792 return ret;
0793 }
0794 reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
0795 val_mask = (LPAIF_IRQ_ALL(ch) |
0796 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
0797 LPAIF_IRQ_HDMI_METADONE |
0798 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
0799 val_irqen = 0;
0800 break;
0801 case MI2S_PRIMARY:
0802 case MI2S_SECONDARY:
0803 case MI2S_TERTIARY:
0804 case MI2S_QUATERNARY:
0805 case MI2S_QUINARY:
0806 reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
0807 val_mask = LPAIF_IRQ_ALL(ch);
0808 val_irqen = 0;
0809 break;
0810 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0811 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0812 ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_OFF);
0813 if (ret) {
0814 dev_err(soc_runtime->dev,
0815 "error writing to rdmactl reg field: %d\n", ret);
0816 return ret;
0817 }
0818
0819 reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0820 val_irqclr = LPAIF_IRQ_ALL(ch);
0821
0822 reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
0823 val_mask = LPAIF_IRQ_ALL(ch);
0824 val_irqen = LPAIF_IRQ_ALL(ch);
0825 break;
0826 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0827 ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_OFF);
0828 if (ret) {
0829 dev_err(soc_runtime->dev,
0830 "error writing to rdmactl reg field: %d\n", ret);
0831 return ret;
0832 }
0833
0834 reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0835 val_irqclr = LPAIF_IRQ_ALL(ch);
0836
0837 reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
0838 val_mask = LPAIF_IRQ_ALL(ch);
0839 val_irqen = LPAIF_IRQ_ALL(ch);
0840 break;
0841 default:
0842 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
0843 return -EINVAL;
0844 }
0845
0846 ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
0847 if (ret) {
0848 dev_err(soc_runtime->dev,
0849 "error writing to irqen reg: %d\n", ret);
0850 return ret;
0851 }
0852 break;
0853 }
0854
0855 return 0;
0856 }
0857
0858 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
0859 struct snd_soc_component *component,
0860 struct snd_pcm_substream *substream)
0861 {
0862 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0863 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0864 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
0865 struct snd_pcm_runtime *rt = substream->runtime;
0866 struct lpass_pcm_data *pcm_data = rt->private_data;
0867 struct lpass_variant *v = drvdata->variant;
0868 unsigned int base_addr, curr_addr;
0869 int ret, ch, dir = substream->stream;
0870 struct regmap *map;
0871 unsigned int dai_id = cpu_dai->driver->id;
0872
0873 map = __lpass_get_regmap_handle(substream, component);
0874 ch = pcm_data->dma_ch;
0875
0876 ret = regmap_read(map,
0877 LPAIF_DMABASE_REG(v, ch, dir, dai_id), &base_addr);
0878 if (ret) {
0879 dev_err(soc_runtime->dev,
0880 "error reading from rdmabase reg: %d\n", ret);
0881 return ret;
0882 }
0883
0884 ret = regmap_read(map,
0885 LPAIF_DMACURR_REG(v, ch, dir, dai_id), &curr_addr);
0886 if (ret) {
0887 dev_err(soc_runtime->dev,
0888 "error reading from rdmacurr reg: %d\n", ret);
0889 return ret;
0890 }
0891
0892 return bytes_to_frames(substream->runtime, curr_addr - base_addr);
0893 }
0894
0895 static int lpass_platform_cdc_dma_mmap(struct snd_pcm_substream *substream,
0896 struct vm_area_struct *vma)
0897 {
0898 struct snd_pcm_runtime *runtime = substream->runtime;
0899 unsigned long size, offset;
0900
0901 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
0902 size = vma->vm_end - vma->vm_start;
0903 offset = vma->vm_pgoff << PAGE_SHIFT;
0904 return io_remap_pfn_range(vma, vma->vm_start,
0905 (runtime->dma_addr + offset) >> PAGE_SHIFT,
0906 size, vma->vm_page_prot);
0907
0908 }
0909
0910 static int lpass_platform_pcmops_mmap(struct snd_soc_component *component,
0911 struct snd_pcm_substream *substream,
0912 struct vm_area_struct *vma)
0913 {
0914 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0915 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0916 unsigned int dai_id = cpu_dai->driver->id;
0917
0918 if (is_cdc_dma_port(dai_id))
0919 return lpass_platform_cdc_dma_mmap(substream, vma);
0920
0921 return snd_pcm_lib_default_mmap(substream, vma);
0922 }
0923
0924 static irqreturn_t lpass_dma_interrupt_handler(
0925 struct snd_pcm_substream *substream,
0926 struct lpass_data *drvdata,
0927 int chan, u32 interrupts)
0928 {
0929 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
0930 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
0931 struct lpass_variant *v = drvdata->variant;
0932 irqreturn_t ret = IRQ_NONE;
0933 int rv;
0934 unsigned int reg, val, mask;
0935 struct regmap *map;
0936 unsigned int dai_id = cpu_dai->driver->id;
0937
0938 mask = LPAIF_IRQ_ALL(chan);
0939 switch (dai_id) {
0940 case LPASS_DP_RX:
0941 map = drvdata->hdmiif_map;
0942 reg = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
0943 val = (LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
0944 LPAIF_IRQ_HDMI_METADONE |
0945 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan));
0946 break;
0947 case MI2S_PRIMARY:
0948 case MI2S_SECONDARY:
0949 case MI2S_TERTIARY:
0950 case MI2S_QUATERNARY:
0951 case MI2S_QUINARY:
0952 map = drvdata->lpaif_map;
0953 reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0954 val = 0;
0955 break;
0956 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0957 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0958 map = drvdata->rxtx_lpaif_map;
0959 reg = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0960 val = 0;
0961 break;
0962 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0963 map = drvdata->va_lpaif_map;
0964 reg = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
0965 val = 0;
0966 break;
0967 default:
0968 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
0969 return -EINVAL;
0970 }
0971 if (interrupts & LPAIF_IRQ_PER(chan)) {
0972 rv = regmap_write_bits(map, reg, mask, (LPAIF_IRQ_PER(chan) | val));
0973 if (rv) {
0974 dev_err(soc_runtime->dev,
0975 "error writing to irqclear reg: %d\n", rv);
0976 return IRQ_NONE;
0977 }
0978 snd_pcm_period_elapsed(substream);
0979 ret = IRQ_HANDLED;
0980 }
0981
0982 if (interrupts & LPAIF_IRQ_XRUN(chan)) {
0983 rv = regmap_write_bits(map, reg, mask, (LPAIF_IRQ_XRUN(chan) | val));
0984 if (rv) {
0985 dev_err(soc_runtime->dev,
0986 "error writing to irqclear reg: %d\n", rv);
0987 return IRQ_NONE;
0988 }
0989 dev_warn_ratelimited(soc_runtime->dev, "xrun warning\n");
0990
0991 snd_pcm_stop_xrun(substream);
0992 ret = IRQ_HANDLED;
0993 }
0994
0995 if (interrupts & LPAIF_IRQ_ERR(chan)) {
0996 rv = regmap_write_bits(map, reg, mask, (LPAIF_IRQ_ERR(chan) | val));
0997 if (rv) {
0998 dev_err(soc_runtime->dev,
0999 "error writing to irqclear reg: %d\n", rv);
1000 return IRQ_NONE;
1001 }
1002 dev_err(soc_runtime->dev, "bus access error\n");
1003 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
1004 ret = IRQ_HANDLED;
1005 }
1006
1007 if (interrupts & val) {
1008 rv = regmap_write(map, reg, val);
1009 if (rv) {
1010 dev_err(soc_runtime->dev,
1011 "error writing to irqclear reg: %d\n", rv);
1012 return IRQ_NONE;
1013 }
1014 ret = IRQ_HANDLED;
1015 }
1016
1017 return ret;
1018 }
1019
1020 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
1021 {
1022 struct lpass_data *drvdata = data;
1023 struct lpass_variant *v = drvdata->variant;
1024 unsigned int irqs;
1025 int rv, chan;
1026
1027 rv = regmap_read(drvdata->lpaif_map,
1028 LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
1029 if (rv) {
1030 pr_err("error reading from irqstat reg: %d\n", rv);
1031 return IRQ_NONE;
1032 }
1033
1034
1035 for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
1036 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
1037 rv = lpass_dma_interrupt_handler(
1038 drvdata->substream[chan],
1039 drvdata, chan, irqs);
1040 if (rv != IRQ_HANDLED)
1041 return rv;
1042 }
1043 }
1044
1045 return IRQ_HANDLED;
1046 }
1047
1048 static irqreturn_t lpass_platform_hdmiif_irq(int irq, void *data)
1049 {
1050 struct lpass_data *drvdata = data;
1051 struct lpass_variant *v = drvdata->variant;
1052 unsigned int irqs;
1053 int rv, chan;
1054
1055 rv = regmap_read(drvdata->hdmiif_map,
1056 LPASS_HDMITX_APP_IRQSTAT_REG(v), &irqs);
1057 if (rv) {
1058 pr_err("error reading from irqstat reg: %d\n", rv);
1059 return IRQ_NONE;
1060 }
1061
1062
1063 for (chan = 0; chan < LPASS_MAX_HDMI_DMA_CHANNELS; chan++) {
1064 if (irqs & (LPAIF_IRQ_ALL(chan) | LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
1065 LPAIF_IRQ_HDMI_METADONE |
1066 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan))
1067 && drvdata->hdmi_substream[chan]) {
1068 rv = lpass_dma_interrupt_handler(
1069 drvdata->hdmi_substream[chan],
1070 drvdata, chan, irqs);
1071 if (rv != IRQ_HANDLED)
1072 return rv;
1073 }
1074 }
1075 return IRQ_HANDLED;
1076 }
1077
1078 static irqreturn_t lpass_platform_rxtxif_irq(int irq, void *data)
1079 {
1080 struct lpass_data *drvdata = data;
1081 struct lpass_variant *v = drvdata->variant;
1082 unsigned int irqs;
1083 irqreturn_t rv;
1084 int chan;
1085
1086 rv = regmap_read(drvdata->rxtx_lpaif_map,
1087 LPAIF_RXTX_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
1088
1089
1090 for (chan = 0; chan < LPASS_MAX_CDC_DMA_CHANNELS; chan++) {
1091 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->rxtx_substream[chan]) {
1092 rv = lpass_dma_interrupt_handler(
1093 drvdata->rxtx_substream[chan],
1094 drvdata, chan, irqs);
1095 if (rv != IRQ_HANDLED)
1096 return rv;
1097 }
1098 }
1099
1100 return IRQ_HANDLED;
1101 }
1102
1103 static irqreturn_t lpass_platform_vaif_irq(int irq, void *data)
1104 {
1105 struct lpass_data *drvdata = data;
1106 struct lpass_variant *v = drvdata->variant;
1107 unsigned int irqs;
1108 irqreturn_t rv;
1109 int chan;
1110
1111 rv = regmap_read(drvdata->va_lpaif_map,
1112 LPAIF_VA_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
1113
1114
1115 for (chan = 0; chan < LPASS_MAX_VA_CDC_DMA_CHANNELS; chan++) {
1116 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->va_substream[chan]) {
1117 rv = lpass_dma_interrupt_handler(
1118 drvdata->va_substream[chan],
1119 drvdata, chan, irqs);
1120 if (rv != IRQ_HANDLED)
1121 return rv;
1122 }
1123 }
1124 return IRQ_HANDLED;
1125 }
1126
1127 static int lpass_platform_prealloc_cdc_dma_buffer(struct snd_soc_component *component,
1128 struct snd_pcm *pcm, int dai_id)
1129 {
1130 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
1131 struct snd_pcm_substream *substream;
1132 struct snd_dma_buffer *buf;
1133
1134 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
1135 substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
1136 else
1137 substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
1138
1139 buf = &substream->dma_buffer;
1140 buf->dev.dev = pcm->card->dev;
1141 buf->private_data = NULL;
1142
1143
1144 buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
1145
1146 switch (dai_id) {
1147 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
1148 buf->bytes = lpass_platform_rxtx_hardware.buffer_bytes_max;
1149 buf->addr = drvdata->rxtx_cdc_dma_lpm_buf;
1150 break;
1151 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
1152 buf->bytes = lpass_platform_rxtx_hardware.buffer_bytes_max;
1153 buf->addr = drvdata->rxtx_cdc_dma_lpm_buf + LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE;
1154 break;
1155 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
1156 buf->bytes = lpass_platform_va_hardware.buffer_bytes_max;
1157 buf->addr = drvdata->va_cdc_dma_lpm_buf;
1158 break;
1159 default:
1160 break;
1161 }
1162
1163 buf->area = (unsigned char * __force)memremap(buf->addr, buf->bytes, MEMREMAP_WC);
1164
1165 return 0;
1166 }
1167
1168 static int lpass_platform_pcm_new(struct snd_soc_component *component,
1169 struct snd_soc_pcm_runtime *soc_runtime)
1170 {
1171 struct snd_pcm *pcm = soc_runtime->pcm;
1172 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
1173 unsigned int dai_id = cpu_dai->driver->id;
1174
1175 size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
1176
1177
1178
1179
1180
1181 if (is_cdc_dma_port(dai_id))
1182 return lpass_platform_prealloc_cdc_dma_buffer(component, pcm, dai_id);
1183
1184 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1185 component->dev, size);
1186 }
1187
1188 static int lpass_platform_pcmops_suspend(struct snd_soc_component *component)
1189 {
1190 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
1191 struct regmap *map;
1192 unsigned int dai_id = component->id;
1193
1194 if (dai_id == LPASS_DP_RX)
1195 map = drvdata->hdmiif_map;
1196 else
1197 map = drvdata->lpaif_map;
1198
1199 regcache_cache_only(map, true);
1200 regcache_mark_dirty(map);
1201
1202 return 0;
1203 }
1204
1205 static int lpass_platform_pcmops_resume(struct snd_soc_component *component)
1206 {
1207 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
1208 struct regmap *map;
1209 unsigned int dai_id = component->id;
1210
1211 if (dai_id == LPASS_DP_RX)
1212 map = drvdata->hdmiif_map;
1213 else
1214 map = drvdata->lpaif_map;
1215
1216 regcache_cache_only(map, false);
1217 return regcache_sync(map);
1218 }
1219
1220 static int lpass_platform_copy(struct snd_soc_component *component,
1221 struct snd_pcm_substream *substream, int channel,
1222 unsigned long pos, void __user *buf, unsigned long bytes)
1223 {
1224 struct snd_pcm_runtime *rt = substream->runtime;
1225 unsigned int dai_id = component->id;
1226 int ret = 0;
1227
1228 void __iomem *dma_buf = (void __iomem *) (rt->dma_area + pos +
1229 channel * (rt->dma_bytes / rt->channels));
1230
1231 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1232 if (is_cdc_dma_port(dai_id)) {
1233 ret = copy_from_user_toio(dma_buf, buf, bytes);
1234 } else {
1235 if (copy_from_user((void __force *)dma_buf, buf, bytes))
1236 ret = -EFAULT;
1237 }
1238 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1239 if (is_cdc_dma_port(dai_id)) {
1240 ret = copy_to_user_fromio(buf, dma_buf, bytes);
1241 } else {
1242 if (copy_to_user(buf, (void __force *)dma_buf, bytes))
1243 ret = -EFAULT;
1244 }
1245 }
1246
1247 return ret;
1248 }
1249
1250 static const struct snd_soc_component_driver lpass_component_driver = {
1251 .name = DRV_NAME,
1252 .open = lpass_platform_pcmops_open,
1253 .close = lpass_platform_pcmops_close,
1254 .hw_params = lpass_platform_pcmops_hw_params,
1255 .hw_free = lpass_platform_pcmops_hw_free,
1256 .prepare = lpass_platform_pcmops_prepare,
1257 .trigger = lpass_platform_pcmops_trigger,
1258 .pointer = lpass_platform_pcmops_pointer,
1259 .mmap = lpass_platform_pcmops_mmap,
1260 .pcm_construct = lpass_platform_pcm_new,
1261 .suspend = lpass_platform_pcmops_suspend,
1262 .resume = lpass_platform_pcmops_resume,
1263 .copy_user = lpass_platform_copy,
1264
1265 };
1266
1267 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
1268 {
1269 struct lpass_data *drvdata = platform_get_drvdata(pdev);
1270 struct lpass_variant *v = drvdata->variant;
1271 int ret;
1272
1273 drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
1274 if (drvdata->lpaif_irq < 0)
1275 return -ENODEV;
1276
1277
1278 ret = regmap_write(drvdata->lpaif_map,
1279 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
1280 if (ret) {
1281 dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
1282 return ret;
1283 }
1284
1285 ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
1286 lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
1287 "lpass-irq-lpaif", drvdata);
1288 if (ret) {
1289 dev_err(&pdev->dev, "irq request failed: %d\n", ret);
1290 return ret;
1291 }
1292
1293 ret = lpass_platform_alloc_dmactl_fields(&pdev->dev,
1294 drvdata->lpaif_map);
1295 if (ret) {
1296 dev_err(&pdev->dev,
1297 "error initializing dmactl fields: %d\n", ret);
1298 return ret;
1299 }
1300
1301 if (drvdata->codec_dma_enable) {
1302 ret = regmap_write(drvdata->rxtx_lpaif_map,
1303 LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0);
1304 if (ret) {
1305 dev_err(&pdev->dev, "error writing to rxtx irqen reg: %d\n", ret);
1306 return ret;
1307 }
1308 ret = regmap_write(drvdata->va_lpaif_map,
1309 LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0);
1310 if (ret) {
1311 dev_err(&pdev->dev, "error writing to rxtx irqen reg: %d\n", ret);
1312 return ret;
1313 }
1314 drvdata->rxtxif_irq = platform_get_irq_byname(pdev, "lpass-irq-rxtxif");
1315 if (drvdata->rxtxif_irq < 0)
1316 return -ENODEV;
1317
1318 ret = devm_request_irq(&pdev->dev, drvdata->rxtxif_irq,
1319 lpass_platform_rxtxif_irq, 0, "lpass-irq-rxtxif", drvdata);
1320 if (ret) {
1321 dev_err(&pdev->dev, "rxtx irq request failed: %d\n", ret);
1322 return ret;
1323 }
1324
1325 ret = lpass_platform_alloc_rxtx_dmactl_fields(&pdev->dev,
1326 drvdata->rxtx_lpaif_map);
1327 if (ret) {
1328 dev_err(&pdev->dev,
1329 "error initializing rxtx dmactl fields: %d\n", ret);
1330 return ret;
1331 }
1332
1333 drvdata->vaif_irq = platform_get_irq_byname(pdev, "lpass-irq-vaif");
1334 if (drvdata->vaif_irq < 0)
1335 return -ENODEV;
1336
1337 ret = devm_request_irq(&pdev->dev, drvdata->vaif_irq,
1338 lpass_platform_vaif_irq, 0, "lpass-irq-vaif", drvdata);
1339 if (ret) {
1340 dev_err(&pdev->dev, "va irq request failed: %d\n", ret);
1341 return ret;
1342 }
1343
1344 ret = lpass_platform_alloc_va_dmactl_fields(&pdev->dev,
1345 drvdata->va_lpaif_map);
1346 if (ret) {
1347 dev_err(&pdev->dev,
1348 "error initializing va dmactl fields: %d\n", ret);
1349 return ret;
1350 }
1351 }
1352
1353 if (drvdata->hdmi_port_enable) {
1354 drvdata->hdmiif_irq = platform_get_irq_byname(pdev, "lpass-irq-hdmi");
1355 if (drvdata->hdmiif_irq < 0)
1356 return -ENODEV;
1357
1358 ret = devm_request_irq(&pdev->dev, drvdata->hdmiif_irq,
1359 lpass_platform_hdmiif_irq, 0, "lpass-irq-hdmi", drvdata);
1360 if (ret) {
1361 dev_err(&pdev->dev, "irq hdmi request failed: %d\n", ret);
1362 return ret;
1363 }
1364 ret = regmap_write(drvdata->hdmiif_map,
1365 LPASS_HDMITX_APP_IRQEN_REG(v), 0);
1366 if (ret) {
1367 dev_err(&pdev->dev, "error writing to hdmi irqen reg: %d\n", ret);
1368 return ret;
1369 }
1370
1371 ret = lpass_platform_alloc_hdmidmactl_fields(&pdev->dev,
1372 drvdata->hdmiif_map);
1373 if (ret) {
1374 dev_err(&pdev->dev,
1375 "error initializing hdmidmactl fields: %d\n", ret);
1376 return ret;
1377 }
1378 }
1379 return devm_snd_soc_register_component(&pdev->dev,
1380 &lpass_component_driver, NULL, 0);
1381 }
1382 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
1383
1384 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
1385 MODULE_LICENSE("GPL v2");
