soc/qcom/lpass-lpaif-reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef __LPASS_LPAIF_REG_H__
0007 #define __LPASS_LPAIF_REG_H__
0008
0009 /* LPAIF I2S */
0010
0011 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
0012     (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
0013
0014 #define LPAIF_I2SCTL_REG(v, port)   LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
0015
0016 #define LPAIF_I2SCTL_LOOPBACK_DISABLE   0
0017 #define LPAIF_I2SCTL_LOOPBACK_ENABLE    1
0018
0019 #define LPAIF_I2SCTL_SPKEN_DISABLE  0
0020 #define LPAIF_I2SCTL_SPKEN_ENABLE   1
0021
0022 #define LPAIF_I2SCTL_MODE_NONE      0
0023 #define LPAIF_I2SCTL_MODE_SD0       1
0024 #define LPAIF_I2SCTL_MODE_SD1       2
0025 #define LPAIF_I2SCTL_MODE_SD2       3
0026 #define LPAIF_I2SCTL_MODE_SD3       4
0027 #define LPAIF_I2SCTL_MODE_QUAD01    5
0028 #define LPAIF_I2SCTL_MODE_QUAD23    6
0029 #define LPAIF_I2SCTL_MODE_6CH       7
0030 #define LPAIF_I2SCTL_MODE_8CH       8
0031 #define LPAIF_I2SCTL_MODE_10CH      9
0032 #define LPAIF_I2SCTL_MODE_12CH      10
0033 #define LPAIF_I2SCTL_MODE_14CH      11
0034 #define LPAIF_I2SCTL_MODE_16CH      12
0035 #define LPAIF_I2SCTL_MODE_SD4       13
0036 #define LPAIF_I2SCTL_MODE_SD5       14
0037 #define LPAIF_I2SCTL_MODE_SD6       15
0038 #define LPAIF_I2SCTL_MODE_SD7       16
0039 #define LPAIF_I2SCTL_MODE_QUAD45    17
0040 #define LPAIF_I2SCTL_MODE_QUAD47    18
0041 #define LPAIF_I2SCTL_MODE_8CH_2     19
0042
0043 #define LPAIF_I2SCTL_SPKMODE(mode)  mode
0044
0045 #define LPAIF_I2SCTL_SPKMONO_STEREO 0
0046 #define LPAIF_I2SCTL_SPKMONO_MONO   1
0047
0048 #define LPAIF_I2SCTL_MICEN_DISABLE  0
0049 #define LPAIF_I2SCTL_MICEN_ENABLE   1
0050
0051 #define LPAIF_I2SCTL_MICMODE(mode)  mode
0052
0053 #define LPAIF_I2SCTL_MICMONO_STEREO 0
0054 #define LPAIF_I2SCTL_MICMONO_MONO   1
0055
0056 #define LPAIF_I2SCTL_WSSRC_INTERNAL 0
0057 #define LPAIF_I2SCTL_WSSRC_EXTERNAL 1
0058
0059 #define LPAIF_I2SCTL_BITWIDTH_16    0
0060 #define LPAIF_I2SCTL_BITWIDTH_24    1
0061 #define LPAIF_I2SCTL_BITWIDTH_32    2
0062
0063 #define LPAIF_I2SCTL_RESET_STATE    0x003C0004
0064 #define LPAIF_DMACTL_RESET_STATE    0x00200000
0065
0066
0067 /* LPAIF IRQ */
0068 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \
0069     (v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
0070
0071 #define LPAIF_IRQ_PORT_HOST     0
0072
0073 #define LPAIF_IRQEN_REG(v, port)    LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
0074 #define LPAIF_IRQSTAT_REG(v, port)  LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
0075 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
0076
0077 /* LPAIF RXTX IRQ */
0078 #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
0079         (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
0080
0081 #define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
0082 #define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
0083 #define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
0084
0085 /* LPAIF VA IRQ */
0086 #define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
0087         (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
0088
0089 #define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
0090 #define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
0091 #define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
0092
0093 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \
0094     ((v->hdmi_irq_reg_base) + (addr))
0095
0096 #define LPASS_HDMITX_APP_IRQEN_REG(v)           LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
0097 #define LPASS_HDMITX_APP_IRQSTAT_REG(v)         LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
0098 #define LPASS_HDMITX_APP_IRQCLEAR_REG(v)        LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
0099
0100 #define LPAIF_IRQ_BITSTRIDE     3
0101
0102 #define LPAIF_IRQ_PER(chan)     (1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
0103 #define LPAIF_IRQ_XRUN(chan)        (2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
0104 #define LPAIF_IRQ_ERR(chan)     (4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
0105
0106 #define LPAIF_IRQ_ALL(chan)     (7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
0107 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan))
0108 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)  (1 << (24 + chan))
0109 #define LPAIF_IRQ_HDMI_METADONE     BIT(23)
0110
0111 /* LPAIF DMA */
0112 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
0113     (v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
0114
0115 #define LPAIF_HDMI_RDMACTL_AUDINTF(id)  (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
0116
0117 #define LPAIF_HDMI_RDMACTL_REG(v, chan)     LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
0118 #define LPAIF_HDMI_RDMABASE_REG(v, chan)    LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
0119 #define LPAIF_HDMI_RDMABUFF_REG(v, chan)    LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
0120 #define LPAIF_HDMI_RDMACURR_REG(v, chan)    LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
0121 #define LPAIF_HDMI_RDMAPER_REG(v, chan)     LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
0122 #define LPAIF_HDMI_RDMAPERCNT_REG(v, chan)  LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
0123
0124 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
0125     (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
0126
0127 #define LPAIF_RDMACTL_AUDINTF(id)   (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
0128
0129 #define LPAIF_RDMACTL_REG(v, chan)  LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
0130 #define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
0131 #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
0132 #define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
0133 #define LPAIF_RDMAPER_REG(v, chan)  LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
0134 #define LPAIF_RDMAPERCNT_REG(v, chan)   LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
0135
0136 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
0137     (v->wrdma_reg_base + (addr) + \
0138      v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
0139
0140 #define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
0141 #define LPAIF_WRDMABASE_REG(v, chan)    LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
0142 #define LPAIF_WRDMABUFF_REG(v, chan)    LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
0143 #define LPAIF_WRDMACURR_REG(v, chan)    LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
0144 #define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
0145 #define LPAIF_WRDMAPERCNT_REG(v, chan)  LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
0146
0147 #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \
0148     ((dai_id ==  LPASS_DP_RX) ? \
0149         LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
0150          LPAIF_RDMA##reg##_REG(v, chan))
0151
0152 #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \
0153     ((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
0154         (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
0155         LPAIF_WRDMA##reg##_REG(v, chan))
0156
0157 #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
0158     (is_cdc_dma_port(dai_id) ? \
0159     __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
0160     __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
0161 #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
0162     (is_cdc_dma_port(dai_id) ? \
0163     __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
0164     __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
0165 #define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
0166     (is_cdc_dma_port(dai_id) ? \
0167     __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
0168     __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
0169 #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
0170     (is_cdc_dma_port(dai_id) ? \
0171     __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
0172     __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
0173 #define LPAIF_DMAPER_REG(v, chan, dir, dai_id)  \
0174     (is_cdc_dma_port(dai_id) ? \
0175     __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
0176     __LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
0177 #define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
0178     (is_cdc_dma_port(dai_id) ? \
0179     __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
0180     __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
0181
0182 #define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
0183     (is_rxtx_cdc_dma_port(dai_id) ? \
0184     (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
0185     (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
0186
0187 #define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
0188         LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
0189 #define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
0190         LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
0191 #define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
0192         LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
0193 #define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
0194         LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
0195 #define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
0196         LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
0197 #define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
0198     LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
0199
0200 #define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
0201 #define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
0202 #define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
0203 #define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
0204 #define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
0205 #define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
0206     LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
0207
0208 #define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
0209     (is_rxtx_cdc_dma_port(dai_id) ? \
0210     (v->rxtx_wrdma_reg_base + (addr) + \
0211         v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
0212     (v->va_wrdma_reg_base + (addr) + \
0213         v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
0214
0215 #define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
0216     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
0217 #define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
0218     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
0219 #define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
0220     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
0221 #define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
0222     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
0223 #define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
0224     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
0225 #define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
0226     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
0227
0228 #define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
0229     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
0230 #define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
0231     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
0232 #define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
0233     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
0234 #define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
0235     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
0236 #define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
0237     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
0238 #define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
0239     LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
0240
0241 #define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
0242         (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
0243             LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
0244
0245 #define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
0246         (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
0247             LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
0248
0249 #define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
0250         ((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
0251             __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
0252             __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
0253
0254 #define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
0255         ((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
0256         LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
0257         LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
0258
0259 #define LPAIF_INTF_REG(v, chan, dir, dai_id) \
0260         (is_cdc_dma_port(dai_id) ? \
0261         LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
0262         LPAIF_DMACTL_REG(v, chan, dir, dai_id))
0263
0264 #define LPAIF_DMACTL_BURSTEN_SINGLE 0
0265 #define LPAIF_DMACTL_BURSTEN_INCR4  1
0266
0267 #define LPAIF_DMACTL_WPSCNT_ONE     0
0268 #define LPAIF_DMACTL_WPSCNT_TWO     1
0269 #define LPAIF_DMACTL_WPSCNT_THREE   2
0270 #define LPAIF_DMACTL_WPSCNT_FOUR    3
0271 #define LPAIF_DMACTL_WPSCNT_SIX     5
0272 #define LPAIF_DMACTL_WPSCNT_EIGHT   7
0273 #define LPAIF_DMACTL_WPSCNT_TEN     9
0274 #define LPAIF_DMACTL_WPSCNT_TWELVE  11
0275 #define LPAIF_DMACTL_WPSCNT_FOURTEEN    13
0276 #define LPAIF_DMACTL_WPSCNT_SIXTEEN 15
0277
0278 #define LPAIF_DMACTL_AUDINTF(id)    id
0279
0280 #define LPAIF_DMACTL_FIFOWM_1       0
0281 #define LPAIF_DMACTL_FIFOWM_2       1
0282 #define LPAIF_DMACTL_FIFOWM_3       2
0283 #define LPAIF_DMACTL_FIFOWM_4       3
0284 #define LPAIF_DMACTL_FIFOWM_5       4
0285 #define LPAIF_DMACTL_FIFOWM_6       5
0286 #define LPAIF_DMACTL_FIFOWM_7       6
0287 #define LPAIF_DMACTL_FIFOWM_8       7
0288 #define LPAIF_DMACTL_FIFOWM_9       8
0289 #define LPAIF_DMACTL_FIFOWM_10      9
0290 #define LPAIF_DMACTL_FIFOWM_11      10
0291 #define LPAIF_DMACTL_FIFOWM_12      11
0292 #define LPAIF_DMACTL_FIFOWM_13      12
0293 #define LPAIF_DMACTL_FIFOWM_14      13
0294 #define LPAIF_DMACTL_FIFOWM_15      14
0295 #define LPAIF_DMACTL_FIFOWM_16      15
0296 #define LPAIF_DMACTL_FIFOWM_17      16
0297 #define LPAIF_DMACTL_FIFOWM_18      17
0298 #define LPAIF_DMACTL_FIFOWM_19      18
0299 #define LPAIF_DMACTL_FIFOWM_20      19
0300 #define LPAIF_DMACTL_FIFOWM_21      20
0301 #define LPAIF_DMACTL_FIFOWM_22      21
0302 #define LPAIF_DMACTL_FIFOWM_23      22
0303 #define LPAIF_DMACTL_FIFOWM_24      23
0304 #define LPAIF_DMACTL_FIFOWM_25      24
0305 #define LPAIF_DMACTL_FIFOWM_26      25
0306 #define LPAIF_DMACTL_FIFOWM_27      26
0307 #define LPAIF_DMACTL_FIFOWM_28      27
0308 #define LPAIF_DMACTL_FIFOWM_29      28
0309 #define LPAIF_DMACTL_FIFOWM_30      29
0310 #define LPAIF_DMACTL_FIFOWM_31      30
0311 #define LPAIF_DMACTL_FIFOWM_32      31
0312
0313 #define LPAIF_DMACTL_ENABLE_OFF     0
0314 #define LPAIF_DMACTL_ENABLE_ON      1
0315
0316 #define LPAIF_DMACTL_DYNCLK_OFF     0
0317 #define LPAIF_DMACTL_DYNCLK_ON      1
0318
0319 #endif /* __LPASS_LPAIF_REG_H__ */