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0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <sound/pcm_params.h>
0012 #include <linux/regmap.h>
0013 #include <sound/soc.h>
0014 #include <sound/soc-dai.h>
0015 #include <dt-bindings/sound/sc7180-lpass.h>
0016 #include "lpass-lpaif-reg.h"
0017 #include "lpass.h"
0018
0019 static int lpass_hdmi_daiops_hw_params(struct snd_pcm_substream *substream,
0020 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0021 {
0022 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
0023 snd_pcm_format_t format = params_format(params);
0024 unsigned int rate = params_rate(params);
0025 unsigned int channels = params_channels(params);
0026 unsigned int ret;
0027 int bitwidth;
0028 unsigned int word_length;
0029 unsigned int ch_sts_buf0;
0030 unsigned int ch_sts_buf1;
0031 unsigned int data_format;
0032 unsigned int sampling_freq;
0033 unsigned int ch = 0;
0034 struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
0035 struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
0036
0037 bitwidth = snd_pcm_format_width(format);
0038 if (bitwidth < 0) {
0039 dev_err(dai->dev, "%s invalid bit width given : %d\n",
0040 __func__, bitwidth);
0041 return bitwidth;
0042 }
0043
0044 switch (bitwidth) {
0045 case 16:
0046 word_length = LPASS_DP_AUDIO_BITWIDTH16;
0047 break;
0048 case 24:
0049 word_length = LPASS_DP_AUDIO_BITWIDTH24;
0050 break;
0051 default:
0052 dev_err(dai->dev, "%s invalid bit width given : %d\n",
0053 __func__, bitwidth);
0054 return -EINVAL;
0055 }
0056
0057 switch (rate) {
0058 case 32000:
0059 sampling_freq = LPASS_SAMPLING_FREQ32;
0060 break;
0061 case 44100:
0062 sampling_freq = LPASS_SAMPLING_FREQ44;
0063 break;
0064 case 48000:
0065 sampling_freq = LPASS_SAMPLING_FREQ48;
0066 break;
0067 default:
0068 dev_err(dai->dev, "%s invalid bit width given : %d\n",
0069 __func__, bitwidth);
0070 return -EINVAL;
0071 }
0072 data_format = LPASS_DATA_FORMAT_LINEAR;
0073 ch_sts_buf0 = (((data_format << LPASS_DATA_FORMAT_SHIFT) & LPASS_DATA_FORMAT_MASK)
0074 | ((sampling_freq << LPASS_FREQ_BIT_SHIFT) & LPASS_FREQ_BIT_MASK));
0075 ch_sts_buf1 = (word_length) & LPASS_WORDLENGTH_MASK;
0076
0077 ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_RESET);
0078 if (ret)
0079 return ret;
0080
0081 ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_CLEAR);
0082 if (ret)
0083 return ret;
0084
0085 ret = regmap_field_write(drvdata->hdmitx_legacy_en, LPASS_HDMITX_LEGACY_DISABLE);
0086 if (ret)
0087 return ret;
0088
0089 ret = regmap_field_write(drvdata->hdmitx_parity_calc_en, HDMITX_PARITY_CALC_EN);
0090 if (ret)
0091 return ret;
0092
0093 ret = regmap_field_write(drvdata->vbit_ctl->replace_vbit, REPLACE_VBIT);
0094 if (ret)
0095 return ret;
0096
0097 ret = regmap_field_write(drvdata->vbit_ctl->vbit_stream, LINEAR_PCM_DATA);
0098 if (ret)
0099 return ret;
0100
0101 ret = regmap_field_write(drvdata->hdmitx_ch_msb[0], ch_sts_buf1);
0102 if (ret)
0103 return ret;
0104
0105 ret = regmap_field_write(drvdata->hdmitx_ch_lsb[0], ch_sts_buf0);
0106 if (ret)
0107 return ret;
0108
0109 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_chs, HW_MODE);
0110 if (ret)
0111 return ret;
0112
0113 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);
0114 if (ret)
0115 return ret;
0116
0117 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_usr, HW_MODE);
0118 if (ret)
0119 return ret;
0120
0121 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);
0122 if (ret)
0123 return ret;
0124
0125 ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
0126 if (ret)
0127 return ret;
0128
0129 ret = regmap_field_write(meta_ctl->as_sdp_cc, channels - 1);
0130 if (ret)
0131 return ret;
0132
0133 ret = regmap_field_write(meta_ctl->as_sdp_ct, LPASS_META_DEFAULT_VAL);
0134 if (ret)
0135 return ret;
0136
0137 ret = regmap_field_write(meta_ctl->aif_db4, LPASS_META_DEFAULT_VAL);
0138 if (ret)
0139 return ret;
0140
0141 ret = regmap_field_write(meta_ctl->frequency, sampling_freq);
0142 if (ret)
0143 return ret;
0144
0145 ret = regmap_field_write(meta_ctl->mst_index, LPASS_META_DEFAULT_VAL);
0146 if (ret)
0147 return ret;
0148
0149 ret = regmap_field_write(meta_ctl->dptx_index, LPASS_META_DEFAULT_VAL);
0150 if (ret)
0151 return ret;
0152
0153 ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
0154 if (ret)
0155 return ret;
0156
0157 ret = regmap_field_write(sstream_ctl->dma_sel, ch);
0158 if (ret)
0159 return ret;
0160
0161 ret = regmap_field_write(sstream_ctl->auto_bbit_en, LPASS_SSTREAM_DEFAULT_ENABLE);
0162 if (ret)
0163 return ret;
0164
0165 ret = regmap_field_write(sstream_ctl->layout, LPASS_SSTREAM_DEFAULT_DISABLE);
0166 if (ret)
0167 return ret;
0168
0169 ret = regmap_field_write(sstream_ctl->layout_sp, LPASS_LAYOUT_SP_DEFAULT);
0170 if (ret)
0171 return ret;
0172
0173 ret = regmap_field_write(sstream_ctl->dp_audio, LPASS_SSTREAM_DEFAULT_ENABLE);
0174 if (ret)
0175 return ret;
0176
0177 ret = regmap_field_write(sstream_ctl->set_sp_on_en, LPASS_SSTREAM_DEFAULT_ENABLE);
0178 if (ret)
0179 return ret;
0180
0181 ret = regmap_field_write(sstream_ctl->dp_sp_b_hw_en, LPASS_SSTREAM_DEFAULT_ENABLE);
0182 if (ret)
0183 return ret;
0184
0185 ret = regmap_field_write(sstream_ctl->dp_staffing_en, LPASS_SSTREAM_DEFAULT_ENABLE);
0186
0187 return ret;
0188 }
0189
0190 static int lpass_hdmi_daiops_prepare(struct snd_pcm_substream *substream,
0191 struct snd_soc_dai *dai)
0192 {
0193 int ret;
0194 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
0195
0196 ret = regmap_field_write(drvdata->sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
0197 if (ret)
0198 return ret;
0199
0200 ret = regmap_field_write(drvdata->meta_ctl->mute, LPASS_MUTE_DISABLE);
0201
0202 return ret;
0203 }
0204
0205 static int lpass_hdmi_daiops_trigger(struct snd_pcm_substream *substream,
0206 int cmd, struct snd_soc_dai *dai)
0207 {
0208 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
0209 struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
0210 struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
0211 int ret = -EINVAL;
0212
0213 switch (cmd) {
0214 case SNDRV_PCM_TRIGGER_START:
0215 case SNDRV_PCM_TRIGGER_RESUME:
0216 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0217 ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
0218 if (ret)
0219 return ret;
0220
0221 ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_DISABLE);
0222 if (ret)
0223 return ret;
0224
0225 break;
0226 case SNDRV_PCM_TRIGGER_STOP:
0227 case SNDRV_PCM_TRIGGER_SUSPEND:
0228 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0229 ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
0230 if (ret)
0231 return ret;
0232
0233 ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
0234 if (ret)
0235 return ret;
0236
0237 ret = regmap_field_write(sstream_ctl->dp_audio, 0);
0238 if (ret)
0239 return ret;
0240
0241 break;
0242 }
0243 return ret;
0244 }
0245
0246 const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops = {
0247 .hw_params = lpass_hdmi_daiops_hw_params,
0248 .prepare = lpass_hdmi_daiops_prepare,
0249 .trigger = lpass_hdmi_daiops_trigger,
0250 };
0251 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_hdmi_dai_ops);
0252
0253 MODULE_DESCRIPTION("QTi LPASS HDMI Driver");
0254 MODULE_LICENSE("GPL v2");
