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0009 #include <linux/clk.h>
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <sound/pcm.h>
0017 #include <sound/pcm_params.h>
0018 #include <sound/soc.h>
0019 #include <sound/soc-dai.h>
0020
0021 #include <dt-bindings/sound/apq8016-lpass.h>
0022 #include "lpass-lpaif-reg.h"
0023 #include "lpass.h"
0024
0025 static struct snd_soc_dai_driver apq8016_lpass_cpu_dai_driver[] = {
0026 [MI2S_PRIMARY] = {
0027 .id = MI2S_PRIMARY,
0028 .name = "Primary MI2S",
0029 .playback = {
0030 .stream_name = "Primary Playback",
0031 .formats = SNDRV_PCM_FMTBIT_S16 |
0032 SNDRV_PCM_FMTBIT_S24 |
0033 SNDRV_PCM_FMTBIT_S32,
0034 .rates = SNDRV_PCM_RATE_8000 |
0035 SNDRV_PCM_RATE_16000 |
0036 SNDRV_PCM_RATE_32000 |
0037 SNDRV_PCM_RATE_48000 |
0038 SNDRV_PCM_RATE_96000,
0039 .rate_min = 8000,
0040 .rate_max = 96000,
0041 .channels_min = 1,
0042 .channels_max = 8,
0043 },
0044 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0045 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0046 },
0047 [MI2S_SECONDARY] = {
0048 .id = MI2S_SECONDARY,
0049 .name = "Secondary MI2S",
0050 .playback = {
0051 .stream_name = "Secondary Playback",
0052 .formats = SNDRV_PCM_FMTBIT_S16 |
0053 SNDRV_PCM_FMTBIT_S24 |
0054 SNDRV_PCM_FMTBIT_S32,
0055 .rates = SNDRV_PCM_RATE_8000 |
0056 SNDRV_PCM_RATE_16000 |
0057 SNDRV_PCM_RATE_32000 |
0058 SNDRV_PCM_RATE_48000 |
0059 SNDRV_PCM_RATE_96000,
0060 .rate_min = 8000,
0061 .rate_max = 96000,
0062 .channels_min = 1,
0063 .channels_max = 8,
0064 },
0065 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0066 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0067 },
0068 [MI2S_TERTIARY] = {
0069 .id = MI2S_TERTIARY,
0070 .name = "Tertiary MI2S",
0071 .capture = {
0072 .stream_name = "Tertiary Capture",
0073 .formats = SNDRV_PCM_FMTBIT_S16 |
0074 SNDRV_PCM_FMTBIT_S24 |
0075 SNDRV_PCM_FMTBIT_S32,
0076 .rates = SNDRV_PCM_RATE_8000 |
0077 SNDRV_PCM_RATE_16000 |
0078 SNDRV_PCM_RATE_32000 |
0079 SNDRV_PCM_RATE_48000 |
0080 SNDRV_PCM_RATE_96000,
0081 .rate_min = 8000,
0082 .rate_max = 96000,
0083 .channels_min = 1,
0084 .channels_max = 8,
0085 },
0086 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0087 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0088 },
0089 [MI2S_QUATERNARY] = {
0090 .id = MI2S_QUATERNARY,
0091 .name = "Quatenary MI2S",
0092 .playback = {
0093 .stream_name = "Quatenary Playback",
0094 .formats = SNDRV_PCM_FMTBIT_S16 |
0095 SNDRV_PCM_FMTBIT_S24 |
0096 SNDRV_PCM_FMTBIT_S32,
0097 .rates = SNDRV_PCM_RATE_8000 |
0098 SNDRV_PCM_RATE_16000 |
0099 SNDRV_PCM_RATE_32000 |
0100 SNDRV_PCM_RATE_48000 |
0101 SNDRV_PCM_RATE_96000,
0102 .rate_min = 8000,
0103 .rate_max = 96000,
0104 .channels_min = 1,
0105 .channels_max = 8,
0106 },
0107 .capture = {
0108 .stream_name = "Quatenary Capture",
0109 .formats = SNDRV_PCM_FMTBIT_S16 |
0110 SNDRV_PCM_FMTBIT_S24 |
0111 SNDRV_PCM_FMTBIT_S32,
0112 .rates = SNDRV_PCM_RATE_8000 |
0113 SNDRV_PCM_RATE_16000 |
0114 SNDRV_PCM_RATE_32000 |
0115 SNDRV_PCM_RATE_48000 |
0116 SNDRV_PCM_RATE_96000,
0117 .rate_min = 8000,
0118 .rate_max = 96000,
0119 .channels_min = 1,
0120 .channels_max = 8,
0121 },
0122 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0123 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0124 },
0125 };
0126
0127 static int apq8016_lpass_alloc_dma_channel(struct lpass_data *drvdata,
0128 int direction, unsigned int dai_id)
0129 {
0130 struct lpass_variant *v = drvdata->variant;
0131 int chan = 0;
0132
0133 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0134 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
0135 v->rdma_channels);
0136
0137 if (chan >= v->rdma_channels)
0138 return -EBUSY;
0139 } else {
0140 chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
0141 v->wrdma_channel_start +
0142 v->wrdma_channels,
0143 v->wrdma_channel_start);
0144
0145 if (chan >= v->wrdma_channel_start + v->wrdma_channels)
0146 return -EBUSY;
0147 }
0148
0149 set_bit(chan, &drvdata->dma_ch_bit_map);
0150
0151 return chan;
0152 }
0153
0154 static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
0155 {
0156 clear_bit(chan, &drvdata->dma_ch_bit_map);
0157
0158 return 0;
0159 }
0160
0161 static int apq8016_lpass_init(struct platform_device *pdev)
0162 {
0163 struct lpass_data *drvdata = platform_get_drvdata(pdev);
0164 struct lpass_variant *variant = drvdata->variant;
0165 struct device *dev = &pdev->dev;
0166 int ret, i;
0167
0168
0169 drvdata->clks = devm_kcalloc(dev, variant->num_clks,
0170 sizeof(*drvdata->clks), GFP_KERNEL);
0171 if (!drvdata->clks)
0172 return -ENOMEM;
0173 drvdata->num_clks = variant->num_clks;
0174
0175 for (i = 0; i < drvdata->num_clks; i++)
0176 drvdata->clks[i].id = variant->clk_name[i];
0177
0178 ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
0179 if (ret) {
0180 dev_err(dev, "Failed to get clocks %d\n", ret);
0181 return ret;
0182 }
0183
0184 ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
0185 if (ret) {
0186 dev_err(dev, "apq8016 clk_enable failed\n");
0187 return ret;
0188 }
0189
0190 drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
0191 if (IS_ERR(drvdata->ahbix_clk)) {
0192 dev_err(dev, "error getting ahbix-clk: %ld\n",
0193 PTR_ERR(drvdata->ahbix_clk));
0194 ret = PTR_ERR(drvdata->ahbix_clk);
0195 goto err_ahbix_clk;
0196 }
0197
0198 ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
0199 if (ret) {
0200 dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
0201 goto err_ahbix_clk;
0202 }
0203 dev_dbg(dev, "set ahbix_clk rate to %lu\n",
0204 clk_get_rate(drvdata->ahbix_clk));
0205
0206 ret = clk_prepare_enable(drvdata->ahbix_clk);
0207 if (ret) {
0208 dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
0209 goto err_ahbix_clk;
0210 }
0211
0212 return 0;
0213
0214 err_ahbix_clk:
0215 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
0216 return ret;
0217 }
0218
0219 static int apq8016_lpass_exit(struct platform_device *pdev)
0220 {
0221 struct lpass_data *drvdata = platform_get_drvdata(pdev);
0222
0223 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
0224 clk_disable_unprepare(drvdata->ahbix_clk);
0225
0226 return 0;
0227 }
0228
0229
0230 static struct lpass_variant apq8016_data = {
0231 .i2sctrl_reg_base = 0x1000,
0232 .i2sctrl_reg_stride = 0x1000,
0233 .i2s_ports = 4,
0234 .irq_reg_base = 0x6000,
0235 .irq_reg_stride = 0x1000,
0236 .irq_ports = 3,
0237 .rdma_reg_base = 0x8400,
0238 .rdma_reg_stride = 0x1000,
0239 .rdma_channels = 2,
0240 .dmactl_audif_start = 1,
0241 .wrdma_reg_base = 0xB000,
0242 .wrdma_reg_stride = 0x1000,
0243 .wrdma_channel_start = 5,
0244 .wrdma_channels = 2,
0245 .loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
0246 .spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
0247 .spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
0248 .spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
0249 .micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
0250 .micmode = REG_FIELD_ID(0x1000, 4, 7, 4, 0x1000),
0251 .micmono = REG_FIELD_ID(0x1000, 3, 3, 4, 0x1000),
0252 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 4, 0x1000),
0253 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 4, 0x1000),
0254
0255 .rdma_dyncclk = REG_FIELD_ID(0x8400, 12, 12, 2, 0x1000),
0256 .rdma_bursten = REG_FIELD_ID(0x8400, 11, 11, 2, 0x1000),
0257 .rdma_wpscnt = REG_FIELD_ID(0x8400, 8, 10, 2, 0x1000),
0258 .rdma_intf = REG_FIELD_ID(0x8400, 4, 7, 2, 0x1000),
0259 .rdma_fifowm = REG_FIELD_ID(0x8400, 1, 3, 2, 0x1000),
0260 .rdma_enable = REG_FIELD_ID(0x8400, 0, 0, 2, 0x1000),
0261
0262 .wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 2, 0x1000),
0263 .wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 2, 0x1000),
0264 .wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 2, 0x1000),
0265 .wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 2, 0x1000),
0266 .wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 2, 0x1000),
0267 .wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 2, 0x1000),
0268
0269 .clk_name = (const char*[]) {
0270 "pcnoc-mport-clk",
0271 "pcnoc-sway-clk",
0272 },
0273 .num_clks = 2,
0274 .dai_driver = apq8016_lpass_cpu_dai_driver,
0275 .num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
0276 .dai_osr_clk_names = (const char *[]) {
0277 "mi2s-osr-clk0",
0278 "mi2s-osr-clk1",
0279 "mi2s-osr-clk2",
0280 "mi2s-osr-clk3",
0281 },
0282 .dai_bit_clk_names = (const char *[]) {
0283 "mi2s-bit-clk0",
0284 "mi2s-bit-clk1",
0285 "mi2s-bit-clk2",
0286 "mi2s-bit-clk3",
0287 },
0288 .init = apq8016_lpass_init,
0289 .exit = apq8016_lpass_exit,
0290 .alloc_dma_channel = apq8016_lpass_alloc_dma_channel,
0291 .free_dma_channel = apq8016_lpass_free_dma_channel,
0292 };
0293
0294 static const struct of_device_id apq8016_lpass_cpu_device_id[] __maybe_unused = {
0295 { .compatible = "qcom,lpass-cpu-apq8016", .data = &apq8016_data },
0296 { .compatible = "qcom,apq8016-lpass-cpu", .data = &apq8016_data },
0297 {}
0298 };
0299 MODULE_DEVICE_TABLE(of, apq8016_lpass_cpu_device_id);
0300
0301 static struct platform_driver apq8016_lpass_cpu_platform_driver = {
0302 .driver = {
0303 .name = "apq8016-lpass-cpu",
0304 .of_match_table = of_match_ptr(apq8016_lpass_cpu_device_id),
0305 },
0306 .probe = asoc_qcom_lpass_cpu_platform_probe,
0307 .remove = asoc_qcom_lpass_cpu_platform_remove,
0308 };
0309 module_platform_driver(apq8016_lpass_cpu_platform_driver);
0310
0311 MODULE_DESCRIPTION("APQ8016 LPASS CPU Driver");
0312 MODULE_LICENSE("GPL v2");
0313
