soc/pxa/pxa-ssp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * pxa-ssp.c  --  ALSA Soc Audio Layer
0004  *
0005  * Copyright 2005,2008 Wolfson Microelectronics PLC.
0006  * Author: Liam Girdwood
0007  *         Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  *
0009  * TODO:
0010  *  o Test network mode for > 16bit sample size
0011  */
0012
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/slab.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/clk.h>
0018 #include <linux/io.h>
0019 #include <linux/pxa2xx_ssp.h>
0020 #include <linux/of.h>
0021 #include <linux/dmaengine.h>
0022
0023 #include <asm/irq.h>
0024
0025 #include <sound/core.h>
0026 #include <sound/pcm.h>
0027 #include <sound/initval.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/soc.h>
0030 #include <sound/pxa2xx-lib.h>
0031 #include <sound/dmaengine_pcm.h>
0032
0033 #include "pxa-ssp.h"
0034
0035 /*
0036  * SSP audio private data
0037  */
0038 struct ssp_priv {
0039     struct ssp_device *ssp;
0040     struct clk *extclk;
0041     unsigned long ssp_clk;
0042     unsigned int sysclk;
0043     unsigned int dai_fmt;
0044     unsigned int configured_dai_fmt;
0045 #ifdef CONFIG_PM
0046     uint32_t    cr0;
0047     uint32_t    cr1;
0048     uint32_t    to;
0049     uint32_t    psp;
0050 #endif
0051 };
0052
0053 static void dump_registers(struct ssp_device *ssp)
0054 {
0055     dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
0056          pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
0057          pxa_ssp_read_reg(ssp, SSTO));
0058
0059     dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
0060          pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
0061          pxa_ssp_read_reg(ssp, SSACD));
0062 }
0063
0064 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
0065             int out, struct snd_dmaengine_dai_dma_data *dma)
0066 {
0067     dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
0068                    DMA_SLAVE_BUSWIDTH_2_BYTES;
0069     dma->maxburst = 16;
0070     dma->addr = ssp->phys_base + SSDR;
0071 }
0072
0073 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
0074                struct snd_soc_dai *cpu_dai)
0075 {
0076     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0077     struct ssp_device *ssp = priv->ssp;
0078     struct snd_dmaengine_dai_dma_data *dma;
0079     int ret = 0;
0080
0081     if (!snd_soc_dai_active(cpu_dai)) {
0082         clk_prepare_enable(ssp->clk);
0083         pxa_ssp_disable(ssp);
0084     }
0085
0086     clk_prepare_enable(priv->extclk);
0087
0088     dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
0089     if (!dma)
0090         return -ENOMEM;
0091     dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
0092         "tx" : "rx";
0093
0094     snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
0095
0096     return ret;
0097 }
0098
0099 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
0100                  struct snd_soc_dai *cpu_dai)
0101 {
0102     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0103     struct ssp_device *ssp = priv->ssp;
0104
0105     if (!snd_soc_dai_active(cpu_dai)) {
0106         pxa_ssp_disable(ssp);
0107         clk_disable_unprepare(ssp->clk);
0108     }
0109
0110     clk_disable_unprepare(priv->extclk);
0111
0112     kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
0113     snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
0114 }
0115
0116 #ifdef CONFIG_PM
0117
0118 static int pxa_ssp_suspend(struct snd_soc_component *component)
0119 {
0120     struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
0121     struct ssp_device *ssp = priv->ssp;
0122
0123     if (!snd_soc_component_active(component))
0124         clk_prepare_enable(ssp->clk);
0125
0126     priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
0127     priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
0128     priv->to  = __raw_readl(ssp->mmio_base + SSTO);
0129     priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
0130
0131     pxa_ssp_disable(ssp);
0132     clk_disable_unprepare(ssp->clk);
0133     return 0;
0134 }
0135
0136 static int pxa_ssp_resume(struct snd_soc_component *component)
0137 {
0138     struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
0139     struct ssp_device *ssp = priv->ssp;
0140     uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
0141
0142     clk_prepare_enable(ssp->clk);
0143
0144     __raw_writel(sssr, ssp->mmio_base + SSSR);
0145     __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
0146     __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
0147     __raw_writel(priv->to,  ssp->mmio_base + SSTO);
0148     __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
0149
0150     if (snd_soc_component_active(component))
0151         pxa_ssp_enable(ssp);
0152     else
0153         clk_disable_unprepare(ssp->clk);
0154
0155     return 0;
0156 }
0157
0158 #else
0159 #define pxa_ssp_suspend NULL
0160 #define pxa_ssp_resume  NULL
0161 #endif
0162
0163 /*
0164  * ssp_set_clkdiv - set SSP clock divider
0165  * @div: serial clock rate divider
0166  */
0167 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
0168 {
0169     u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
0170
0171     if (ssp->type == PXA25x_SSP) {
0172         sscr0 &= ~0x0000ff00;
0173         sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
0174     } else {
0175         sscr0 &= ~0x000fff00;
0176         sscr0 |= (div - 1) << 8;     /* 1..4096 */
0177     }
0178     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0179 }
0180
0181 /*
0182  * Set the SSP ports SYSCLK.
0183  */
0184 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
0185     int clk_id, unsigned int freq, int dir)
0186 {
0187     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0188     struct ssp_device *ssp = priv->ssp;
0189
0190     u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
0191         ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
0192
0193     if (priv->extclk) {
0194         int ret;
0195
0196         /*
0197          * For DT based boards, if an extclk is given, use it
0198          * here and configure PXA_SSP_CLK_EXT.
0199          */
0200
0201         ret = clk_set_rate(priv->extclk, freq);
0202         if (ret < 0)
0203             return ret;
0204
0205         clk_id = PXA_SSP_CLK_EXT;
0206     }
0207
0208     dev_dbg(ssp->dev,
0209         "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
0210         cpu_dai->id, clk_id, freq);
0211
0212     switch (clk_id) {
0213     case PXA_SSP_CLK_NET_PLL:
0214         sscr0 |= SSCR0_MOD;
0215         break;
0216     case PXA_SSP_CLK_PLL:
0217         /* Internal PLL is fixed */
0218         if (ssp->type == PXA25x_SSP)
0219             priv->sysclk = 1843200;
0220         else
0221             priv->sysclk = 13000000;
0222         break;
0223     case PXA_SSP_CLK_EXT:
0224         priv->sysclk = freq;
0225         sscr0 |= SSCR0_ECS;
0226         break;
0227     case PXA_SSP_CLK_NET:
0228         priv->sysclk = freq;
0229         sscr0 |= SSCR0_NCS | SSCR0_MOD;
0230         break;
0231     case PXA_SSP_CLK_AUDIO:
0232         priv->sysclk = 0;
0233         pxa_ssp_set_scr(ssp, 1);
0234         sscr0 |= SSCR0_ACS;
0235         break;
0236     default:
0237         return -ENODEV;
0238     }
0239
0240     /* The SSP clock must be disabled when changing SSP clock mode
0241      * on PXA2xx.  On PXA3xx it must be enabled when doing so. */
0242     if (ssp->type != PXA3xx_SSP)
0243         clk_disable_unprepare(ssp->clk);
0244     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0245     if (ssp->type != PXA3xx_SSP)
0246         clk_prepare_enable(ssp->clk);
0247
0248     return 0;
0249 }
0250
0251 /*
0252  * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
0253  */
0254 static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
0255 {
0256     struct ssp_device *ssp = priv->ssp;
0257     u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
0258
0259     if (ssp->type == PXA3xx_SSP)
0260         pxa_ssp_write_reg(ssp, SSACDD, 0);
0261
0262     switch (freq) {
0263     case 5622000:
0264         break;
0265     case 11345000:
0266         ssacd |= (0x1 << 4);
0267         break;
0268     case 12235000:
0269         ssacd |= (0x2 << 4);
0270         break;
0271     case 14857000:
0272         ssacd |= (0x3 << 4);
0273         break;
0274     case 32842000:
0275         ssacd |= (0x4 << 4);
0276         break;
0277     case 48000000:
0278         ssacd |= (0x5 << 4);
0279         break;
0280     case 0:
0281         /* Disable */
0282         break;
0283
0284     default:
0285         /* PXA3xx has a clock ditherer which can be used to generate
0286          * a wider range of frequencies - calculate a value for it.
0287          */
0288         if (ssp->type == PXA3xx_SSP) {
0289             u32 val;
0290             u64 tmp = 19968;
0291
0292             tmp *= 1000000;
0293             do_div(tmp, freq);
0294             val = tmp;
0295
0296             val = (val << 16) | 64;
0297             pxa_ssp_write_reg(ssp, SSACDD, val);
0298
0299             ssacd |= (0x6 << 4);
0300
0301             dev_dbg(ssp->dev,
0302                 "Using SSACDD %x to supply %uHz\n",
0303                 val, freq);
0304             break;
0305         }
0306
0307         return -EINVAL;
0308     }
0309
0310     pxa_ssp_write_reg(ssp, SSACD, ssacd);
0311
0312     return 0;
0313 }
0314
0315 /*
0316  * Set the active slots in TDM/Network mode
0317  */
0318 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
0319     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
0320 {
0321     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0322     struct ssp_device *ssp = priv->ssp;
0323     u32 sscr0;
0324
0325     sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
0326     sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
0327
0328     /* set slot width */
0329     if (slot_width > 16)
0330         sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
0331     else
0332         sscr0 |= SSCR0_DataSize(slot_width);
0333
0334     if (slots > 1) {
0335         /* enable network mode */
0336         sscr0 |= SSCR0_MOD;
0337
0338         /* set number of active slots */
0339         sscr0 |= SSCR0_SlotsPerFrm(slots);
0340
0341         /* set active slot mask */
0342         pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
0343         pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
0344     }
0345     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0346
0347     return 0;
0348 }
0349
0350 /*
0351  * Tristate the SSP DAI lines
0352  */
0353 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
0354     int tristate)
0355 {
0356     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0357     struct ssp_device *ssp = priv->ssp;
0358     u32 sscr1;
0359
0360     sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
0361     if (tristate)
0362         sscr1 &= ~SSCR1_TTE;
0363     else
0364         sscr1 |= SSCR1_TTE;
0365     pxa_ssp_write_reg(ssp, SSCR1, sscr1);
0366
0367     return 0;
0368 }
0369
0370 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
0371                    unsigned int fmt)
0372 {
0373     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0374
0375     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0376     case SND_SOC_DAIFMT_BC_FC:
0377     case SND_SOC_DAIFMT_BC_FP:
0378     case SND_SOC_DAIFMT_BP_FP:
0379         break;
0380     default:
0381         return -EINVAL;
0382     }
0383
0384     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0385     case SND_SOC_DAIFMT_NB_NF:
0386     case SND_SOC_DAIFMT_NB_IF:
0387     case SND_SOC_DAIFMT_IB_IF:
0388     case SND_SOC_DAIFMT_IB_NF:
0389         break;
0390     default:
0391         return -EINVAL;
0392     }
0393
0394     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0395     case SND_SOC_DAIFMT_I2S:
0396     case SND_SOC_DAIFMT_DSP_A:
0397     case SND_SOC_DAIFMT_DSP_B:
0398         break;
0399
0400     default:
0401         return -EINVAL;
0402     }
0403
0404     /* Settings will be applied in hw_params() */
0405     priv->dai_fmt = fmt;
0406
0407     return 0;
0408 }
0409
0410 /*
0411  * Set up the SSP DAI format.
0412  * The SSP Port must be inactive before calling this function as the
0413  * physical interface format is changed.
0414  */
0415 static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
0416 {
0417     struct ssp_device *ssp = priv->ssp;
0418     u32 sscr0, sscr1, sspsp, scfr;
0419
0420     /* check if we need to change anything at all */
0421     if (priv->configured_dai_fmt == priv->dai_fmt)
0422         return 0;
0423
0424     /* reset port settings */
0425     sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
0426         ~(SSCR0_PSP | SSCR0_MOD);
0427     sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
0428         ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
0429           SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
0430     sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
0431         ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
0432
0433     sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
0434
0435     switch (priv->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0436     case SND_SOC_DAIFMT_BC_FC:
0437         sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
0438         break;
0439     case SND_SOC_DAIFMT_BC_FP:
0440         sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
0441         break;
0442     case SND_SOC_DAIFMT_BP_FP:
0443         break;
0444     default:
0445         return -EINVAL;
0446     }
0447
0448     switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
0449     case SND_SOC_DAIFMT_NB_NF:
0450         sspsp |= SSPSP_SFRMP;
0451         break;
0452     case SND_SOC_DAIFMT_NB_IF:
0453         break;
0454     case SND_SOC_DAIFMT_IB_IF:
0455         sspsp |= SSPSP_SCMODE(2);
0456         break;
0457     case SND_SOC_DAIFMT_IB_NF:
0458         sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
0459         break;
0460     default:
0461         return -EINVAL;
0462     }
0463
0464     switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0465     case SND_SOC_DAIFMT_I2S:
0466         sscr0 |= SSCR0_PSP;
0467         sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0468         /* See hw_params() */
0469         break;
0470
0471     case SND_SOC_DAIFMT_DSP_A:
0472         sspsp |= SSPSP_FSRT;
0473         fallthrough;
0474     case SND_SOC_DAIFMT_DSP_B:
0475         sscr0 |= SSCR0_MOD | SSCR0_PSP;
0476         sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
0477         break;
0478
0479     default:
0480         return -EINVAL;
0481     }
0482
0483     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0484     pxa_ssp_write_reg(ssp, SSCR1, sscr1);
0485     pxa_ssp_write_reg(ssp, SSPSP, sspsp);
0486
0487     switch (priv->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0488     case SND_SOC_DAIFMT_BC_FC:
0489     case SND_SOC_DAIFMT_BC_FP:
0490         scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
0491         pxa_ssp_write_reg(ssp, SSCR1, scfr);
0492
0493         while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
0494             cpu_relax();
0495         break;
0496     }
0497
0498     dump_registers(ssp);
0499
0500     /* Since we are configuring the timings for the format by hand
0501      * we have to defer some things until hw_params() where we
0502      * know parameters like the sample size.
0503      */
0504     priv->configured_dai_fmt = priv->dai_fmt;
0505
0506     return 0;
0507 }
0508
0509 struct pxa_ssp_clock_mode {
0510     int rate;
0511     int pll;
0512     u8 acds;
0513     u8 scdb;
0514 };
0515
0516 static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
0517     { .rate =  8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
0518     { .rate = 11025, .pll =  5622000, .acds = SSACD_ACDS_4,  .scdb = SSACD_SCDB_4X },
0519     { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
0520     { .rate = 22050, .pll =  5622000, .acds = SSACD_ACDS_2,  .scdb = SSACD_SCDB_4X },
0521     { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2,  .scdb = SSACD_SCDB_4X },
0522     { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2,  .scdb = SSACD_SCDB_4X },
0523     { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4,  .scdb = SSACD_SCDB_1X },
0524     {}
0525 };
0526
0527 /*
0528  * Set the SSP audio DMA parameters and sample size.
0529  * Can be called multiple times by oss emulation.
0530  */
0531 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
0532                 struct snd_pcm_hw_params *params,
0533                 struct snd_soc_dai *cpu_dai)
0534 {
0535     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0536     struct ssp_device *ssp = priv->ssp;
0537     int chn = params_channels(params);
0538     u32 sscr0, sspsp;
0539     int width = snd_pcm_format_physical_width(params_format(params));
0540     int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
0541     struct snd_dmaengine_dai_dma_data *dma_data;
0542     int rate = params_rate(params);
0543     int bclk = rate * chn * (width / 8);
0544     int ret;
0545
0546     dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
0547
0548     /* Network mode with one active slot (ttsa == 1) can be used
0549      * to force 16-bit frame width on the wire (for S16_LE), even
0550      * with two channels. Use 16-bit DMA transfers for this case.
0551      */
0552     pxa_ssp_set_dma_params(ssp,
0553         ((chn == 2) && (ttsa != 1)) || (width == 32),
0554         substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
0555
0556     /* we can only change the settings if the port is not in use */
0557     if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
0558         return 0;
0559
0560     ret = pxa_ssp_configure_dai_fmt(priv);
0561     if (ret < 0)
0562         return ret;
0563
0564     /* clear selected SSP bits */
0565     sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
0566
0567     /* bit size */
0568     switch (params_format(params)) {
0569     case SNDRV_PCM_FORMAT_S16_LE:
0570         if (ssp->type == PXA3xx_SSP)
0571             sscr0 |= SSCR0_FPCKE;
0572         sscr0 |= SSCR0_DataSize(16);
0573         break;
0574     case SNDRV_PCM_FORMAT_S24_LE:
0575         sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
0576         break;
0577     case SNDRV_PCM_FORMAT_S32_LE:
0578         sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
0579         break;
0580     }
0581     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0582
0583     if (sscr0 & SSCR0_ACS) {
0584         ret = pxa_ssp_set_pll(priv, bclk);
0585
0586         /*
0587          * If we were able to generate the bclk directly,
0588          * all is fine. Otherwise, look up the closest rate
0589          * from the table and also set the dividers.
0590          */
0591
0592         if (ret < 0) {
0593             const struct pxa_ssp_clock_mode *m;
0594             int ssacd, acds;
0595
0596             for (m = pxa_ssp_clock_modes; m->rate; m++) {
0597                 if (m->rate == rate)
0598                     break;
0599             }
0600
0601             if (!m->rate)
0602                 return -EINVAL;
0603
0604             acds = m->acds;
0605
0606             /* The values in the table are for 16 bits */
0607             if (width == 32)
0608                 acds--;
0609
0610             ret = pxa_ssp_set_pll(priv, bclk);
0611             if (ret < 0)
0612                 return ret;
0613
0614             ssacd = pxa_ssp_read_reg(ssp, SSACD);
0615             ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
0616             ssacd |= SSACD_ACDS(m->acds);
0617             ssacd |= m->scdb;
0618             pxa_ssp_write_reg(ssp, SSACD, ssacd);
0619         }
0620     } else if (sscr0 & SSCR0_ECS) {
0621         /*
0622          * For setups with external clocking, the PLL and its diviers
0623          * are not active. Instead, the SCR bits in SSCR0 can be used
0624          * to divide the clock.
0625          */
0626         pxa_ssp_set_scr(ssp, bclk / rate);
0627     }
0628
0629     switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0630     case SND_SOC_DAIFMT_I2S:
0631            sspsp = pxa_ssp_read_reg(ssp, SSPSP);
0632
0633         if (((priv->sysclk / bclk) == 64) && (width == 16)) {
0634             /* This is a special case where the bitclk is 64fs
0635              * and we're not dealing with 2*32 bits of audio
0636              * samples.
0637              *
0638              * The SSP values used for that are all found out by
0639              * trying and failing a lot; some of the registers
0640              * needed for that mode are only available on PXA3xx.
0641              */
0642             if (ssp->type != PXA3xx_SSP)
0643                 return -EINVAL;
0644
0645             sspsp |= SSPSP_SFRMWDTH(width * 2);
0646             sspsp |= SSPSP_SFRMDLY(width * 4);
0647             sspsp |= SSPSP_EDMYSTOP(3);
0648             sspsp |= SSPSP_DMYSTOP(3);
0649             sspsp |= SSPSP_DMYSTRT(1);
0650         } else {
0651             /* The frame width is the width the LRCLK is
0652              * asserted for; the delay is expressed in
0653              * half cycle units.  We need the extra cycle
0654              * because the data starts clocking out one BCLK
0655              * after LRCLK changes polarity.
0656              */
0657             sspsp |= SSPSP_SFRMWDTH(width + 1);
0658             sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
0659             sspsp |= SSPSP_DMYSTRT(1);
0660         }
0661
0662         pxa_ssp_write_reg(ssp, SSPSP, sspsp);
0663         break;
0664     default:
0665         break;
0666     }
0667
0668     /* When we use a network mode, we always require TDM slots
0669      * - complain loudly and fail if they've not been set up yet.
0670      */
0671     if ((sscr0 & SSCR0_MOD) && !ttsa) {
0672         dev_err(ssp->dev, "No TDM timeslot configured\n");
0673         return -EINVAL;
0674     }
0675
0676     dump_registers(ssp);
0677
0678     return 0;
0679 }
0680
0681 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
0682                     struct ssp_device *ssp, int value)
0683 {
0684     uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
0685     uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
0686     uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
0687     uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
0688
0689     if (value && (sscr0 & SSCR0_SSE))
0690         pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
0691
0692     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0693         if (value)
0694             sscr1 |= SSCR1_TSRE;
0695         else
0696             sscr1 &= ~SSCR1_TSRE;
0697     } else {
0698         if (value)
0699             sscr1 |= SSCR1_RSRE;
0700         else
0701             sscr1 &= ~SSCR1_RSRE;
0702     }
0703
0704     pxa_ssp_write_reg(ssp, SSCR1, sscr1);
0705
0706     if (value) {
0707         pxa_ssp_write_reg(ssp, SSSR, sssr);
0708         pxa_ssp_write_reg(ssp, SSPSP, sspsp);
0709         pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
0710     }
0711 }
0712
0713 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
0714                struct snd_soc_dai *cpu_dai)
0715 {
0716     int ret = 0;
0717     struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
0718     struct ssp_device *ssp = priv->ssp;
0719     int val;
0720
0721     switch (cmd) {
0722     case SNDRV_PCM_TRIGGER_RESUME:
0723         pxa_ssp_enable(ssp);
0724         break;
0725     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0726         pxa_ssp_set_running_bit(substream, ssp, 1);
0727         val = pxa_ssp_read_reg(ssp, SSSR);
0728         pxa_ssp_write_reg(ssp, SSSR, val);
0729         break;
0730     case SNDRV_PCM_TRIGGER_START:
0731         pxa_ssp_set_running_bit(substream, ssp, 1);
0732         break;
0733     case SNDRV_PCM_TRIGGER_STOP:
0734         pxa_ssp_set_running_bit(substream, ssp, 0);
0735         break;
0736     case SNDRV_PCM_TRIGGER_SUSPEND:
0737         pxa_ssp_disable(ssp);
0738         break;
0739     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0740         pxa_ssp_set_running_bit(substream, ssp, 0);
0741         break;
0742
0743     default:
0744         ret = -EINVAL;
0745     }
0746
0747     dump_registers(ssp);
0748
0749     return ret;
0750 }
0751
0752 static int pxa_ssp_probe(struct snd_soc_dai *dai)
0753 {
0754     struct device *dev = dai->dev;
0755     struct ssp_priv *priv;
0756     int ret;
0757
0758     priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
0759     if (!priv)
0760         return -ENOMEM;
0761
0762     if (dev->of_node) {
0763         struct device_node *ssp_handle;
0764
0765         ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
0766         if (!ssp_handle) {
0767             dev_err(dev, "unable to get 'port' phandle\n");
0768             ret = -ENODEV;
0769             goto err_priv;
0770         }
0771
0772         priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
0773         if (priv->ssp == NULL) {
0774             ret = -ENODEV;
0775             goto err_priv;
0776         }
0777
0778         priv->extclk = devm_clk_get(dev, "extclk");
0779         if (IS_ERR(priv->extclk)) {
0780             ret = PTR_ERR(priv->extclk);
0781             if (ret == -EPROBE_DEFER)
0782                 return ret;
0783
0784             priv->extclk = NULL;
0785         }
0786     } else {
0787         priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
0788         if (priv->ssp == NULL) {
0789             ret = -ENODEV;
0790             goto err_priv;
0791         }
0792     }
0793
0794     priv->dai_fmt = (unsigned int) -1;
0795     snd_soc_dai_set_drvdata(dai, priv);
0796
0797     return 0;
0798
0799 err_priv:
0800     kfree(priv);
0801     return ret;
0802 }
0803
0804 static int pxa_ssp_remove(struct snd_soc_dai *dai)
0805 {
0806     struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
0807
0808     pxa_ssp_free(priv->ssp);
0809     kfree(priv);
0810     return 0;
0811 }
0812
0813 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
0814               SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
0815               SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
0816               SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
0817               SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
0818
0819 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
0820
0821 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
0822     .startup    = pxa_ssp_startup,
0823     .shutdown   = pxa_ssp_shutdown,
0824     .trigger    = pxa_ssp_trigger,
0825     .hw_params  = pxa_ssp_hw_params,
0826     .set_sysclk = pxa_ssp_set_dai_sysclk,
0827     .set_fmt    = pxa_ssp_set_dai_fmt,
0828     .set_tdm_slot   = pxa_ssp_set_dai_tdm_slot,
0829     .set_tristate   = pxa_ssp_set_dai_tristate,
0830 };
0831
0832 static struct snd_soc_dai_driver pxa_ssp_dai = {
0833         .probe = pxa_ssp_probe,
0834         .remove = pxa_ssp_remove,
0835         .playback = {
0836             .channels_min = 1,
0837             .channels_max = 8,
0838             .rates = PXA_SSP_RATES,
0839             .formats = PXA_SSP_FORMATS,
0840         },
0841         .capture = {
0842              .channels_min = 1,
0843              .channels_max = 8,
0844             .rates = PXA_SSP_RATES,
0845             .formats = PXA_SSP_FORMATS,
0846          },
0847         .ops = &pxa_ssp_dai_ops,
0848 };
0849
0850 static const struct snd_soc_component_driver pxa_ssp_component = {
0851     .name           = "pxa-ssp",
0852     .pcm_construct      = pxa2xx_soc_pcm_new,
0853     .open           = pxa2xx_soc_pcm_open,
0854     .close          = pxa2xx_soc_pcm_close,
0855     .hw_params      = pxa2xx_soc_pcm_hw_params,
0856     .prepare        = pxa2xx_soc_pcm_prepare,
0857     .trigger        = pxa2xx_soc_pcm_trigger,
0858     .pointer        = pxa2xx_soc_pcm_pointer,
0859     .suspend        = pxa_ssp_suspend,
0860     .resume         = pxa_ssp_resume,
0861     .legacy_dai_naming  = 1,
0862 };
0863
0864 #ifdef CONFIG_OF
0865 static const struct of_device_id pxa_ssp_of_ids[] = {
0866     { .compatible = "mrvl,pxa-ssp-dai" },
0867     {}
0868 };
0869 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
0870 #endif
0871
0872 static int asoc_ssp_probe(struct platform_device *pdev)
0873 {
0874     return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
0875                            &pxa_ssp_dai, 1);
0876 }
0877
0878 static struct platform_driver asoc_ssp_driver = {
0879     .driver = {
0880         .name = "pxa-ssp-dai",
0881         .of_match_table = of_match_ptr(pxa_ssp_of_ids),
0882     },
0883
0884     .probe = asoc_ssp_probe,
0885 };
0886
0887 module_platform_driver(asoc_ssp_driver);
0888
0889 /* Module information */
0890 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
0891 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
0892 MODULE_LICENSE("GPL");
0893 MODULE_ALIAS("platform:pxa-ssp-dai");