soc/mxs/mxs-saif.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
0004  */
0005
0006
0007 #ifndef _MXS_SAIF_H
0008 #define _MXS_SAIF_H
0009
0010 #define SAIF_CTRL   0x0
0011 #define SAIF_STAT   0x10
0012 #define SAIF_DATA   0x20
0013 #define SAIF_VERSION    0X30
0014
0015 /* SAIF_CTRL */
0016 #define BM_SAIF_CTRL_SFTRST     0x80000000
0017 #define BM_SAIF_CTRL_CLKGATE        0x40000000
0018 #define BP_SAIF_CTRL_BITCLK_MULT_RATE   27
0019 #define BM_SAIF_CTRL_BITCLK_MULT_RATE   0x38000000
0020 #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
0021         (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
0022 #define BM_SAIF_CTRL_BITCLK_BASE_RATE   0x04000000
0023 #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN  0x02000000
0024 #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    0x01000000
0025 #define BP_SAIF_CTRL_RSRVD2     21
0026 #define BM_SAIF_CTRL_RSRVD2     0x00E00000
0027
0028 #define BP_SAIF_CTRL_DMAWAIT_COUNT  16
0029 #define BM_SAIF_CTRL_DMAWAIT_COUNT  0x001F0000
0030 #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
0031         (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
0032 #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
0033 #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
0034 #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
0035         (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
0036 #define BM_SAIF_CTRL_LRCLK_PULSE    0x00002000
0037 #define BM_SAIF_CTRL_BIT_ORDER      0x00001000
0038 #define BM_SAIF_CTRL_DELAY      0x00000800
0039 #define BM_SAIF_CTRL_JUSTIFY        0x00000400
0040 #define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200
0041 #define BM_SAIF_CTRL_BITCLK_EDGE    0x00000100
0042 #define BP_SAIF_CTRL_WORD_LENGTH    4
0043 #define BM_SAIF_CTRL_WORD_LENGTH    0x000000F0
0044 #define BF_SAIF_CTRL_WORD_LENGTH(v) \
0045         (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
0046 #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE    0x00000008
0047 #define BM_SAIF_CTRL_SLAVE_MODE     0x00000004
0048 #define BM_SAIF_CTRL_READ_MODE      0x00000002
0049 #define BM_SAIF_CTRL_RUN        0x00000001
0050
0051 /* SAIF_STAT */
0052 #define BM_SAIF_STAT_PRESENT        0x80000000
0053 #define BP_SAIF_STAT_RSRVD2     17
0054 #define BM_SAIF_STAT_RSRVD2     0x7FFE0000
0055 #define BF_SAIF_STAT_RSRVD2(v) \
0056         (((v) << 17) & BM_SAIF_STAT_RSRVD2)
0057 #define BM_SAIF_STAT_DMA_PREQ       0x00010000
0058 #define BP_SAIF_STAT_RSRVD1     7
0059 #define BM_SAIF_STAT_RSRVD1     0x0000FF80
0060 #define BF_SAIF_STAT_RSRVD1(v) \
0061         (((v) << 7) & BM_SAIF_STAT_RSRVD1)
0062
0063 #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
0064 #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ  0x00000020
0065 #define BM_SAIF_STAT_FIFO_SERVICE_IRQ   0x00000010
0066 #define BP_SAIF_STAT_RSRVD0     1
0067 #define BM_SAIF_STAT_RSRVD0     0x0000000E
0068 #define BF_SAIF_STAT_RSRVD0(v) \
0069         (((v) << 1) & BM_SAIF_STAT_RSRVD0)
0070 #define BM_SAIF_STAT_BUSY       0x00000001
0071
0072 /* SAFI_DATA */
0073 #define BP_SAIF_DATA_PCM_RIGHT      16
0074 #define BM_SAIF_DATA_PCM_RIGHT      0xFFFF0000
0075 #define BF_SAIF_DATA_PCM_RIGHT(v) \
0076         (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
0077 #define BP_SAIF_DATA_PCM_LEFT       0
0078 #define BM_SAIF_DATA_PCM_LEFT       0x0000FFFF
0079 #define BF_SAIF_DATA_PCM_LEFT(v)    \
0080         (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
0081
0082 /* SAIF_VERSION */
0083 #define BP_SAIF_VERSION_MAJOR       24
0084 #define BM_SAIF_VERSION_MAJOR       0xFF000000
0085 #define BF_SAIF_VERSION_MAJOR(v) \
0086         (((v) << 24) & BM_SAIF_VERSION_MAJOR)
0087 #define BP_SAIF_VERSION_MINOR       16
0088 #define BM_SAIF_VERSION_MINOR       0x00FF0000
0089 #define BF_SAIF_VERSION_MINOR(v) \
0090         (((v) << 16) & BM_SAIF_VERSION_MINOR)
0091 #define BP_SAIF_VERSION_STEP        0
0092 #define BM_SAIF_VERSION_STEP        0x0000FFFF
0093 #define BF_SAIF_VERSION_STEP(v) \
0094         (((v) << 0) & BM_SAIF_VERSION_STEP)
0095
0096 #define MXS_SAIF_MCLK       0
0097
0098 #include "mxs-pcm.h"
0099
0100 struct mxs_saif {
0101     struct device *dev;
0102     struct clk *clk;
0103     unsigned int mclk;
0104     unsigned int mclk_in_use;
0105     void __iomem *base;
0106     unsigned int id;
0107     unsigned int master_id;
0108     unsigned int cur_rate;
0109     unsigned int ongoing;
0110
0111     u32 fifo_underrun;
0112     u32 fifo_overrun;
0113
0114     enum {
0115         MXS_SAIF_STATE_STOPPED,
0116         MXS_SAIF_STATE_RUNNING,
0117     } state;
0118 };
0119
0120 extern int mxs_saif_put_mclk(unsigned int saif_id);
0121 extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
0122                     unsigned int rate);
0123 #endif