soc/mxs/mxs-saif.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2011 Freescale Semiconductor, Inc.
0004  */
0005
0006 #include <linux/module.h>
0007 #include <linux/init.h>
0008 #include <linux/of.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/slab.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/clk.h>
0014 #include <linux/clk-provider.h>
0015 #include <linux/delay.h>
0016 #include <linux/io.h>
0017 #include <linux/time.h>
0018 #include <sound/core.h>
0019 #include <sound/pcm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/soc.h>
0022
0023 #include "mxs-saif.h"
0024
0025 #define MXS_SET_ADDR    0x4
0026 #define MXS_CLR_ADDR    0x8
0027
0028 static struct mxs_saif *mxs_saif[2];
0029
0030 /*
0031  * SAIF is a little different with other normal SOC DAIs on clock using.
0032  *
0033  * For MXS, two SAIF modules are instantiated on-chip.
0034  * Each SAIF has a set of clock pins and can be operating in master
0035  * mode simultaneously if they are connected to different off-chip codecs.
0036  * Also, one of the two SAIFs can master or drive the clock pins while the
0037  * other SAIF, in slave mode, receives clocking from the master SAIF.
0038  * This also means that both SAIFs must operate at the same sample rate.
0039  *
0040  * We abstract this as each saif has a master, the master could be
0041  * itself or other saifs. In the generic saif driver, saif does not need
0042  * to know the different clkmux. Saif only needs to know who is its master
0043  * and operating its master to generate the proper clock rate for it.
0044  * The master id is provided in mach-specific layer according to different
0045  * clkmux setting.
0046  */
0047
0048 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
0049             int clk_id, unsigned int freq, int dir)
0050 {
0051     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0052
0053     switch (clk_id) {
0054     case MXS_SAIF_MCLK:
0055         saif->mclk = freq;
0056         break;
0057     default:
0058         return -EINVAL;
0059     }
0060     return 0;
0061 }
0062
0063 /*
0064  * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
0065  * is provided by other SAIF, we provide a interface here to get its master
0066  * from its master_id.
0067  * Note that the master could be itself.
0068  */
0069 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
0070 {
0071     return mxs_saif[saif->master_id];
0072 }
0073
0074 /*
0075  * Set SAIF clock and MCLK
0076  */
0077 static int mxs_saif_set_clk(struct mxs_saif *saif,
0078                   unsigned int mclk,
0079                   unsigned int rate)
0080 {
0081     u32 scr;
0082     int ret;
0083     struct mxs_saif *master_saif;
0084
0085     dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
0086
0087     /* Set master saif to generate proper clock */
0088     master_saif = mxs_saif_get_master(saif);
0089     if (!master_saif)
0090         return -EINVAL;
0091
0092     dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
0093
0094     /* Checking if can playback and capture simutaneously */
0095     if (master_saif->ongoing && rate != master_saif->cur_rate) {
0096         dev_err(saif->dev,
0097             "can not change clock, master saif%d(rate %d) is ongoing\n",
0098             master_saif->id, master_saif->cur_rate);
0099         return -EINVAL;
0100     }
0101
0102     scr = __raw_readl(master_saif->base + SAIF_CTRL);
0103     scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
0104     scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
0105
0106     /*
0107      * Set SAIF clock
0108      *
0109      * The SAIF clock should be either 384*fs or 512*fs.
0110      * If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
0111      *  For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
0112      *  For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
0113      *
0114      * If MCLK is not used, we just set saif clk to 512*fs.
0115      */
0116     ret = clk_prepare_enable(master_saif->clk);
0117     if (ret)
0118         return ret;
0119
0120     if (master_saif->mclk_in_use) {
0121         switch (mclk / rate) {
0122         case 32:
0123         case 64:
0124         case 128:
0125         case 256:
0126         case 512:
0127             scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
0128             ret = clk_set_rate(master_saif->clk, 512 * rate);
0129             break;
0130         case 48:
0131         case 96:
0132         case 192:
0133         case 384:
0134             scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
0135             ret = clk_set_rate(master_saif->clk, 384 * rate);
0136             break;
0137         default:
0138             /* SAIF MCLK should be a sub-rate of 512x or 384x */
0139             clk_disable_unprepare(master_saif->clk);
0140             return -EINVAL;
0141         }
0142     } else {
0143         ret = clk_set_rate(master_saif->clk, 512 * rate);
0144         scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
0145     }
0146
0147     clk_disable_unprepare(master_saif->clk);
0148
0149     if (ret)
0150         return ret;
0151
0152     master_saif->cur_rate = rate;
0153
0154     if (!master_saif->mclk_in_use) {
0155         __raw_writel(scr, master_saif->base + SAIF_CTRL);
0156         return 0;
0157     }
0158
0159     /*
0160      * Program the over-sample rate for MCLK output
0161      *
0162      * The available MCLK range is 32x, 48x... 512x. The rate
0163      * could be from 8kHz to 192kH.
0164      */
0165     switch (mclk / rate) {
0166     case 32:
0167         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
0168         break;
0169     case 64:
0170         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
0171         break;
0172     case 128:
0173         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
0174         break;
0175     case 256:
0176         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
0177         break;
0178     case 512:
0179         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
0180         break;
0181     case 48:
0182         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
0183         break;
0184     case 96:
0185         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
0186         break;
0187     case 192:
0188         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
0189         break;
0190     case 384:
0191         scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
0192         break;
0193     default:
0194         return -EINVAL;
0195     }
0196
0197     __raw_writel(scr, master_saif->base + SAIF_CTRL);
0198
0199     return 0;
0200 }
0201
0202 /*
0203  * Put and disable MCLK.
0204  */
0205 int mxs_saif_put_mclk(unsigned int saif_id)
0206 {
0207     struct mxs_saif *saif = mxs_saif[saif_id];
0208     u32 stat;
0209
0210     if (!saif)
0211         return -EINVAL;
0212
0213     stat = __raw_readl(saif->base + SAIF_STAT);
0214     if (stat & BM_SAIF_STAT_BUSY) {
0215         dev_err(saif->dev, "error: busy\n");
0216         return -EBUSY;
0217     }
0218
0219     clk_disable_unprepare(saif->clk);
0220
0221     /* disable MCLK output */
0222     __raw_writel(BM_SAIF_CTRL_CLKGATE,
0223         saif->base + SAIF_CTRL + MXS_SET_ADDR);
0224     __raw_writel(BM_SAIF_CTRL_RUN,
0225         saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0226
0227     saif->mclk_in_use = 0;
0228     return 0;
0229 }
0230 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
0231
0232 /*
0233  * Get MCLK and set clock rate, then enable it
0234  *
0235  * This interface is used for codecs who are using MCLK provided
0236  * by saif.
0237  */
0238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
0239                     unsigned int rate)
0240 {
0241     struct mxs_saif *saif = mxs_saif[saif_id];
0242     u32 stat;
0243     int ret;
0244     struct mxs_saif *master_saif;
0245
0246     if (!saif)
0247         return -EINVAL;
0248
0249     /* Clear Reset */
0250     __raw_writel(BM_SAIF_CTRL_SFTRST,
0251         saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0252
0253     /* FIXME: need clear clk gate for register r/w */
0254     __raw_writel(BM_SAIF_CTRL_CLKGATE,
0255         saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0256
0257     master_saif = mxs_saif_get_master(saif);
0258     if (saif != master_saif) {
0259         dev_err(saif->dev, "can not get mclk from a non-master saif\n");
0260         return -EINVAL;
0261     }
0262
0263     stat = __raw_readl(saif->base + SAIF_STAT);
0264     if (stat & BM_SAIF_STAT_BUSY) {
0265         dev_err(saif->dev, "error: busy\n");
0266         return -EBUSY;
0267     }
0268
0269     saif->mclk_in_use = 1;
0270     ret = mxs_saif_set_clk(saif, mclk, rate);
0271     if (ret)
0272         return ret;
0273
0274     ret = clk_prepare_enable(saif->clk);
0275     if (ret)
0276         return ret;
0277
0278     /* enable MCLK output */
0279     __raw_writel(BM_SAIF_CTRL_RUN,
0280         saif->base + SAIF_CTRL + MXS_SET_ADDR);
0281
0282     return 0;
0283 }
0284 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
0285
0286 /*
0287  * SAIF DAI format configuration.
0288  * Should only be called when port is inactive.
0289  */
0290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
0291 {
0292     u32 scr, stat;
0293     u32 scr0;
0294     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0295
0296     stat = __raw_readl(saif->base + SAIF_STAT);
0297     if (stat & BM_SAIF_STAT_BUSY) {
0298         dev_err(cpu_dai->dev, "error: busy\n");
0299         return -EBUSY;
0300     }
0301
0302     /* If SAIF1 is configured as slave, the clk gate needs to be cleared
0303      * before the register can be written.
0304      */
0305     if (saif->id != saif->master_id) {
0306         __raw_writel(BM_SAIF_CTRL_SFTRST,
0307             saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0308         __raw_writel(BM_SAIF_CTRL_CLKGATE,
0309             saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0310     }
0311
0312     scr0 = __raw_readl(saif->base + SAIF_CTRL);
0313     scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
0314         & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
0315     scr = 0;
0316
0317     /* DAI mode */
0318     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0319     case SND_SOC_DAIFMT_I2S:
0320         /* data frame low 1clk before data */
0321         scr |= BM_SAIF_CTRL_DELAY;
0322         scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
0323         break;
0324     case SND_SOC_DAIFMT_LEFT_J:
0325         /* data frame high with data */
0326         scr &= ~BM_SAIF_CTRL_DELAY;
0327         scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
0328         scr &= ~BM_SAIF_CTRL_JUSTIFY;
0329         break;
0330     default:
0331         return -EINVAL;
0332     }
0333
0334     /* DAI clock inversion */
0335     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0336     case SND_SOC_DAIFMT_IB_IF:
0337         scr |= BM_SAIF_CTRL_BITCLK_EDGE;
0338         scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
0339         break;
0340     case SND_SOC_DAIFMT_IB_NF:
0341         scr |= BM_SAIF_CTRL_BITCLK_EDGE;
0342         scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
0343         break;
0344     case SND_SOC_DAIFMT_NB_IF:
0345         scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
0346         scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
0347         break;
0348     case SND_SOC_DAIFMT_NB_NF:
0349         scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
0350         scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
0351         break;
0352     }
0353
0354     /*
0355      * Note: We simply just support master mode since SAIF TX can only
0356      * work as master.
0357      * Here the master is relative to codec side.
0358      * Saif internally could be slave when working on EXTMASTER mode.
0359      * We just hide this to machine driver.
0360      */
0361     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0362     case SND_SOC_DAIFMT_BP_FP:
0363         if (saif->id == saif->master_id)
0364             scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
0365         else
0366             scr |= BM_SAIF_CTRL_SLAVE_MODE;
0367
0368         __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
0369         break;
0370     default:
0371         return -EINVAL;
0372     }
0373
0374     return 0;
0375 }
0376
0377 static int mxs_saif_startup(struct snd_pcm_substream *substream,
0378                struct snd_soc_dai *cpu_dai)
0379 {
0380     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0381     int ret;
0382
0383     /* clear error status to 0 for each re-open */
0384     saif->fifo_underrun = 0;
0385     saif->fifo_overrun = 0;
0386
0387     /* Clear Reset for normal operations */
0388     __raw_writel(BM_SAIF_CTRL_SFTRST,
0389         saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0390
0391     /* clear clock gate */
0392     __raw_writel(BM_SAIF_CTRL_CLKGATE,
0393         saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0394
0395     ret = clk_prepare(saif->clk);
0396     if (ret)
0397         return ret;
0398
0399     return 0;
0400 }
0401
0402 static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
0403                   struct snd_soc_dai *cpu_dai)
0404 {
0405     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0406
0407     clk_unprepare(saif->clk);
0408 }
0409
0410 /*
0411  * Should only be called when port is inactive.
0412  * although can be called multiple times by upper layers.
0413  */
0414 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
0415                  struct snd_pcm_hw_params *params,
0416                  struct snd_soc_dai *cpu_dai)
0417 {
0418     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0419     struct mxs_saif *master_saif;
0420     u32 scr, stat;
0421     int ret;
0422
0423     master_saif = mxs_saif_get_master(saif);
0424     if (!master_saif)
0425         return -EINVAL;
0426
0427     /* mclk should already be set */
0428     if (!saif->mclk && saif->mclk_in_use) {
0429         dev_err(cpu_dai->dev, "set mclk first\n");
0430         return -EINVAL;
0431     }
0432
0433     stat = __raw_readl(saif->base + SAIF_STAT);
0434     if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
0435         dev_err(cpu_dai->dev, "error: busy\n");
0436         return -EBUSY;
0437     }
0438
0439     /*
0440      * Set saif clk based on sample rate.
0441      * If mclk is used, we also set mclk, if not, saif->mclk is
0442      * default 0, means not used.
0443      */
0444     ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
0445     if (ret) {
0446         dev_err(cpu_dai->dev, "unable to get proper clk\n");
0447         return ret;
0448     }
0449
0450     if (saif != master_saif) {
0451         /*
0452         * Set an initial clock rate for the saif internal logic to work
0453         * properly. This is important when working in EXTMASTER mode
0454         * that uses the other saif's BITCLK&LRCLK but it still needs a
0455         * basic clock which should be fast enough for the internal
0456         * logic.
0457         */
0458         ret = clk_enable(saif->clk);
0459         if (ret)
0460             return ret;
0461
0462         ret = clk_set_rate(saif->clk, 24000000);
0463         clk_disable(saif->clk);
0464         if (ret)
0465             return ret;
0466
0467         ret = clk_prepare(master_saif->clk);
0468         if (ret)
0469             return ret;
0470     }
0471
0472     scr = __raw_readl(saif->base + SAIF_CTRL);
0473
0474     scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
0475     scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
0476     switch (params_format(params)) {
0477     case SNDRV_PCM_FORMAT_S16_LE:
0478         scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
0479         break;
0480     case SNDRV_PCM_FORMAT_S20_3LE:
0481         scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
0482         scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
0483         break;
0484     case SNDRV_PCM_FORMAT_S24_LE:
0485         scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
0486         scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
0487         break;
0488     default:
0489         return -EINVAL;
0490     }
0491
0492     /* Tx/Rx config */
0493     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0494         /* enable TX mode */
0495         scr &= ~BM_SAIF_CTRL_READ_MODE;
0496     } else {
0497         /* enable RX mode */
0498         scr |= BM_SAIF_CTRL_READ_MODE;
0499     }
0500
0501     __raw_writel(scr, saif->base + SAIF_CTRL);
0502     return 0;
0503 }
0504
0505 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
0506                struct snd_soc_dai *cpu_dai)
0507 {
0508     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0509
0510     /* enable FIFO error irqs */
0511     __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
0512         saif->base + SAIF_CTRL + MXS_SET_ADDR);
0513
0514     return 0;
0515 }
0516
0517 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
0518                 struct snd_soc_dai *cpu_dai)
0519 {
0520     struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
0521     struct mxs_saif *master_saif;
0522     u32 delay;
0523     int ret;
0524
0525     master_saif = mxs_saif_get_master(saif);
0526     if (!master_saif)
0527         return -EINVAL;
0528
0529     switch (cmd) {
0530     case SNDRV_PCM_TRIGGER_START:
0531     case SNDRV_PCM_TRIGGER_RESUME:
0532     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0533         if (saif->state == MXS_SAIF_STATE_RUNNING)
0534             return 0;
0535
0536         dev_dbg(cpu_dai->dev, "start\n");
0537
0538         ret = clk_enable(master_saif->clk);
0539         if (ret) {
0540             dev_err(saif->dev, "Failed to enable master clock\n");
0541             return ret;
0542         }
0543
0544         /*
0545          * If the saif's master is not itself, we also need to enable
0546          * itself clk for its internal basic logic to work.
0547          */
0548         if (saif != master_saif) {
0549             ret = clk_enable(saif->clk);
0550             if (ret) {
0551                 dev_err(saif->dev, "Failed to enable master clock\n");
0552                 clk_disable(master_saif->clk);
0553                 return ret;
0554             }
0555
0556             __raw_writel(BM_SAIF_CTRL_RUN,
0557                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
0558         }
0559
0560         if (!master_saif->mclk_in_use)
0561             __raw_writel(BM_SAIF_CTRL_RUN,
0562                 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
0563
0564         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0565             /*
0566              * write data to saif data register to trigger
0567              * the transfer.
0568              * For 24-bit format the 32-bit FIFO register stores
0569              * only one channel, so we need to write twice.
0570              * This is also safe for the other non 24-bit formats.
0571              */
0572             __raw_writel(0, saif->base + SAIF_DATA);
0573             __raw_writel(0, saif->base + SAIF_DATA);
0574         } else {
0575             /*
0576              * read data from saif data register to trigger
0577              * the receive.
0578              * For 24-bit format the 32-bit FIFO register stores
0579              * only one channel, so we need to read twice.
0580              * This is also safe for the other non 24-bit formats.
0581              */
0582             __raw_readl(saif->base + SAIF_DATA);
0583             __raw_readl(saif->base + SAIF_DATA);
0584         }
0585
0586         master_saif->ongoing = 1;
0587         saif->state = MXS_SAIF_STATE_RUNNING;
0588
0589         dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
0590             __raw_readl(saif->base + SAIF_CTRL),
0591             __raw_readl(saif->base + SAIF_STAT));
0592
0593         dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
0594             __raw_readl(master_saif->base + SAIF_CTRL),
0595             __raw_readl(master_saif->base + SAIF_STAT));
0596         break;
0597     case SNDRV_PCM_TRIGGER_SUSPEND:
0598     case SNDRV_PCM_TRIGGER_STOP:
0599     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0600         if (saif->state == MXS_SAIF_STATE_STOPPED)
0601             return 0;
0602
0603         dev_dbg(cpu_dai->dev, "stop\n");
0604
0605         /* wait a while for the current sample to complete */
0606         delay = USEC_PER_SEC / master_saif->cur_rate;
0607
0608         if (!master_saif->mclk_in_use) {
0609             __raw_writel(BM_SAIF_CTRL_RUN,
0610                 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0611             udelay(delay);
0612         }
0613         clk_disable(master_saif->clk);
0614
0615         if (saif != master_saif) {
0616             __raw_writel(BM_SAIF_CTRL_RUN,
0617                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
0618             udelay(delay);
0619             clk_disable(saif->clk);
0620         }
0621
0622         master_saif->ongoing = 0;
0623         saif->state = MXS_SAIF_STATE_STOPPED;
0624
0625         break;
0626     default:
0627         return -EINVAL;
0628     }
0629
0630     return 0;
0631 }
0632
0633 #define MXS_SAIF_RATES      SNDRV_PCM_RATE_8000_192000
0634 #define MXS_SAIF_FORMATS \
0635     (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0636     SNDRV_PCM_FMTBIT_S24_LE)
0637
0638 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
0639     .startup = mxs_saif_startup,
0640     .shutdown = mxs_saif_shutdown,
0641     .trigger = mxs_saif_trigger,
0642     .prepare = mxs_saif_prepare,
0643     .hw_params = mxs_saif_hw_params,
0644     .set_sysclk = mxs_saif_set_dai_sysclk,
0645     .set_fmt = mxs_saif_set_dai_fmt,
0646 };
0647
0648 static struct snd_soc_dai_driver mxs_saif_dai = {
0649     .name = "mxs-saif",
0650     .playback = {
0651         .channels_min = 2,
0652         .channels_max = 2,
0653         .rates = MXS_SAIF_RATES,
0654         .formats = MXS_SAIF_FORMATS,
0655     },
0656     .capture = {
0657         .channels_min = 2,
0658         .channels_max = 2,
0659         .rates = MXS_SAIF_RATES,
0660         .formats = MXS_SAIF_FORMATS,
0661     },
0662     .ops = &mxs_saif_dai_ops,
0663 };
0664
0665 static const struct snd_soc_component_driver mxs_saif_component = {
0666     .name           = "mxs-saif",
0667     .legacy_dai_naming  = 1,
0668 };
0669
0670 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
0671 {
0672     struct mxs_saif *saif = dev_id;
0673     unsigned int stat;
0674
0675     stat = __raw_readl(saif->base + SAIF_STAT);
0676     if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
0677             BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
0678         return IRQ_NONE;
0679
0680     if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
0681         dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
0682         __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
0683                 saif->base + SAIF_STAT + MXS_CLR_ADDR);
0684     }
0685
0686     if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
0687         dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
0688         __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
0689                 saif->base + SAIF_STAT + MXS_CLR_ADDR);
0690     }
0691
0692     dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
0693            __raw_readl(saif->base + SAIF_CTRL),
0694            __raw_readl(saif->base + SAIF_STAT));
0695
0696     return IRQ_HANDLED;
0697 }
0698
0699 static int mxs_saif_mclk_init(struct platform_device *pdev)
0700 {
0701     struct mxs_saif *saif = platform_get_drvdata(pdev);
0702     struct device_node *np = pdev->dev.of_node;
0703     struct clk *clk;
0704     int ret;
0705
0706     clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
0707                    __clk_get_name(saif->clk), 0,
0708                    saif->base + SAIF_CTRL,
0709                    BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
0710                    0, NULL);
0711     if (IS_ERR(clk)) {
0712         ret = PTR_ERR(clk);
0713         if (ret == -EEXIST)
0714             return 0;
0715         dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
0716         return PTR_ERR(clk);
0717     }
0718
0719     ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
0720     if (ret)
0721         return ret;
0722
0723     return 0;
0724 }
0725
0726 static int mxs_saif_probe(struct platform_device *pdev)
0727 {
0728     struct device_node *np = pdev->dev.of_node;
0729     struct mxs_saif *saif;
0730     int irq, ret;
0731     struct device_node *master;
0732
0733     saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
0734     if (!saif)
0735         return -ENOMEM;
0736
0737     ret = of_alias_get_id(np, "saif");
0738     if (ret < 0)
0739         return ret;
0740     else
0741         saif->id = ret;
0742
0743     if (saif->id >= ARRAY_SIZE(mxs_saif)) {
0744         dev_err(&pdev->dev, "get wrong saif id\n");
0745         return -EINVAL;
0746     }
0747
0748     /*
0749      * If there is no "fsl,saif-master" phandle, it's a saif
0750      * master.  Otherwise, it's a slave and its phandle points
0751      * to the master.
0752      */
0753     master = of_parse_phandle(np, "fsl,saif-master", 0);
0754     if (!master) {
0755         saif->master_id = saif->id;
0756     } else {
0757         ret = of_alias_get_id(master, "saif");
0758         of_node_put(master);
0759         if (ret < 0)
0760             return ret;
0761         else
0762             saif->master_id = ret;
0763
0764         if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
0765             dev_err(&pdev->dev, "get wrong master id\n");
0766             return -EINVAL;
0767         }
0768     }
0769
0770     mxs_saif[saif->id] = saif;
0771
0772     saif->clk = devm_clk_get(&pdev->dev, NULL);
0773     if (IS_ERR(saif->clk)) {
0774         ret = PTR_ERR(saif->clk);
0775         dev_err(&pdev->dev, "Cannot get the clock: %d\n",
0776             ret);
0777         return ret;
0778     }
0779
0780     saif->base = devm_platform_ioremap_resource(pdev, 0);
0781     if (IS_ERR(saif->base))
0782         return PTR_ERR(saif->base);
0783
0784     irq = platform_get_irq(pdev, 0);
0785     if (irq < 0)
0786         return irq;
0787
0788     saif->dev = &pdev->dev;
0789     ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
0790                    dev_name(&pdev->dev), saif);
0791     if (ret) {
0792         dev_err(&pdev->dev, "failed to request irq\n");
0793         return ret;
0794     }
0795
0796     platform_set_drvdata(pdev, saif);
0797
0798     /* We only support saif0 being tx and clock master */
0799     if (saif->id == 0) {
0800         ret = mxs_saif_mclk_init(pdev);
0801         if (ret)
0802             dev_warn(&pdev->dev, "failed to init clocks\n");
0803     }
0804
0805     ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
0806                           &mxs_saif_dai, 1);
0807     if (ret) {
0808         dev_err(&pdev->dev, "register DAI failed\n");
0809         return ret;
0810     }
0811
0812     ret = mxs_pcm_platform_register(&pdev->dev);
0813     if (ret) {
0814         dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
0815         return ret;
0816     }
0817
0818     return 0;
0819 }
0820
0821 static const struct of_device_id mxs_saif_dt_ids[] = {
0822     { .compatible = "fsl,imx28-saif", },
0823     { /* sentinel */ }
0824 };
0825 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
0826
0827 static struct platform_driver mxs_saif_driver = {
0828     .probe = mxs_saif_probe,
0829
0830     .driver = {
0831         .name = "mxs-saif",
0832         .of_match_table = mxs_saif_dt_ids,
0833     },
0834 };
0835
0836 module_platform_driver(mxs_saif_driver);
0837
0838 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
0839 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
0840 MODULE_LICENSE("GPL");
0841 MODULE_ALIAS("platform:mxs-saif");