soc/meson/axg-spdifin.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 //
0003 // Copyright (c) 2018 BayLibre, SAS.
0004 // Author: Jerome Brunet <jbrunet@baylibre.com>
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/clk.h>
0008 #include <linux/module.h>
0009 #include <linux/of_platform.h>
0010 #include <linux/regmap.h>
0011 #include <sound/soc.h>
0012 #include <sound/soc-dai.h>
0013 #include <sound/pcm_params.h>
0014
0015 #define SPDIFIN_CTRL0           0x00
0016 #define  SPDIFIN_CTRL0_EN       BIT(31)
0017 #define  SPDIFIN_CTRL0_RST_OUT      BIT(29)
0018 #define  SPDIFIN_CTRL0_RST_IN       BIT(28)
0019 #define  SPDIFIN_CTRL0_WIDTH_SEL    BIT(24)
0020 #define  SPDIFIN_CTRL0_STATUS_CH_SHIFT  11
0021 #define  SPDIFIN_CTRL0_STATUS_SEL   GENMASK(10, 8)
0022 #define  SPDIFIN_CTRL0_SRC_SEL      GENMASK(5, 4)
0023 #define  SPDIFIN_CTRL0_CHK_VALID    BIT(3)
0024 #define SPDIFIN_CTRL1           0x04
0025 #define  SPDIFIN_CTRL1_BASE_TIMER   GENMASK(19, 0)
0026 #define  SPDIFIN_CTRL1_IRQ_MASK     GENMASK(27, 20)
0027 #define SPDIFIN_CTRL2           0x08
0028 #define  SPDIFIN_THRES_PER_REG      3
0029 #define  SPDIFIN_THRES_WIDTH        10
0030 #define SPDIFIN_CTRL3           0x0c
0031 #define SPDIFIN_CTRL4           0x10
0032 #define  SPDIFIN_TIMER_PER_REG      4
0033 #define  SPDIFIN_TIMER_WIDTH        8
0034 #define SPDIFIN_CTRL5           0x14
0035 #define SPDIFIN_CTRL6           0x18
0036 #define SPDIFIN_STAT0           0x1c
0037 #define  SPDIFIN_STAT0_MODE     GENMASK(30, 28)
0038 #define  SPDIFIN_STAT0_MAXW     GENMASK(17, 8)
0039 #define  SPDIFIN_STAT0_IRQ      GENMASK(7, 0)
0040 #define  SPDIFIN_IRQ_MODE_CHANGED   BIT(2)
0041 #define SPDIFIN_STAT1           0x20
0042 #define SPDIFIN_STAT2           0x24
0043 #define SPDIFIN_MUTE_VAL        0x28
0044
0045 #define SPDIFIN_MODE_NUM        7
0046
0047 struct axg_spdifin_cfg {
0048     const unsigned int *mode_rates;
0049     unsigned int ref_rate;
0050 };
0051
0052 struct axg_spdifin {
0053     const struct axg_spdifin_cfg *conf;
0054     struct regmap *map;
0055     struct clk *refclk;
0056     struct clk *pclk;
0057 };
0058
0059 /*
0060  * TODO:
0061  * It would have been nice to check the actual rate against the sample rate
0062  * requested in hw_params(). Unfortunately, I was not able to make the mode
0063  * detection and IRQ work reliably:
0064  *
0065  * 1. IRQs are generated on mode change only, so there is no notification
0066  *    on transition between no signal and mode 0 (32kHz).
0067  * 2. Mode detection very often has glitches, and may detects the
0068  *    lowest or the highest mode before zeroing in on the actual mode.
0069  *
0070  * This makes calling snd_pcm_stop() difficult to get right. Even notifying
0071  * the kcontrol would be very unreliable at this point.
0072  * Let's keep things simple until the magic spell that makes this work is
0073  * found.
0074  */
0075
0076 static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
0077 {
0078     unsigned int stat, mode, rate = 0;
0079
0080     regmap_read(priv->map, SPDIFIN_STAT0, &stat);
0081     mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
0082
0083     /*
0084      * If max width is zero, we are not capturing anything.
0085      * Also Sometimes, when the capture is on but there is no data,
0086      * mode is SPDIFIN_MODE_NUM, but not always ...
0087      */
0088     if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
0089         mode < SPDIFIN_MODE_NUM)
0090         rate = priv->conf->mode_rates[mode];
0091
0092     return rate;
0093 }
0094
0095 static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
0096                    struct snd_soc_dai *dai)
0097 {
0098     struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
0099
0100     /* Apply both reset */
0101     regmap_update_bits(priv->map, SPDIFIN_CTRL0,
0102                SPDIFIN_CTRL0_RST_OUT |
0103                SPDIFIN_CTRL0_RST_IN,
0104                0);
0105
0106     /* Clear out reset before in reset */
0107     regmap_update_bits(priv->map, SPDIFIN_CTRL0,
0108                SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
0109     regmap_update_bits(priv->map, SPDIFIN_CTRL0,
0110                SPDIFIN_CTRL0_RST_IN,  SPDIFIN_CTRL0_RST_IN);
0111
0112     return 0;
0113 }
0114
0115 static int axg_spdifin_startup(struct snd_pcm_substream *substream,
0116                    struct snd_soc_dai *dai)
0117 {
0118     struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
0119     int ret;
0120
0121     ret = clk_prepare_enable(priv->refclk);
0122     if (ret) {
0123         dev_err(dai->dev,
0124             "failed to enable spdifin reference clock\n");
0125         return ret;
0126     }
0127
0128     regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
0129                SPDIFIN_CTRL0_EN);
0130
0131     return 0;
0132 }
0133
0134 static void axg_spdifin_shutdown(struct snd_pcm_substream *substream,
0135                  struct snd_soc_dai *dai)
0136 {
0137     struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
0138
0139     regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
0140     clk_disable_unprepare(priv->refclk);
0141 }
0142
0143 static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
0144                      unsigned int val,
0145                      unsigned int num_per_reg,
0146                      unsigned int base_reg,
0147                      unsigned int width)
0148 {
0149     uint64_t offset = mode;
0150     unsigned int reg, shift, rem;
0151
0152     rem = do_div(offset, num_per_reg);
0153
0154     reg = offset * regmap_get_reg_stride(map) + base_reg;
0155     shift = width * (num_per_reg - 1 - rem);
0156
0157     regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
0158                val << shift);
0159 }
0160
0161 static void axg_spdifin_write_timer(struct regmap *map, int mode,
0162                     unsigned int val)
0163 {
0164     axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG,
0165                      SPDIFIN_CTRL4, SPDIFIN_TIMER_WIDTH);
0166 }
0167
0168 static void axg_spdifin_write_threshold(struct regmap *map, int mode,
0169                     unsigned int val)
0170 {
0171     axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG,
0172                      SPDIFIN_CTRL2, SPDIFIN_THRES_WIDTH);
0173 }
0174
0175 static unsigned int axg_spdifin_mode_timer(struct axg_spdifin *priv,
0176                        int mode,
0177                        unsigned int rate)
0178 {
0179     /*
0180      * Number of period of the reference clock during a period of the
0181      * input signal reference clock
0182      */
0183     return rate / (128 * priv->conf->mode_rates[mode]);
0184 }
0185
0186 static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
0187                       struct axg_spdifin *priv)
0188 {
0189     unsigned int rate, t_next;
0190     int ret, i = SPDIFIN_MODE_NUM - 1;
0191
0192     /* Set spdif input reference clock */
0193     ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
0194     if (ret) {
0195         dev_err(dai->dev, "reference clock rate set failed\n");
0196         return ret;
0197     }
0198
0199     /*
0200      * The rate actually set might be slightly different, get
0201      * the actual rate for the following mode calculation
0202      */
0203     rate = clk_get_rate(priv->refclk);
0204
0205     /* HW will update mode every 1ms */
0206     regmap_update_bits(priv->map, SPDIFIN_CTRL1,
0207                SPDIFIN_CTRL1_BASE_TIMER,
0208                FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
0209
0210     /* Threshold based on the minimum width between two edges */
0211     regmap_update_bits(priv->map, SPDIFIN_CTRL0,
0212                SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
0213
0214     /* Calculate the last timer which has no threshold */
0215     t_next = axg_spdifin_mode_timer(priv, i, rate);
0216     axg_spdifin_write_timer(priv->map, i, t_next);
0217
0218     do {
0219         unsigned int t;
0220
0221         i -= 1;
0222
0223         /* Calculate the timer */
0224         t = axg_spdifin_mode_timer(priv, i, rate);
0225
0226         /* Set the timer value */
0227         axg_spdifin_write_timer(priv->map, i, t);
0228
0229         /* Set the threshold value */
0230         axg_spdifin_write_threshold(priv->map, i, t + t_next);
0231
0232         /* Save the current timer for the next threshold calculation */
0233         t_next = t;
0234
0235     } while (i > 0);
0236
0237     return 0;
0238 }
0239
0240 static int axg_spdifin_dai_probe(struct snd_soc_dai *dai)
0241 {
0242     struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
0243     int ret;
0244
0245     ret = clk_prepare_enable(priv->pclk);
0246     if (ret) {
0247         dev_err(dai->dev, "failed to enable pclk\n");
0248         return ret;
0249     }
0250
0251     ret = axg_spdifin_sample_mode_config(dai, priv);
0252     if (ret) {
0253         dev_err(dai->dev, "mode configuration failed\n");
0254         clk_disable_unprepare(priv->pclk);
0255         return ret;
0256     }
0257
0258     return 0;
0259 }
0260
0261 static int axg_spdifin_dai_remove(struct snd_soc_dai *dai)
0262 {
0263     struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
0264
0265     clk_disable_unprepare(priv->pclk);
0266     return 0;
0267 }
0268
0269 static const struct snd_soc_dai_ops axg_spdifin_ops = {
0270     .prepare    = axg_spdifin_prepare,
0271     .startup    = axg_spdifin_startup,
0272     .shutdown   = axg_spdifin_shutdown,
0273 };
0274
0275 static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
0276                    struct snd_ctl_elem_info *uinfo)
0277 {
0278     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0279     uinfo->count = 1;
0280
0281     return 0;
0282 }
0283
0284 static int axg_spdifin_get_status_mask(struct snd_kcontrol *kcontrol,
0285                        struct snd_ctl_elem_value *ucontrol)
0286 {
0287     int i;
0288
0289     for (i = 0; i < 24; i++)
0290         ucontrol->value.iec958.status[i] = 0xff;
0291
0292     return 0;
0293 }
0294
0295 static int axg_spdifin_get_status(struct snd_kcontrol *kcontrol,
0296                   struct snd_ctl_elem_value *ucontrol)
0297 {
0298     struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
0299     struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
0300     int i, j;
0301
0302     for (i = 0; i < 6; i++) {
0303         unsigned int val;
0304
0305         regmap_update_bits(priv->map, SPDIFIN_CTRL0,
0306                    SPDIFIN_CTRL0_STATUS_SEL,
0307                    FIELD_PREP(SPDIFIN_CTRL0_STATUS_SEL, i));
0308
0309         regmap_read(priv->map, SPDIFIN_STAT1, &val);
0310
0311         for (j = 0; j < 4; j++) {
0312             unsigned int offset = i * 4 + j;
0313
0314             ucontrol->value.iec958.status[offset] =
0315                 (val >> (j * 8)) & 0xff;
0316         }
0317     }
0318
0319     return 0;
0320 }
0321
0322 #define AXG_SPDIFIN_IEC958_MASK                     \
0323     {                               \
0324         .access = SNDRV_CTL_ELEM_ACCESS_READ,           \
0325         .iface = SNDRV_CTL_ELEM_IFACE_PCM,          \
0326         .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),   \
0327         .info = axg_spdifin_iec958_info,            \
0328         .get = axg_spdifin_get_status_mask,         \
0329     }
0330
0331 #define AXG_SPDIFIN_IEC958_STATUS                   \
0332     {                               \
0333         .access = (SNDRV_CTL_ELEM_ACCESS_READ |         \
0334                SNDRV_CTL_ELEM_ACCESS_VOLATILE),     \
0335         .iface = SNDRV_CTL_ELEM_IFACE_PCM,          \
0336         .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE),   \
0337         .info = axg_spdifin_iec958_info,            \
0338         .get = axg_spdifin_get_status,              \
0339     }
0340
0341 static const char * const spdifin_chsts_src_texts[] = {
0342     "A", "B",
0343 };
0344
0345 static SOC_ENUM_SINGLE_DECL(axg_spdifin_chsts_src_enum, SPDIFIN_CTRL0,
0346                 SPDIFIN_CTRL0_STATUS_CH_SHIFT,
0347                 spdifin_chsts_src_texts);
0348
0349 static int axg_spdifin_rate_lock_info(struct snd_kcontrol *kcontrol,
0350                       struct snd_ctl_elem_info *uinfo)
0351 {
0352     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0353     uinfo->count = 1;
0354     uinfo->value.integer.min = 0;
0355     uinfo->value.integer.max = 192000;
0356
0357     return 0;
0358 }
0359
0360 static int axg_spdifin_rate_lock_get(struct snd_kcontrol *kcontrol,
0361                      struct snd_ctl_elem_value *ucontrol)
0362 {
0363     struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
0364     struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
0365
0366     ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);
0367
0368     return 0;
0369 }
0370
0371 #define AXG_SPDIFIN_LOCK_RATE(xname)                \
0372     {                           \
0373         .iface = SNDRV_CTL_ELEM_IFACE_PCM,      \
0374         .access = (SNDRV_CTL_ELEM_ACCESS_READ |     \
0375                SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
0376         .get = axg_spdifin_rate_lock_get,       \
0377         .info = axg_spdifin_rate_lock_info,     \
0378         .name = xname,                  \
0379     }
0380
0381 static const struct snd_kcontrol_new axg_spdifin_controls[] = {
0382     AXG_SPDIFIN_LOCK_RATE("Capture Rate Lock"),
0383     SOC_DOUBLE("Capture Switch", SPDIFIN_CTRL0, 7, 6, 1, 1),
0384     SOC_ENUM(SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Src",
0385          axg_spdifin_chsts_src_enum),
0386     AXG_SPDIFIN_IEC958_MASK,
0387     AXG_SPDIFIN_IEC958_STATUS,
0388 };
0389
0390 static const struct snd_soc_component_driver axg_spdifin_component_drv = {
0391     .controls       = axg_spdifin_controls,
0392     .num_controls       = ARRAY_SIZE(axg_spdifin_controls),
0393     .legacy_dai_naming  = 1,
0394 };
0395
0396 static const struct regmap_config axg_spdifin_regmap_cfg = {
0397     .reg_bits   = 32,
0398     .val_bits   = 32,
0399     .reg_stride = 4,
0400     .max_register   = SPDIFIN_MUTE_VAL,
0401 };
0402
0403 static const unsigned int axg_spdifin_mode_rates[SPDIFIN_MODE_NUM] = {
0404     32000, 44100, 48000, 88200, 96000, 176400, 192000,
0405 };
0406
0407 static const struct axg_spdifin_cfg axg_cfg = {
0408     .mode_rates = axg_spdifin_mode_rates,
0409     .ref_rate = 333333333,
0410 };
0411
0412 static const struct of_device_id axg_spdifin_of_match[] = {
0413     {
0414         .compatible = "amlogic,axg-spdifin",
0415         .data = &axg_cfg,
0416     }, {}
0417 };
0418 MODULE_DEVICE_TABLE(of, axg_spdifin_of_match);
0419
0420 static struct snd_soc_dai_driver *
0421 axg_spdifin_get_dai_drv(struct device *dev, struct axg_spdifin *priv)
0422 {
0423     struct snd_soc_dai_driver *drv;
0424     int i;
0425
0426     drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
0427     if (!drv)
0428         return ERR_PTR(-ENOMEM);
0429
0430     drv->name = "SPDIF Input";
0431     drv->ops = &axg_spdifin_ops;
0432     drv->probe = axg_spdifin_dai_probe;
0433     drv->remove = axg_spdifin_dai_remove;
0434     drv->capture.stream_name = "Capture";
0435     drv->capture.channels_min = 1;
0436     drv->capture.channels_max = 2;
0437     drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
0438
0439     for (i = 0; i < SPDIFIN_MODE_NUM; i++) {
0440         unsigned int rb =
0441             snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);
0442
0443         if (rb == SNDRV_PCM_RATE_KNOT)
0444             return ERR_PTR(-EINVAL);
0445
0446         drv->capture.rates |= rb;
0447     }
0448
0449     return drv;
0450 }
0451
0452 static int axg_spdifin_probe(struct platform_device *pdev)
0453 {
0454     struct device *dev = &pdev->dev;
0455     struct axg_spdifin *priv;
0456     struct snd_soc_dai_driver *dai_drv;
0457     void __iomem *regs;
0458
0459     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0460     if (!priv)
0461         return -ENOMEM;
0462     platform_set_drvdata(pdev, priv);
0463
0464     priv->conf = of_device_get_match_data(dev);
0465     if (!priv->conf) {
0466         dev_err(dev, "failed to match device\n");
0467         return -ENODEV;
0468     }
0469
0470     regs = devm_platform_ioremap_resource(pdev, 0);
0471     if (IS_ERR(regs))
0472         return PTR_ERR(regs);
0473
0474     priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);
0475     if (IS_ERR(priv->map)) {
0476         dev_err(dev, "failed to init regmap: %ld\n",
0477             PTR_ERR(priv->map));
0478         return PTR_ERR(priv->map);
0479     }
0480
0481     priv->pclk = devm_clk_get(dev, "pclk");
0482     if (IS_ERR(priv->pclk))
0483         return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");
0484
0485     priv->refclk = devm_clk_get(dev, "refclk");
0486     if (IS_ERR(priv->refclk))
0487         return dev_err_probe(dev, PTR_ERR(priv->refclk), "failed to get mclk\n");
0488
0489     dai_drv = axg_spdifin_get_dai_drv(dev, priv);
0490     if (IS_ERR(dai_drv)) {
0491         dev_err(dev, "failed to get dai driver: %ld\n",
0492             PTR_ERR(dai_drv));
0493         return PTR_ERR(dai_drv);
0494     }
0495
0496     return devm_snd_soc_register_component(dev, &axg_spdifin_component_drv,
0497                            dai_drv, 1);
0498 }
0499
0500 static struct platform_driver axg_spdifin_pdrv = {
0501     .probe = axg_spdifin_probe,
0502     .driver = {
0503         .name = "axg-spdifin",
0504         .of_match_table = axg_spdifin_of_match,
0505     },
0506 };
0507 module_platform_driver(axg_spdifin_pdrv);
0508
0509 MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");
0510 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
0511 MODULE_LICENSE("GPL v2");