soc/meson/axg-pdm.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 //
0003 // Copyright (c) 2018 BayLibre, SAS.
0004 // Author: Jerome Brunet <jbrunet@baylibre.com>
0005
0006 #include <linux/clk.h>
0007 #include <linux/module.h>
0008 #include <linux/of_irq.h>
0009 #include <linux/of_platform.h>
0010 #include <linux/regmap.h>
0011 #include <sound/soc.h>
0012 #include <sound/soc-dai.h>
0013 #include <sound/pcm_params.h>
0014
0015 #define PDM_CTRL            0x00
0016 #define  PDM_CTRL_EN            BIT(31)
0017 #define  PDM_CTRL_OUT_MODE      BIT(29)
0018 #define  PDM_CTRL_BYPASS_MODE       BIT(28)
0019 #define  PDM_CTRL_RST_FIFO      BIT(16)
0020 #define  PDM_CTRL_CHAN_RSTN_MASK    GENMASK(15, 8)
0021 #define  PDM_CTRL_CHAN_RSTN(x)      ((x) << 8)
0022 #define  PDM_CTRL_CHAN_EN_MASK      GENMASK(7, 0)
0023 #define  PDM_CTRL_CHAN_EN(x)        ((x) << 0)
0024 #define PDM_HCIC_CTRL1          0x04
0025 #define  PDM_FILTER_EN          BIT(31)
0026 #define  PDM_HCIC_CTRL1_GAIN_SFT_MASK   GENMASK(29, 24)
0027 #define  PDM_HCIC_CTRL1_GAIN_SFT(x) ((x) << 24)
0028 #define  PDM_HCIC_CTRL1_GAIN_MULT_MASK  GENMASK(23, 16)
0029 #define  PDM_HCIC_CTRL1_GAIN_MULT(x)    ((x) << 16)
0030 #define  PDM_HCIC_CTRL1_DSR_MASK    GENMASK(8, 4)
0031 #define  PDM_HCIC_CTRL1_DSR(x)      ((x) << 4)
0032 #define  PDM_HCIC_CTRL1_STAGE_NUM_MASK  GENMASK(3, 0)
0033 #define  PDM_HCIC_CTRL1_STAGE_NUM(x)    ((x) << 0)
0034 #define PDM_HCIC_CTRL2          0x08
0035 #define PDM_F1_CTRL         0x0c
0036 #define  PDM_LPF_ROUND_MODE_MASK    GENMASK(17, 16)
0037 #define  PDM_LPF_ROUND_MODE(x)      ((x) << 16)
0038 #define  PDM_LPF_DSR_MASK       GENMASK(15, 12)
0039 #define  PDM_LPF_DSR(x)         ((x) << 12)
0040 #define  PDM_LPF_STAGE_NUM_MASK     GENMASK(8, 0)
0041 #define  PDM_LPF_STAGE_NUM(x)       ((x) << 0)
0042 #define  PDM_LPF_MAX_STAGE      336
0043 #define  PDM_LPF_NUM            3
0044 #define PDM_F2_CTRL         0x10
0045 #define PDM_F3_CTRL         0x14
0046 #define PDM_HPF_CTRL            0x18
0047 #define  PDM_HPF_SFT_STEPS_MASK     GENMASK(20, 16)
0048 #define  PDM_HPF_SFT_STEPS(x)       ((x) << 16)
0049 #define  PDM_HPF_OUT_FACTOR_MASK    GENMASK(15, 0)
0050 #define  PDM_HPF_OUT_FACTOR(x)      ((x) << 0)
0051 #define PDM_CHAN_CTRL           0x1c
0052 #define  PDM_CHAN_CTRL_POINTER_WIDTH    8
0053 #define  PDM_CHAN_CTRL_POINTER_MAX  ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1)
0054 #define  PDM_CHAN_CTRL_NUM      4
0055 #define PDM_CHAN_CTRL1          0x20
0056 #define PDM_COEFF_ADDR          0x24
0057 #define PDM_COEFF_DATA          0x28
0058 #define PDM_CLKG_CTRL           0x2c
0059 #define PDM_STS             0x30
0060
0061 struct axg_pdm_lpf {
0062     unsigned int ds;
0063     unsigned int round_mode;
0064     const unsigned int *tap;
0065     unsigned int tap_num;
0066 };
0067
0068 struct axg_pdm_hcic {
0069     unsigned int shift;
0070     unsigned int mult;
0071     unsigned int steps;
0072     unsigned int ds;
0073 };
0074
0075 struct axg_pdm_hpf {
0076     unsigned int out_factor;
0077     unsigned int steps;
0078 };
0079
0080 struct axg_pdm_filters {
0081     struct axg_pdm_hcic hcic;
0082     struct axg_pdm_hpf hpf;
0083     struct axg_pdm_lpf lpf[PDM_LPF_NUM];
0084 };
0085
0086 struct axg_pdm_cfg {
0087     const struct axg_pdm_filters *filters;
0088     unsigned int sys_rate;
0089 };
0090
0091 struct axg_pdm {
0092     const struct axg_pdm_cfg *cfg;
0093     struct regmap *map;
0094     struct clk *dclk;
0095     struct clk *sysclk;
0096     struct clk *pclk;
0097 };
0098
0099 static void axg_pdm_enable(struct regmap *map)
0100 {
0101     /* Reset AFIFO */
0102     regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, PDM_CTRL_RST_FIFO);
0103     regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, 0);
0104
0105     /* Enable PDM */
0106     regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, PDM_CTRL_EN);
0107 }
0108
0109 static void axg_pdm_disable(struct regmap *map)
0110 {
0111     regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, 0);
0112 }
0113
0114 static void axg_pdm_filters_enable(struct regmap *map, bool enable)
0115 {
0116     unsigned int val = enable ? PDM_FILTER_EN : 0;
0117
0118     regmap_update_bits(map, PDM_HCIC_CTRL1, PDM_FILTER_EN, val);
0119     regmap_update_bits(map, PDM_F1_CTRL, PDM_FILTER_EN, val);
0120     regmap_update_bits(map, PDM_F2_CTRL, PDM_FILTER_EN, val);
0121     regmap_update_bits(map, PDM_F3_CTRL, PDM_FILTER_EN, val);
0122     regmap_update_bits(map, PDM_HPF_CTRL, PDM_FILTER_EN, val);
0123 }
0124
0125 static int axg_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
0126                struct snd_soc_dai *dai)
0127 {
0128     struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
0129
0130     switch (cmd) {
0131     case SNDRV_PCM_TRIGGER_START:
0132     case SNDRV_PCM_TRIGGER_RESUME:
0133     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0134         axg_pdm_enable(priv->map);
0135         return 0;
0136
0137     case SNDRV_PCM_TRIGGER_STOP:
0138     case SNDRV_PCM_TRIGGER_SUSPEND:
0139     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0140         axg_pdm_disable(priv->map);
0141         return 0;
0142
0143     default:
0144         return -EINVAL;
0145     }
0146 }
0147
0148 static unsigned int axg_pdm_get_os(struct axg_pdm *priv)
0149 {
0150     const struct axg_pdm_filters *filters = priv->cfg->filters;
0151     unsigned int os = filters->hcic.ds;
0152     int i;
0153
0154     /*
0155      * The global oversampling factor is defined by the down sampling
0156      * factor applied by each filter (HCIC and LPFs)
0157      */
0158
0159     for (i = 0; i < PDM_LPF_NUM; i++)
0160         os *= filters->lpf[i].ds;
0161
0162     return os;
0163 }
0164
0165 static int axg_pdm_set_sysclk(struct axg_pdm *priv, unsigned int os,
0166                   unsigned int rate)
0167 {
0168     unsigned int sys_rate = os * 2 * rate * PDM_CHAN_CTRL_POINTER_MAX;
0169
0170     /*
0171      * Set the default system clock rate unless it is too fast for
0172      * for the requested sample rate. In this case, the sample pointer
0173      * counter could overflow so set a lower system clock rate
0174      */
0175     if (sys_rate < priv->cfg->sys_rate)
0176         return clk_set_rate(priv->sysclk, sys_rate);
0177
0178     return clk_set_rate(priv->sysclk, priv->cfg->sys_rate);
0179 }
0180
0181 static int axg_pdm_set_sample_pointer(struct axg_pdm *priv)
0182 {
0183     unsigned int spmax, sp, val;
0184     int i;
0185
0186     /* Max sample counter value per half period of dclk */
0187     spmax = DIV_ROUND_UP_ULL((u64)clk_get_rate(priv->sysclk),
0188                  clk_get_rate(priv->dclk) * 2);
0189
0190     /* Check if sysclk is not too fast - should not happen */
0191     if (WARN_ON(spmax > PDM_CHAN_CTRL_POINTER_MAX))
0192         return -EINVAL;
0193
0194     /* Capture the data when we are at 75% of the half period */
0195     sp = spmax * 3 / 4;
0196
0197     for (i = 0, val = 0; i < PDM_CHAN_CTRL_NUM; i++)
0198         val |= sp << (PDM_CHAN_CTRL_POINTER_WIDTH * i);
0199
0200     regmap_write(priv->map, PDM_CHAN_CTRL, val);
0201     regmap_write(priv->map, PDM_CHAN_CTRL1, val);
0202
0203     return 0;
0204 }
0205
0206 static void axg_pdm_set_channel_mask(struct axg_pdm *priv,
0207                      unsigned int channels)
0208 {
0209     unsigned int mask = GENMASK(channels - 1, 0);
0210
0211     /* Put all channel in reset */
0212     regmap_update_bits(priv->map, PDM_CTRL,
0213                PDM_CTRL_CHAN_RSTN_MASK, 0);
0214
0215     /* Take the necessary channels out of reset and enable them */
0216     regmap_update_bits(priv->map, PDM_CTRL,
0217                PDM_CTRL_CHAN_RSTN_MASK |
0218                PDM_CTRL_CHAN_EN_MASK,
0219                PDM_CTRL_CHAN_RSTN(mask) |
0220                PDM_CTRL_CHAN_EN(mask));
0221 }
0222
0223 static int axg_pdm_hw_params(struct snd_pcm_substream *substream,
0224                  struct snd_pcm_hw_params *params,
0225                  struct snd_soc_dai *dai)
0226 {
0227     struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
0228     unsigned int os = axg_pdm_get_os(priv);
0229     unsigned int rate = params_rate(params);
0230     unsigned int val;
0231     int ret;
0232
0233     switch (params_width(params)) {
0234     case 24:
0235         val = PDM_CTRL_OUT_MODE;
0236         break;
0237     case 32:
0238         val = 0;
0239         break;
0240     default:
0241         dev_err(dai->dev, "unsupported sample width\n");
0242         return -EINVAL;
0243     }
0244
0245     regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_OUT_MODE, val);
0246
0247     ret = axg_pdm_set_sysclk(priv, os, rate);
0248     if (ret) {
0249         dev_err(dai->dev, "failed to set system clock\n");
0250         return ret;
0251     }
0252
0253     ret = clk_set_rate(priv->dclk, rate * os);
0254     if (ret) {
0255         dev_err(dai->dev, "failed to set dclk\n");
0256         return ret;
0257     }
0258
0259     ret = axg_pdm_set_sample_pointer(priv);
0260     if (ret) {
0261         dev_err(dai->dev, "invalid clock setting\n");
0262         return ret;
0263     }
0264
0265     axg_pdm_set_channel_mask(priv, params_channels(params));
0266
0267     return 0;
0268 }
0269
0270 static int axg_pdm_startup(struct snd_pcm_substream *substream,
0271                struct snd_soc_dai *dai)
0272 {
0273     struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
0274     int ret;
0275
0276     ret = clk_prepare_enable(priv->dclk);
0277     if (ret) {
0278         dev_err(dai->dev, "enabling dclk failed\n");
0279         return ret;
0280     }
0281
0282     /* Enable the filters */
0283     axg_pdm_filters_enable(priv->map, true);
0284
0285     return ret;
0286 }
0287
0288 static void axg_pdm_shutdown(struct snd_pcm_substream *substream,
0289                  struct snd_soc_dai *dai)
0290 {
0291     struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
0292
0293     axg_pdm_filters_enable(priv->map, false);
0294     clk_disable_unprepare(priv->dclk);
0295 }
0296
0297 static const struct snd_soc_dai_ops axg_pdm_dai_ops = {
0298     .trigger    = axg_pdm_trigger,
0299     .hw_params  = axg_pdm_hw_params,
0300     .startup    = axg_pdm_startup,
0301     .shutdown   = axg_pdm_shutdown,
0302 };
0303
0304 static void axg_pdm_set_hcic_ctrl(struct axg_pdm *priv)
0305 {
0306     const struct axg_pdm_hcic *hcic = &priv->cfg->filters->hcic;
0307     unsigned int val;
0308
0309     val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps);
0310     val |= PDM_HCIC_CTRL1_DSR(hcic->ds);
0311     val |= PDM_HCIC_CTRL1_GAIN_MULT(hcic->mult);
0312     val |= PDM_HCIC_CTRL1_GAIN_SFT(hcic->shift);
0313
0314     regmap_update_bits(priv->map, PDM_HCIC_CTRL1,
0315                PDM_HCIC_CTRL1_STAGE_NUM_MASK |
0316                PDM_HCIC_CTRL1_DSR_MASK |
0317                PDM_HCIC_CTRL1_GAIN_MULT_MASK |
0318                PDM_HCIC_CTRL1_GAIN_SFT_MASK,
0319                val);
0320 }
0321
0322 static void axg_pdm_set_lpf_ctrl(struct axg_pdm *priv, unsigned int index)
0323 {
0324     const struct axg_pdm_lpf *lpf = &priv->cfg->filters->lpf[index];
0325     unsigned int offset = index * regmap_get_reg_stride(priv->map)
0326         + PDM_F1_CTRL;
0327     unsigned int val;
0328
0329     val = PDM_LPF_STAGE_NUM(lpf->tap_num);
0330     val |= PDM_LPF_DSR(lpf->ds);
0331     val |= PDM_LPF_ROUND_MODE(lpf->round_mode);
0332
0333     regmap_update_bits(priv->map, offset,
0334                PDM_LPF_STAGE_NUM_MASK |
0335                PDM_LPF_DSR_MASK |
0336                PDM_LPF_ROUND_MODE_MASK,
0337                val);
0338 }
0339
0340 static void axg_pdm_set_hpf_ctrl(struct axg_pdm *priv)
0341 {
0342     const struct axg_pdm_hpf *hpf = &priv->cfg->filters->hpf;
0343     unsigned int val;
0344
0345     val = PDM_HPF_OUT_FACTOR(hpf->out_factor);
0346     val |= PDM_HPF_SFT_STEPS(hpf->steps);
0347
0348     regmap_update_bits(priv->map, PDM_HPF_CTRL,
0349                PDM_HPF_OUT_FACTOR_MASK |
0350                PDM_HPF_SFT_STEPS_MASK,
0351                val);
0352 }
0353
0354 static int axg_pdm_set_lpf_filters(struct axg_pdm *priv)
0355 {
0356     const struct axg_pdm_lpf *lpf = priv->cfg->filters->lpf;
0357     unsigned int count = 0;
0358     int i, j;
0359
0360     for (i = 0; i < PDM_LPF_NUM; i++)
0361         count += lpf[i].tap_num;
0362
0363     /* Make sure the coeffs fit in the memory */
0364     if (count >= PDM_LPF_MAX_STAGE)
0365         return -EINVAL;
0366
0367     /* Set the initial APB bus register address */
0368     regmap_write(priv->map, PDM_COEFF_ADDR, 0);
0369
0370     /* Set the tap filter values of all 3 filters */
0371     for (i = 0; i < PDM_LPF_NUM; i++) {
0372         axg_pdm_set_lpf_ctrl(priv, i);
0373
0374         for (j = 0; j < lpf[i].tap_num; j++)
0375             regmap_write(priv->map, PDM_COEFF_DATA, lpf[i].tap[j]);
0376     }
0377
0378     return 0;
0379 }
0380
0381 static int axg_pdm_dai_probe(struct snd_soc_dai *dai)
0382 {
0383     struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
0384     int ret;
0385
0386     ret = clk_prepare_enable(priv->pclk);
0387     if (ret) {
0388         dev_err(dai->dev, "enabling pclk failed\n");
0389         return ret;
0390     }
0391
0392     /*
0393      * sysclk must be set and enabled as well to access the pdm registers
0394      * Accessing the register w/o it will give a bus error.
0395      */
0396     ret = clk_set_rate(priv->sysclk, priv->cfg->sys_rate);
0397     if (ret) {
0398         dev_err(dai->dev, "setting sysclk failed\n");
0399         goto err_pclk;
0400     }
0401
0402     ret = clk_prepare_enable(priv->sysclk);
0403     if (ret) {
0404         dev_err(dai->dev, "enabling sysclk failed\n");
0405         goto err_pclk;
0406     }
0407
0408     /* Make sure the device is initially disabled */
0409     axg_pdm_disable(priv->map);
0410
0411     /* Make sure filter bypass is disabled */
0412     regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_BYPASS_MODE, 0);
0413
0414     /* Load filter settings */
0415     axg_pdm_set_hcic_ctrl(priv);
0416     axg_pdm_set_hpf_ctrl(priv);
0417
0418     ret = axg_pdm_set_lpf_filters(priv);
0419     if (ret) {
0420         dev_err(dai->dev, "invalid filter configuration\n");
0421         goto err_sysclk;
0422     }
0423
0424     return 0;
0425
0426 err_sysclk:
0427     clk_disable_unprepare(priv->sysclk);
0428 err_pclk:
0429     clk_disable_unprepare(priv->pclk);
0430     return ret;
0431 }
0432
0433 static int axg_pdm_dai_remove(struct snd_soc_dai *dai)
0434 {
0435     struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
0436
0437     clk_disable_unprepare(priv->sysclk);
0438     clk_disable_unprepare(priv->pclk);
0439
0440     return 0;
0441 }
0442
0443 static struct snd_soc_dai_driver axg_pdm_dai_drv = {
0444     .name = "PDM",
0445     .capture = {
0446         .stream_name    = "Capture",
0447         .channels_min   = 1,
0448         .channels_max   = 8,
0449         .rates      = SNDRV_PCM_RATE_CONTINUOUS,
0450         .rate_min   = 5512,
0451         .rate_max   = 48000,
0452         .formats    = (SNDRV_PCM_FMTBIT_S24_LE |
0453                    SNDRV_PCM_FMTBIT_S32_LE),
0454     },
0455     .ops        = &axg_pdm_dai_ops,
0456     .probe      = axg_pdm_dai_probe,
0457     .remove     = axg_pdm_dai_remove,
0458 };
0459
0460 static const struct snd_soc_component_driver axg_pdm_component_drv = {
0461     .legacy_dai_naming = 1,
0462 };
0463
0464 static const struct regmap_config axg_pdm_regmap_cfg = {
0465     .reg_bits   = 32,
0466     .val_bits   = 32,
0467     .reg_stride = 4,
0468     .max_register   = PDM_STS,
0469 };
0470
0471 static const unsigned int lpf1_default_tap[] = {
0472     0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45,
0473     0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21,
0474     0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212,
0475     0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa,
0476     0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef,
0477     0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077,
0478     0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690,
0479     0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3,
0480     0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686,
0481     0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812,
0482     0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60,
0483     0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000,
0484     0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e,
0485     0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c,
0486     0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece,
0487     0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645,
0488     0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9,
0489     0xffffb2, 0x000014,
0490 };
0491
0492 static const unsigned int lpf2_default_tap[] = {
0493     0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818,
0494     0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41,
0495     0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0,
0496     0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000,
0497     0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93,
0498     0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12,
0499     0x0002c1, 0xfff004, 0x00050a,
0500 };
0501
0502 static const unsigned int lpf3_default_tap[] = {
0503     0x000000, 0x000081, 0x000000, 0xfffedb, 0x000000,
0504     0x00022d, 0x000000, 0xfffc46, 0x000000, 0x0005f7,
0505     0x000000, 0xfff6eb, 0x000000, 0x000d4e, 0x000000,
0506     0xffed1e, 0x000000, 0x001a1c, 0x000000, 0xffdcb0,
0507     0x000000, 0x002ede, 0x000000, 0xffc2d1, 0x000000,
0508     0x004ebe, 0x000000, 0xff9beb, 0x000000, 0x007dd7,
0509     0x000000, 0xff633a, 0x000000, 0x00c1d2, 0x000000,
0510     0xff11d5, 0x000000, 0x012368, 0x000000, 0xfe9c45,
0511     0x000000, 0x01b252, 0x000000, 0xfdebf6, 0x000000,
0512     0x0290b8, 0x000000, 0xfcca0d, 0x000000, 0x041d7c,
0513     0x000000, 0xfa8152, 0x000000, 0x07e9c6, 0x000000,
0514     0xf28fb5, 0x000000, 0x28b216, 0x3fffde, 0x28b216,
0515     0x000000, 0xf28fb5, 0x000000, 0x07e9c6, 0x000000,
0516     0xfa8152, 0x000000, 0x041d7c, 0x000000, 0xfcca0d,
0517     0x000000, 0x0290b8, 0x000000, 0xfdebf6, 0x000000,
0518     0x01b252, 0x000000, 0xfe9c45, 0x000000, 0x012368,
0519     0x000000, 0xff11d5, 0x000000, 0x00c1d2, 0x000000,
0520     0xff633a, 0x000000, 0x007dd7, 0x000000, 0xff9beb,
0521     0x000000, 0x004ebe, 0x000000, 0xffc2d1, 0x000000,
0522     0x002ede, 0x000000, 0xffdcb0, 0x000000, 0x001a1c,
0523     0x000000, 0xffed1e, 0x000000, 0x000d4e, 0x000000,
0524     0xfff6eb, 0x000000, 0x0005f7, 0x000000, 0xfffc46,
0525     0x000000, 0x00022d, 0x000000, 0xfffedb, 0x000000,
0526     0x000081, 0x000000,
0527 };
0528
0529 /*
0530  * These values are sane defaults for the axg platform:
0531  * - OS = 64
0532  * - Latency = 38700 (?)
0533  *
0534  * TODO: There is a lot of different HCIC, LPFs and HPF configurations possible.
0535  *       the configuration may depend on the dmic used by the platform, the
0536  *       expected tradeoff between latency and quality, etc ... If/When other
0537  *       settings are required, we should add a fw interface to this driver to
0538  *       load new filter settings.
0539  */
0540 static const struct axg_pdm_filters axg_default_filters = {
0541     .hcic = {
0542         .shift = 0x15,
0543         .mult = 0x80,
0544         .steps = 7,
0545         .ds = 8,
0546     },
0547     .hpf = {
0548         .out_factor = 0x8000,
0549         .steps = 13,
0550     },
0551     .lpf = {
0552         [0] = {
0553             .ds = 2,
0554             .round_mode = 1,
0555             .tap = lpf1_default_tap,
0556             .tap_num = ARRAY_SIZE(lpf1_default_tap),
0557         },
0558         [1] = {
0559             .ds = 2,
0560             .round_mode = 0,
0561             .tap = lpf2_default_tap,
0562             .tap_num = ARRAY_SIZE(lpf2_default_tap),
0563         },
0564         [2] = {
0565             .ds = 2,
0566             .round_mode = 1,
0567             .tap = lpf3_default_tap,
0568             .tap_num = ARRAY_SIZE(lpf3_default_tap)
0569         },
0570     },
0571 };
0572
0573 static const struct axg_pdm_cfg axg_pdm_config = {
0574     .filters = &axg_default_filters,
0575     .sys_rate = 250000000,
0576 };
0577
0578 static const struct of_device_id axg_pdm_of_match[] = {
0579     {
0580         .compatible = "amlogic,axg-pdm",
0581         .data = &axg_pdm_config,
0582     }, {}
0583 };
0584 MODULE_DEVICE_TABLE(of, axg_pdm_of_match);
0585
0586 static int axg_pdm_probe(struct platform_device *pdev)
0587 {
0588     struct device *dev = &pdev->dev;
0589     struct axg_pdm *priv;
0590     void __iomem *regs;
0591
0592     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0593     if (!priv)
0594         return -ENOMEM;
0595     platform_set_drvdata(pdev, priv);
0596
0597     priv->cfg = of_device_get_match_data(dev);
0598     if (!priv->cfg) {
0599         dev_err(dev, "failed to match device\n");
0600         return -ENODEV;
0601     }
0602
0603     regs = devm_platform_ioremap_resource(pdev, 0);
0604     if (IS_ERR(regs))
0605         return PTR_ERR(regs);
0606
0607     priv->map = devm_regmap_init_mmio(dev, regs, &axg_pdm_regmap_cfg);
0608     if (IS_ERR(priv->map)) {
0609         dev_err(dev, "failed to init regmap: %ld\n",
0610             PTR_ERR(priv->map));
0611         return PTR_ERR(priv->map);
0612     }
0613
0614     priv->pclk = devm_clk_get(dev, "pclk");
0615     if (IS_ERR(priv->pclk))
0616         return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");
0617
0618     priv->dclk = devm_clk_get(dev, "dclk");
0619     if (IS_ERR(priv->dclk))
0620         return dev_err_probe(dev, PTR_ERR(priv->dclk), "failed to get dclk\n");
0621
0622     priv->sysclk = devm_clk_get(dev, "sysclk");
0623     if (IS_ERR(priv->sysclk))
0624         return dev_err_probe(dev, PTR_ERR(priv->sysclk), "failed to get dclk\n");
0625
0626     return devm_snd_soc_register_component(dev, &axg_pdm_component_drv,
0627                            &axg_pdm_dai_drv, 1);
0628 }
0629
0630 static struct platform_driver axg_pdm_pdrv = {
0631     .probe = axg_pdm_probe,
0632     .driver = {
0633         .name = "axg-pdm",
0634         .of_match_table = axg_pdm_of_match,
0635     },
0636 };
0637 module_platform_driver(axg_pdm_pdrv);
0638
0639 MODULE_DESCRIPTION("Amlogic AXG PDM Input driver");
0640 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
0641 MODULE_LICENSE("GPL v2");