soc/meson/axg-fifo.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Copyright (c) 2018 BayLibre, SAS.
0004  * Author: Jerome Brunet <jbrunet@baylibre.com>
0005  */
0006
0007 #ifndef _MESON_AXG_FIFO_H
0008 #define _MESON_AXG_FIFO_H
0009
0010 struct clk;
0011 struct platform_device;
0012 struct reg_field;
0013 struct regmap;
0014 struct regmap_field;
0015 struct reset_control;
0016
0017 struct snd_soc_component_driver;
0018 struct snd_soc_dai;
0019 struct snd_soc_dai_driver;
0020
0021 struct snd_soc_pcm_runtime;
0022
0023 #define AXG_FIFO_CH_MAX         128
0024 #define AXG_FIFO_RATES          (SNDRV_PCM_RATE_5512 |      \
0025                      SNDRV_PCM_RATE_8000_192000)
0026 #define AXG_FIFO_FORMATS        (SNDRV_PCM_FMTBIT_S8 |      \
0027                      SNDRV_PCM_FMTBIT_S16_LE |  \
0028                      SNDRV_PCM_FMTBIT_S20_LE |  \
0029                      SNDRV_PCM_FMTBIT_S24_LE |  \
0030                      SNDRV_PCM_FMTBIT_S32_LE |  \
0031                      SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
0032
0033 #define AXG_FIFO_BURST          8
0034
0035 #define FIFO_INT_ADDR_FINISH        BIT(0)
0036 #define FIFO_INT_ADDR_INT       BIT(1)
0037 #define FIFO_INT_COUNT_REPEAT       BIT(2)
0038 #define FIFO_INT_COUNT_ONCE     BIT(3)
0039 #define FIFO_INT_FIFO_ZERO      BIT(4)
0040 #define FIFO_INT_FIFO_DEPTH     BIT(5)
0041 #define FIFO_INT_MASK           GENMASK(7, 0)
0042
0043 #define FIFO_CTRL0          0x00
0044 #define  CTRL0_DMA_EN           BIT(31)
0045 #define  CTRL0_INT_EN(x)        ((x) << 16)
0046 #define  CTRL0_SEL_MASK         GENMASK(2, 0)
0047 #define  CTRL0_SEL_SHIFT        0
0048 #define FIFO_CTRL1          0x04
0049 #define  CTRL1_INT_CLR(x)       ((x) << 0)
0050 #define  CTRL1_STATUS2_SEL_MASK     GENMASK(11, 8)
0051 #define  CTRL1_STATUS2_SEL(x)       ((x) << 8)
0052 #define   STATUS2_SEL_DDR_READ      0
0053 #define  CTRL1_FRDDR_DEPTH_MASK     GENMASK(31, 24)
0054 #define  CTRL1_FRDDR_DEPTH(x)       ((x) << 24)
0055 #define FIFO_START_ADDR         0x08
0056 #define FIFO_FINISH_ADDR        0x0c
0057 #define FIFO_INT_ADDR           0x10
0058 #define FIFO_STATUS1            0x14
0059 #define  STATUS1_INT_STS(x)     ((x) << 0)
0060 #define FIFO_STATUS2            0x18
0061 #define FIFO_INIT_ADDR          0x24
0062 #define FIFO_CTRL2          0x28
0063
0064 struct axg_fifo {
0065     struct regmap *map;
0066     struct clk *pclk;
0067     struct reset_control *arb;
0068     struct regmap_field *field_threshold;
0069     unsigned int depth;
0070     int irq;
0071 };
0072
0073 struct axg_fifo_match_data {
0074     const struct snd_soc_component_driver *component_drv;
0075     struct snd_soc_dai_driver *dai_drv;
0076     struct reg_field field_threshold;
0077 };
0078
0079 int axg_fifo_pcm_open(struct snd_soc_component *component,
0080               struct snd_pcm_substream *ss);
0081 int axg_fifo_pcm_close(struct snd_soc_component *component,
0082                struct snd_pcm_substream *ss);
0083 int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
0084                struct snd_pcm_substream *ss,
0085                struct snd_pcm_hw_params *params);
0086 int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
0087                 struct snd_pcm_substream *ss,
0088                 struct snd_pcm_hw_params *params);
0089 int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
0090              struct snd_pcm_substream *ss);
0091 snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
0092                        struct snd_pcm_substream *ss);
0093 int axg_fifo_pcm_trigger(struct snd_soc_component *component,
0094              struct snd_pcm_substream *ss, int cmd);
0095
0096 int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
0097 int axg_fifo_probe(struct platform_device *pdev);
0098
0099 #endif /* _MESON_AXG_FIFO_H */