mediatek/mt8195/mt8195-dai-etdm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MediaTek ALSA SoC Audio DAI eTDM Control
0004  *
0005  * Copyright (c) 2021 MediaTek Inc.
0006  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
0007  *         Trevor Wu <trevor.wu@mediatek.com>
0008  */
0009
0010 #include <linux/delay.h>
0011 #include <linux/pm_runtime.h>
0012 #include <linux/regmap.h>
0013 #include <sound/pcm_params.h>
0014 #include "mt8195-afe-clk.h"
0015 #include "mt8195-afe-common.h"
0016 #include "mt8195-reg.h"
0017
0018 #define MT8195_ETDM_MAX_CHANNELS 24
0019 #define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000
0020 #define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START)
0021 #define ENUM_TO_STR(x)  #x
0022
0023 enum {
0024     MTK_DAI_ETDM_FORMAT_I2S = 0,
0025     MTK_DAI_ETDM_FORMAT_LJ,
0026     MTK_DAI_ETDM_FORMAT_RJ,
0027     MTK_DAI_ETDM_FORMAT_EIAJ,
0028     MTK_DAI_ETDM_FORMAT_DSPA,
0029     MTK_DAI_ETDM_FORMAT_DSPB,
0030 };
0031
0032 enum {
0033     MTK_DAI_ETDM_DATA_ONE_PIN = 0,
0034     MTK_DAI_ETDM_DATA_MULTI_PIN,
0035 };
0036
0037 enum {
0038     ETDM_IN,
0039     ETDM_OUT,
0040 };
0041
0042 enum {
0043     ETDM_IN_FROM_PAD,
0044     ETDM_IN_FROM_ETDM_OUT1,
0045     ETDM_IN_FROM_ETDM_OUT2,
0046 };
0047
0048 enum {
0049     ETDM_IN_SLAVE_FROM_PAD,
0050     ETDM_IN_SLAVE_FROM_ETDM_OUT1,
0051     ETDM_IN_SLAVE_FROM_ETDM_OUT2,
0052 };
0053
0054 enum {
0055     ETDM_OUT_SLAVE_FROM_PAD,
0056     ETDM_OUT_SLAVE_FROM_ETDM_IN1,
0057     ETDM_OUT_SLAVE_FROM_ETDM_IN2,
0058 };
0059
0060 enum {
0061     COWORK_ETDM_NONE = 0,
0062     COWORK_ETDM_IN1_M = 2,
0063     COWORK_ETDM_IN1_S = 3,
0064     COWORK_ETDM_IN2_M = 4,
0065     COWORK_ETDM_IN2_S = 5,
0066     COWORK_ETDM_OUT1_M = 10,
0067     COWORK_ETDM_OUT1_S = 11,
0068     COWORK_ETDM_OUT2_M = 12,
0069     COWORK_ETDM_OUT2_S = 13,
0070     COWORK_ETDM_OUT3_M = 14,
0071     COWORK_ETDM_OUT3_S = 15,
0072 };
0073
0074 enum {
0075     ETDM_RELATCH_TIMING_A1A2SYS,
0076     ETDM_RELATCH_TIMING_A3SYS,
0077     ETDM_RELATCH_TIMING_A4SYS,
0078 };
0079
0080 enum {
0081     ETDM_SYNC_NONE,
0082     ETDM_SYNC_FROM_IN1,
0083     ETDM_SYNC_FROM_IN2,
0084     ETDM_SYNC_FROM_OUT1,
0085     ETDM_SYNC_FROM_OUT2,
0086     ETDM_SYNC_FROM_OUT3,
0087 };
0088
0089 struct etdm_con_reg {
0090     unsigned int con0;
0091     unsigned int con1;
0092     unsigned int con2;
0093     unsigned int con3;
0094     unsigned int con4;
0095     unsigned int con5;
0096 };
0097
0098 struct mtk_dai_etdm_rate {
0099     unsigned int rate;
0100     unsigned int reg_value;
0101 };
0102
0103 struct mtk_dai_etdm_priv {
0104     unsigned int clock_mode;
0105     unsigned int data_mode;
0106     bool slave_mode;
0107     bool lrck_inv;
0108     bool bck_inv;
0109     unsigned int format;
0110     unsigned int slots;
0111     unsigned int lrck_width;
0112     unsigned int mclk_freq;
0113     unsigned int mclk_apll;
0114     unsigned int mclk_dir;
0115     int cowork_source_id; //dai id
0116     unsigned int cowork_slv_count;
0117     int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id
0118     bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS];
0119     unsigned int en_ref_cnt;
0120 };
0121
0122 static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = {
0123     { .rate = 8000, .reg_value = 0, },
0124     { .rate = 12000, .reg_value = 1, },
0125     { .rate = 16000, .reg_value = 2, },
0126     { .rate = 24000, .reg_value = 3, },
0127     { .rate = 32000, .reg_value = 4, },
0128     { .rate = 48000, .reg_value = 5, },
0129     { .rate = 96000, .reg_value = 7, },
0130     { .rate = 192000, .reg_value = 9, },
0131     { .rate = 384000, .reg_value = 11, },
0132     { .rate = 11025, .reg_value = 16, },
0133     { .rate = 22050, .reg_value = 17, },
0134     { .rate = 44100, .reg_value = 18, },
0135     { .rate = 88200, .reg_value = 19, },
0136     { .rate = 176400, .reg_value = 20, },
0137     { .rate = 352800, .reg_value = 21, },
0138 };
0139
0140 static int get_etdm_fs_timing(unsigned int rate)
0141 {
0142     int i;
0143
0144     for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++)
0145         if (mt8195_etdm_rates[i].rate == rate)
0146             return mt8195_etdm_rates[i].reg_value;
0147
0148     return -EINVAL;
0149 }
0150
0151 static unsigned int get_etdm_ch_fixup(unsigned int channels)
0152 {
0153     if (channels > 16)
0154         return 24;
0155     else if (channels > 8)
0156         return 16;
0157     else if (channels > 4)
0158         return 8;
0159     else if (channels > 2)
0160         return 4;
0161     else
0162         return 2;
0163 }
0164
0165 static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg)
0166 {
0167     switch (dai_id) {
0168     case MT8195_AFE_IO_ETDM1_IN:
0169         etdm_reg->con0 = ETDM_IN1_CON0;
0170         etdm_reg->con1 = ETDM_IN1_CON1;
0171         etdm_reg->con2 = ETDM_IN1_CON2;
0172         etdm_reg->con3 = ETDM_IN1_CON3;
0173         etdm_reg->con4 = ETDM_IN1_CON4;
0174         etdm_reg->con5 = ETDM_IN1_CON5;
0175         break;
0176     case MT8195_AFE_IO_ETDM2_IN:
0177         etdm_reg->con0 = ETDM_IN2_CON0;
0178         etdm_reg->con1 = ETDM_IN2_CON1;
0179         etdm_reg->con2 = ETDM_IN2_CON2;
0180         etdm_reg->con3 = ETDM_IN2_CON3;
0181         etdm_reg->con4 = ETDM_IN2_CON4;
0182         etdm_reg->con5 = ETDM_IN2_CON5;
0183         break;
0184     case MT8195_AFE_IO_ETDM1_OUT:
0185         etdm_reg->con0 = ETDM_OUT1_CON0;
0186         etdm_reg->con1 = ETDM_OUT1_CON1;
0187         etdm_reg->con2 = ETDM_OUT1_CON2;
0188         etdm_reg->con3 = ETDM_OUT1_CON3;
0189         etdm_reg->con4 = ETDM_OUT1_CON4;
0190         etdm_reg->con5 = ETDM_OUT1_CON5;
0191         break;
0192     case MT8195_AFE_IO_ETDM2_OUT:
0193         etdm_reg->con0 = ETDM_OUT2_CON0;
0194         etdm_reg->con1 = ETDM_OUT2_CON1;
0195         etdm_reg->con2 = ETDM_OUT2_CON2;
0196         etdm_reg->con3 = ETDM_OUT2_CON3;
0197         etdm_reg->con4 = ETDM_OUT2_CON4;
0198         etdm_reg->con5 = ETDM_OUT2_CON5;
0199         break;
0200     case MT8195_AFE_IO_ETDM3_OUT:
0201     case MT8195_AFE_IO_DPTX:
0202         etdm_reg->con0 = ETDM_OUT3_CON0;
0203         etdm_reg->con1 = ETDM_OUT3_CON1;
0204         etdm_reg->con2 = ETDM_OUT3_CON2;
0205         etdm_reg->con3 = ETDM_OUT3_CON3;
0206         etdm_reg->con4 = ETDM_OUT3_CON4;
0207         etdm_reg->con5 = ETDM_OUT3_CON5;
0208         break;
0209     default:
0210         return -EINVAL;
0211     }
0212     return 0;
0213 }
0214
0215 static int get_etdm_dir(unsigned int dai_id)
0216 {
0217     switch (dai_id) {
0218     case MT8195_AFE_IO_ETDM1_IN:
0219     case MT8195_AFE_IO_ETDM2_IN:
0220         return ETDM_IN;
0221     case MT8195_AFE_IO_ETDM1_OUT:
0222     case MT8195_AFE_IO_ETDM2_OUT:
0223     case MT8195_AFE_IO_ETDM3_OUT:
0224         return ETDM_OUT;
0225     default:
0226         return -EINVAL;
0227     }
0228 }
0229
0230 static int get_etdm_wlen(unsigned int bitwidth)
0231 {
0232     return bitwidth <= 16 ? 16 : 32;
0233 }
0234
0235 static int is_cowork_mode(struct snd_soc_dai *dai)
0236 {
0237     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0238     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0239     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
0240
0241     return (etdm_data->cowork_slv_count > 0 ||
0242         etdm_data->cowork_source_id != COWORK_ETDM_NONE);
0243 }
0244
0245 static int sync_to_dai_id(int source_sel)
0246 {
0247     switch (source_sel) {
0248     case ETDM_SYNC_FROM_IN1:
0249         return MT8195_AFE_IO_ETDM1_IN;
0250     case ETDM_SYNC_FROM_IN2:
0251         return MT8195_AFE_IO_ETDM2_IN;
0252     case ETDM_SYNC_FROM_OUT1:
0253         return MT8195_AFE_IO_ETDM1_OUT;
0254     case ETDM_SYNC_FROM_OUT2:
0255         return MT8195_AFE_IO_ETDM2_OUT;
0256     case ETDM_SYNC_FROM_OUT3:
0257         return MT8195_AFE_IO_ETDM3_OUT;
0258     default:
0259         return 0;
0260     }
0261 }
0262
0263 static int get_etdm_cowork_master_id(struct snd_soc_dai *dai)
0264 {
0265     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0266     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0267     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
0268     int dai_id = etdm_data->cowork_source_id;
0269
0270     if (dai_id == COWORK_ETDM_NONE)
0271         dai_id = dai->id;
0272
0273     return dai_id;
0274 }
0275
0276 static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = {
0277     SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0),
0278     SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0),
0279     SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0),
0280     SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0),
0281 };
0282
0283 static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = {
0284     SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0),
0285     SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0),
0286     SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0),
0287     SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0),
0288 };
0289
0290 static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = {
0291     SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0),
0292     SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0),
0293 };
0294
0295 static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = {
0296     SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0),
0297     SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0),
0298 };
0299
0300 static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = {
0301     SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0),
0302     SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0),
0303 };
0304
0305 static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = {
0306     SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0),
0307     SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0),
0308 };
0309
0310 static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = {
0311     SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0),
0312     SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0),
0313 };
0314
0315 static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = {
0316     SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0),
0317     SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0),
0318 };
0319
0320 static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = {
0321     SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0),
0322     SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0),
0323 };
0324
0325 static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = {
0326     SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0),
0327     SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0),
0328 };
0329
0330 static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = {
0331     SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0),
0332     SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0),
0333 };
0334
0335 static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = {
0336     SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0),
0337     SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0),
0338 };
0339
0340 static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = {
0341     SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0),
0342     SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0),
0343 };
0344
0345 static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = {
0346     SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0),
0347     SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0),
0348 };
0349
0350 static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = {
0351     SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0),
0352     SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0),
0353 };
0354
0355 static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = {
0356     SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0),
0357     SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0),
0358 };
0359
0360 static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = {
0361     SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0),
0362     SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0),
0363 };
0364
0365 static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = {
0366     SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0),
0367     SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0),
0368 };
0369
0370 static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = {
0371     SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0),
0372     SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0),
0373 };
0374
0375 static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = {
0376     SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0),
0377     SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0),
0378 };
0379
0380 static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = {
0381     SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0),
0382     SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0),
0383 };
0384
0385 static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = {
0386     SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0),
0387     SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0),
0388 };
0389
0390 static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = {
0391     SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0),
0392     SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0),
0393 };
0394
0395 static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = {
0396     SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0),
0397     SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0),
0398 };
0399
0400 static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = {
0401     SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0),
0402     SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0),
0403     SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0),
0404     SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0),
0405 };
0406
0407 static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = {
0408     SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0),
0409     SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0),
0410     SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0),
0411     SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0),
0412 };
0413
0414 static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = {
0415     SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0),
0416     SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0),
0417 };
0418
0419 static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = {
0420     SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0),
0421     SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0),
0422 };
0423
0424 static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = {
0425     SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0),
0426     SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0),
0427 };
0428
0429 static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = {
0430     SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0),
0431     SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0),
0432 };
0433
0434 static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = {
0435     SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0),
0436     SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0),
0437 };
0438
0439 static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = {
0440     SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0),
0441     SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0),
0442 };
0443
0444 static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = {
0445     SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0),
0446     SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0),
0447 };
0448
0449 static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = {
0450     SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0),
0451     SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0),
0452 };
0453
0454 static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = {
0455     SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0),
0456     SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0),
0457 };
0458
0459 static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = {
0460     SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0),
0461     SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0),
0462 };
0463
0464 static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = {
0465     SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0),
0466     SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0),
0467 };
0468
0469 static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = {
0470     SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0),
0471     SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0),
0472 };
0473
0474 static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = {
0475     SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0),
0476     SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0),
0477 };
0478
0479 static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = {
0480     SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0),
0481     SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0),
0482 };
0483
0484 static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = {
0485     SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0),
0486     SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0),
0487 };
0488
0489 static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = {
0490     SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0),
0491     SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0),
0492 };
0493
0494 static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = {
0495     SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0),
0496     SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0),
0497 };
0498
0499 static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = {
0500     SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0),
0501     SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0),
0502 };
0503
0504 static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = {
0505     SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0),
0506     SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0),
0507 };
0508
0509 static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = {
0510     SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0),
0511     SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0),
0512 };
0513
0514 static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = {
0515     SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0),
0516     SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0),
0517 };
0518
0519 static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = {
0520     SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0),
0521     SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0),
0522 };
0523
0524 static const char * const mt8195_etdm_clk_src_sel_text[] = {
0525     "26m",
0526     "a1sys_a2sys",
0527     "a3sys",
0528     "a4sys",
0529 };
0530
0531 static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum,
0532     mt8195_etdm_clk_src_sel_text);
0533
0534 static const char * const hdmitx_dptx_mux_map[] = {
0535     "Disconnect", "Connect",
0536 };
0537
0538 static int hdmitx_dptx_mux_map_value[] = {
0539     0, 1,
0540 };
0541
0542 /* HDMI_OUT_MUX */
0543 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum,
0544                 SND_SOC_NOPM,
0545                 0,
0546                 1,
0547                 hdmitx_dptx_mux_map,
0548                 hdmitx_dptx_mux_map_value);
0549
0550 static const struct snd_kcontrol_new hdmi_out_mux_control =
0551     SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum);
0552
0553 /* DPTX_OUT_MUX */
0554 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum,
0555                 SND_SOC_NOPM,
0556                 0,
0557                 1,
0558                 hdmitx_dptx_mux_map,
0559                 hdmitx_dptx_mux_map_value);
0560
0561 static const struct snd_kcontrol_new dptx_out_mux_control =
0562     SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum);
0563
0564 /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */
0565 static const char *const afe_conn_hdmi_mux_map[] = {
0566     "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
0567 };
0568
0569 static int afe_conn_hdmi_mux_map_value[] = {
0570     0, 1, 2, 3, 4, 5, 6, 7,
0571 };
0572
0573 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
0574                 AFE_TDMOUT_CONN0,
0575                 0,
0576                 0xf,
0577                 afe_conn_hdmi_mux_map,
0578                 afe_conn_hdmi_mux_map_value);
0579
0580 static const struct snd_kcontrol_new hdmi_ch0_mux_control =
0581     SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
0582
0583 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
0584                 AFE_TDMOUT_CONN0,
0585                 4,
0586                 0xf,
0587                 afe_conn_hdmi_mux_map,
0588                 afe_conn_hdmi_mux_map_value);
0589
0590 static const struct snd_kcontrol_new hdmi_ch1_mux_control =
0591     SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
0592
0593 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
0594                 AFE_TDMOUT_CONN0,
0595                 8,
0596                 0xf,
0597                 afe_conn_hdmi_mux_map,
0598                 afe_conn_hdmi_mux_map_value);
0599
0600 static const struct snd_kcontrol_new hdmi_ch2_mux_control =
0601     SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
0602
0603 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
0604                 AFE_TDMOUT_CONN0,
0605                 12,
0606                 0xf,
0607                 afe_conn_hdmi_mux_map,
0608                 afe_conn_hdmi_mux_map_value);
0609
0610 static const struct snd_kcontrol_new hdmi_ch3_mux_control =
0611     SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
0612
0613 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
0614                 AFE_TDMOUT_CONN0,
0615                 16,
0616                 0xf,
0617                 afe_conn_hdmi_mux_map,
0618                 afe_conn_hdmi_mux_map_value);
0619
0620 static const struct snd_kcontrol_new hdmi_ch4_mux_control =
0621     SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
0622
0623 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
0624                 AFE_TDMOUT_CONN0,
0625                 20,
0626                 0xf,
0627                 afe_conn_hdmi_mux_map,
0628                 afe_conn_hdmi_mux_map_value);
0629
0630 static const struct snd_kcontrol_new hdmi_ch5_mux_control =
0631     SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
0632
0633 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
0634                 AFE_TDMOUT_CONN0,
0635                 24,
0636                 0xf,
0637                 afe_conn_hdmi_mux_map,
0638                 afe_conn_hdmi_mux_map_value);
0639
0640 static const struct snd_kcontrol_new hdmi_ch6_mux_control =
0641     SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
0642
0643 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
0644                 AFE_TDMOUT_CONN0,
0645                 28,
0646                 0xf,
0647                 afe_conn_hdmi_mux_map,
0648                 afe_conn_hdmi_mux_map_value);
0649
0650 static const struct snd_kcontrol_new hdmi_ch7_mux_control =
0651     SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
0652
0653 static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol,
0654                        struct snd_ctl_elem_value *ucontrol)
0655 {
0656     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0657     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0658     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0659     unsigned int source = ucontrol->value.enumerated.item[0];
0660     unsigned int val;
0661     unsigned int mask;
0662     unsigned int reg;
0663
0664     if (source >= e->items)
0665         return -EINVAL;
0666
0667     reg = 0;
0668     if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
0669         reg = ETDM_OUT1_CON4;
0670         mask = ETDM_OUT_CON4_CLOCK_MASK;
0671         val = ETDM_OUT_CON4_CLOCK(source);
0672     } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
0673         reg = ETDM_OUT2_CON4;
0674         mask = ETDM_OUT_CON4_CLOCK_MASK;
0675         val = ETDM_OUT_CON4_CLOCK(source);
0676     } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
0677         reg = ETDM_OUT3_CON4;
0678         mask = ETDM_OUT_CON4_CLOCK_MASK;
0679         val = ETDM_OUT_CON4_CLOCK(source);
0680     } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
0681         reg = ETDM_IN1_CON2;
0682         mask = ETDM_IN_CON2_CLOCK_MASK;
0683         val = ETDM_IN_CON2_CLOCK(source);
0684     } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
0685         reg = ETDM_IN2_CON2;
0686         mask = ETDM_IN_CON2_CLOCK_MASK;
0687         val = ETDM_IN_CON2_CLOCK(source);
0688     }
0689
0690     if (reg)
0691         regmap_update_bits(afe->regmap, reg, mask, val);
0692
0693     return 0;
0694 }
0695
0696 static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol,
0697                        struct snd_ctl_elem_value *ucontrol)
0698 {
0699     struct snd_soc_component *component =
0700         snd_soc_kcontrol_component(kcontrol);
0701     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0702     unsigned int value = 0;
0703     unsigned int reg = 0;
0704     unsigned int mask = 0;
0705     unsigned int shift = 0;
0706
0707     if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
0708         reg = ETDM_OUT1_CON4;
0709         mask = ETDM_OUT_CON4_CLOCK_MASK;
0710         shift = ETDM_OUT_CON4_CLOCK_SHIFT;
0711     } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
0712         reg = ETDM_OUT2_CON4;
0713         mask = ETDM_OUT_CON4_CLOCK_MASK;
0714         shift = ETDM_OUT_CON4_CLOCK_SHIFT;
0715     } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
0716         reg = ETDM_OUT3_CON4;
0717         mask = ETDM_OUT_CON4_CLOCK_MASK;
0718         shift = ETDM_OUT_CON4_CLOCK_SHIFT;
0719     } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
0720         reg = ETDM_IN1_CON2;
0721         mask = ETDM_IN_CON2_CLOCK_MASK;
0722         shift = ETDM_IN_CON2_CLOCK_SHIFT;
0723     } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
0724         reg = ETDM_IN2_CON2;
0725         mask = ETDM_IN_CON2_CLOCK_MASK;
0726         shift = ETDM_IN_CON2_CLOCK_SHIFT;
0727     }
0728
0729     if (reg)
0730         regmap_read(afe->regmap, reg, &value);
0731
0732     value &= mask;
0733     value >>= shift;
0734     ucontrol->value.enumerated.item[0] = value;
0735     return 0;
0736 }
0737
0738 static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = {
0739     SOC_ENUM_EXT("ETDM_OUT1_Clock_Source",
0740              etdmout_clk_src_enum,
0741              mt8195_etdm_clk_src_sel_get,
0742              mt8195_etdm_clk_src_sel_put),
0743     SOC_ENUM_EXT("ETDM_OUT2_Clock_Source",
0744              etdmout_clk_src_enum,
0745              mt8195_etdm_clk_src_sel_get,
0746              mt8195_etdm_clk_src_sel_put),
0747     SOC_ENUM_EXT("ETDM_OUT3_Clock_Source",
0748              etdmout_clk_src_enum,
0749              mt8195_etdm_clk_src_sel_get,
0750              mt8195_etdm_clk_src_sel_put),
0751     SOC_ENUM_EXT("ETDM_IN1_Clock_Source",
0752              etdmout_clk_src_enum,
0753              mt8195_etdm_clk_src_sel_get,
0754              mt8195_etdm_clk_src_sel_put),
0755     SOC_ENUM_EXT("ETDM_IN2_Clock_Source",
0756              etdmout_clk_src_enum,
0757              mt8195_etdm_clk_src_sel_get,
0758              mt8195_etdm_clk_src_sel_put),
0759 };
0760
0761 static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
0762     /* eTDM_IN2 */
0763     SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0),
0764     SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0),
0765     SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0),
0766     SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0),
0767     SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0),
0768     SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0),
0769     SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0),
0770     SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0),
0771
0772     /* eTDM_IN1 */
0773     SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0),
0774     SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0),
0775     SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0),
0776     SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0),
0777     SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0),
0778     SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0),
0779     SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0),
0780     SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0),
0781     SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0),
0782     SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0),
0783     SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0),
0784     SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0),
0785     SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0),
0786     SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0),
0787     SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0),
0788     SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0),
0789     SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0),
0790     SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0),
0791     SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0),
0792     SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0),
0793     SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0),
0794     SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0),
0795     SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0),
0796     SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0),
0797
0798     /* eTDM_OUT2 */
0799     SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0,
0800                mtk_dai_etdm_o048_mix,
0801                ARRAY_SIZE(mtk_dai_etdm_o048_mix)),
0802     SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0,
0803                mtk_dai_etdm_o049_mix,
0804                ARRAY_SIZE(mtk_dai_etdm_o049_mix)),
0805     SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0,
0806                mtk_dai_etdm_o050_mix,
0807                ARRAY_SIZE(mtk_dai_etdm_o050_mix)),
0808     SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0,
0809                mtk_dai_etdm_o051_mix,
0810                ARRAY_SIZE(mtk_dai_etdm_o051_mix)),
0811     SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0,
0812                mtk_dai_etdm_o052_mix,
0813                ARRAY_SIZE(mtk_dai_etdm_o052_mix)),
0814     SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0,
0815                mtk_dai_etdm_o053_mix,
0816                ARRAY_SIZE(mtk_dai_etdm_o053_mix)),
0817     SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0,
0818                mtk_dai_etdm_o054_mix,
0819                ARRAY_SIZE(mtk_dai_etdm_o054_mix)),
0820     SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0,
0821                mtk_dai_etdm_o055_mix,
0822                ARRAY_SIZE(mtk_dai_etdm_o055_mix)),
0823     SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0,
0824                mtk_dai_etdm_o056_mix,
0825                ARRAY_SIZE(mtk_dai_etdm_o056_mix)),
0826     SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0,
0827                mtk_dai_etdm_o057_mix,
0828                ARRAY_SIZE(mtk_dai_etdm_o057_mix)),
0829     SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0,
0830                mtk_dai_etdm_o058_mix,
0831                ARRAY_SIZE(mtk_dai_etdm_o058_mix)),
0832     SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0,
0833                mtk_dai_etdm_o059_mix,
0834                ARRAY_SIZE(mtk_dai_etdm_o059_mix)),
0835     SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0,
0836                mtk_dai_etdm_o060_mix,
0837                ARRAY_SIZE(mtk_dai_etdm_o060_mix)),
0838     SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0,
0839                mtk_dai_etdm_o061_mix,
0840                ARRAY_SIZE(mtk_dai_etdm_o061_mix)),
0841     SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0,
0842                mtk_dai_etdm_o062_mix,
0843                ARRAY_SIZE(mtk_dai_etdm_o062_mix)),
0844     SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0,
0845                mtk_dai_etdm_o063_mix,
0846                ARRAY_SIZE(mtk_dai_etdm_o063_mix)),
0847     SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0,
0848                mtk_dai_etdm_o064_mix,
0849                ARRAY_SIZE(mtk_dai_etdm_o064_mix)),
0850     SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0,
0851                mtk_dai_etdm_o065_mix,
0852                ARRAY_SIZE(mtk_dai_etdm_o065_mix)),
0853     SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0,
0854                mtk_dai_etdm_o066_mix,
0855                ARRAY_SIZE(mtk_dai_etdm_o066_mix)),
0856     SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0,
0857                mtk_dai_etdm_o067_mix,
0858                ARRAY_SIZE(mtk_dai_etdm_o067_mix)),
0859     SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0,
0860                mtk_dai_etdm_o068_mix,
0861                ARRAY_SIZE(mtk_dai_etdm_o068_mix)),
0862     SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0,
0863                mtk_dai_etdm_o069_mix,
0864                ARRAY_SIZE(mtk_dai_etdm_o069_mix)),
0865     SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0,
0866                mtk_dai_etdm_o070_mix,
0867                ARRAY_SIZE(mtk_dai_etdm_o070_mix)),
0868     SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0,
0869                mtk_dai_etdm_o071_mix,
0870                ARRAY_SIZE(mtk_dai_etdm_o071_mix)),
0871
0872     /* eTDM_OUT1 */
0873     SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0,
0874                mtk_dai_etdm_o072_mix,
0875                ARRAY_SIZE(mtk_dai_etdm_o072_mix)),
0876     SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0,
0877                mtk_dai_etdm_o073_mix,
0878                ARRAY_SIZE(mtk_dai_etdm_o073_mix)),
0879     SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0,
0880                mtk_dai_etdm_o074_mix,
0881                ARRAY_SIZE(mtk_dai_etdm_o074_mix)),
0882     SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0,
0883                mtk_dai_etdm_o075_mix,
0884                ARRAY_SIZE(mtk_dai_etdm_o075_mix)),
0885     SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0,
0886                mtk_dai_etdm_o076_mix,
0887                ARRAY_SIZE(mtk_dai_etdm_o076_mix)),
0888     SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0,
0889                mtk_dai_etdm_o077_mix,
0890                ARRAY_SIZE(mtk_dai_etdm_o077_mix)),
0891     SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0,
0892                mtk_dai_etdm_o078_mix,
0893                ARRAY_SIZE(mtk_dai_etdm_o078_mix)),
0894     SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0,
0895                mtk_dai_etdm_o079_mix,
0896                ARRAY_SIZE(mtk_dai_etdm_o079_mix)),
0897     SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0,
0898                mtk_dai_etdm_o080_mix,
0899                ARRAY_SIZE(mtk_dai_etdm_o080_mix)),
0900     SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0,
0901                mtk_dai_etdm_o081_mix,
0902                ARRAY_SIZE(mtk_dai_etdm_o081_mix)),
0903     SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0,
0904                mtk_dai_etdm_o082_mix,
0905                ARRAY_SIZE(mtk_dai_etdm_o082_mix)),
0906     SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0,
0907                mtk_dai_etdm_o083_mix,
0908                ARRAY_SIZE(mtk_dai_etdm_o083_mix)),
0909     SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0,
0910                mtk_dai_etdm_o084_mix,
0911                ARRAY_SIZE(mtk_dai_etdm_o084_mix)),
0912     SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0,
0913                mtk_dai_etdm_o085_mix,
0914                ARRAY_SIZE(mtk_dai_etdm_o085_mix)),
0915     SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0,
0916                mtk_dai_etdm_o086_mix,
0917                ARRAY_SIZE(mtk_dai_etdm_o086_mix)),
0918     SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0,
0919                mtk_dai_etdm_o087_mix,
0920                ARRAY_SIZE(mtk_dai_etdm_o087_mix)),
0921     SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0,
0922                mtk_dai_etdm_o088_mix,
0923                ARRAY_SIZE(mtk_dai_etdm_o088_mix)),
0924     SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0,
0925                mtk_dai_etdm_o089_mix,
0926                ARRAY_SIZE(mtk_dai_etdm_o089_mix)),
0927     SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0,
0928                mtk_dai_etdm_o090_mix,
0929                ARRAY_SIZE(mtk_dai_etdm_o090_mix)),
0930     SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0,
0931                mtk_dai_etdm_o091_mix,
0932                ARRAY_SIZE(mtk_dai_etdm_o091_mix)),
0933     SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0,
0934                mtk_dai_etdm_o092_mix,
0935                ARRAY_SIZE(mtk_dai_etdm_o092_mix)),
0936     SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0,
0937                mtk_dai_etdm_o093_mix,
0938                ARRAY_SIZE(mtk_dai_etdm_o093_mix)),
0939     SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0,
0940                mtk_dai_etdm_o094_mix,
0941                ARRAY_SIZE(mtk_dai_etdm_o094_mix)),
0942     SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0,
0943                mtk_dai_etdm_o095_mix,
0944                ARRAY_SIZE(mtk_dai_etdm_o095_mix)),
0945
0946     /* eTDM_OUT3 */
0947     SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0,
0948              &hdmi_out_mux_control),
0949     SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0,
0950              &dptx_out_mux_control),
0951
0952     SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
0953              &hdmi_ch0_mux_control),
0954     SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
0955              &hdmi_ch1_mux_control),
0956     SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
0957              &hdmi_ch2_mux_control),
0958     SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
0959              &hdmi_ch3_mux_control),
0960     SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
0961              &hdmi_ch4_mux_control),
0962     SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
0963              &hdmi_ch5_mux_control),
0964     SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
0965              &hdmi_ch6_mux_control),
0966     SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
0967              &hdmi_ch7_mux_control),
0968
0969     SND_SOC_DAPM_INPUT("ETDM_INPUT"),
0970     SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"),
0971 };
0972
0973 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
0974     {"I012", NULL, "ETDM2 Capture"},
0975     {"I013", NULL, "ETDM2 Capture"},
0976     {"I014", NULL, "ETDM2 Capture"},
0977     {"I015", NULL, "ETDM2 Capture"},
0978     {"I016", NULL, "ETDM2 Capture"},
0979     {"I017", NULL, "ETDM2 Capture"},
0980     {"I018", NULL, "ETDM2 Capture"},
0981     {"I019", NULL, "ETDM2 Capture"},
0982
0983     {"I072", NULL, "ETDM1 Capture"},
0984     {"I073", NULL, "ETDM1 Capture"},
0985     {"I074", NULL, "ETDM1 Capture"},
0986     {"I075", NULL, "ETDM1 Capture"},
0987     {"I076", NULL, "ETDM1 Capture"},
0988     {"I077", NULL, "ETDM1 Capture"},
0989     {"I078", NULL, "ETDM1 Capture"},
0990     {"I079", NULL, "ETDM1 Capture"},
0991     {"I080", NULL, "ETDM1 Capture"},
0992     {"I081", NULL, "ETDM1 Capture"},
0993     {"I082", NULL, "ETDM1 Capture"},
0994     {"I083", NULL, "ETDM1 Capture"},
0995     {"I084", NULL, "ETDM1 Capture"},
0996     {"I085", NULL, "ETDM1 Capture"},
0997     {"I086", NULL, "ETDM1 Capture"},
0998     {"I087", NULL, "ETDM1 Capture"},
0999     {"I088", NULL, "ETDM1 Capture"},
1000     {"I089", NULL, "ETDM1 Capture"},
1001     {"I090", NULL, "ETDM1 Capture"},
1002     {"I091", NULL, "ETDM1 Capture"},
1003     {"I092", NULL, "ETDM1 Capture"},
1004     {"I093", NULL, "ETDM1 Capture"},
1005     {"I094", NULL, "ETDM1 Capture"},
1006     {"I095", NULL, "ETDM1 Capture"},
1007
1008     {"UL8", NULL, "ETDM1 Capture"},
1009     {"UL3", NULL, "ETDM2 Capture"},
1010
1011     {"ETDM2 Playback", NULL, "O048"},
1012     {"ETDM2 Playback", NULL, "O049"},
1013     {"ETDM2 Playback", NULL, "O050"},
1014     {"ETDM2 Playback", NULL, "O051"},
1015     {"ETDM2 Playback", NULL, "O052"},
1016     {"ETDM2 Playback", NULL, "O053"},
1017     {"ETDM2 Playback", NULL, "O054"},
1018     {"ETDM2 Playback", NULL, "O055"},
1019     {"ETDM2 Playback", NULL, "O056"},
1020     {"ETDM2 Playback", NULL, "O057"},
1021     {"ETDM2 Playback", NULL, "O058"},
1022     {"ETDM2 Playback", NULL, "O059"},
1023     {"ETDM2 Playback", NULL, "O060"},
1024     {"ETDM2 Playback", NULL, "O061"},
1025     {"ETDM2 Playback", NULL, "O062"},
1026     {"ETDM2 Playback", NULL, "O063"},
1027     {"ETDM2 Playback", NULL, "O064"},
1028     {"ETDM2 Playback", NULL, "O065"},
1029     {"ETDM2 Playback", NULL, "O066"},
1030     {"ETDM2 Playback", NULL, "O067"},
1031     {"ETDM2 Playback", NULL, "O068"},
1032     {"ETDM2 Playback", NULL, "O069"},
1033     {"ETDM2 Playback", NULL, "O070"},
1034     {"ETDM2 Playback", NULL, "O071"},
1035
1036     {"ETDM1 Playback", NULL, "O072"},
1037     {"ETDM1 Playback", NULL, "O073"},
1038     {"ETDM1 Playback", NULL, "O074"},
1039     {"ETDM1 Playback", NULL, "O075"},
1040     {"ETDM1 Playback", NULL, "O076"},
1041     {"ETDM1 Playback", NULL, "O077"},
1042     {"ETDM1 Playback", NULL, "O078"},
1043     {"ETDM1 Playback", NULL, "O079"},
1044     {"ETDM1 Playback", NULL, "O080"},
1045     {"ETDM1 Playback", NULL, "O081"},
1046     {"ETDM1 Playback", NULL, "O082"},
1047     {"ETDM1 Playback", NULL, "O083"},
1048     {"ETDM1 Playback", NULL, "O084"},
1049     {"ETDM1 Playback", NULL, "O085"},
1050     {"ETDM1 Playback", NULL, "O086"},
1051     {"ETDM1 Playback", NULL, "O087"},
1052     {"ETDM1 Playback", NULL, "O088"},
1053     {"ETDM1 Playback", NULL, "O089"},
1054     {"ETDM1 Playback", NULL, "O090"},
1055     {"ETDM1 Playback", NULL, "O091"},
1056     {"ETDM1 Playback", NULL, "O092"},
1057     {"ETDM1 Playback", NULL, "O093"},
1058     {"ETDM1 Playback", NULL, "O094"},
1059     {"ETDM1 Playback", NULL, "O095"},
1060
1061     {"O048", "I020 Switch", "I020"},
1062     {"O049", "I021 Switch", "I021"},
1063
1064     {"O048", "I022 Switch", "I022"},
1065     {"O049", "I023 Switch", "I023"},
1066     {"O050", "I024 Switch", "I024"},
1067     {"O051", "I025 Switch", "I025"},
1068     {"O052", "I026 Switch", "I026"},
1069     {"O053", "I027 Switch", "I027"},
1070     {"O054", "I028 Switch", "I028"},
1071     {"O055", "I029 Switch", "I029"},
1072     {"O056", "I030 Switch", "I030"},
1073     {"O057", "I031 Switch", "I031"},
1074     {"O058", "I032 Switch", "I032"},
1075     {"O059", "I033 Switch", "I033"},
1076     {"O060", "I034 Switch", "I034"},
1077     {"O061", "I035 Switch", "I035"},
1078     {"O062", "I036 Switch", "I036"},
1079     {"O063", "I037 Switch", "I037"},
1080     {"O064", "I038 Switch", "I038"},
1081     {"O065", "I039 Switch", "I039"},
1082     {"O066", "I040 Switch", "I040"},
1083     {"O067", "I041 Switch", "I041"},
1084     {"O068", "I042 Switch", "I042"},
1085     {"O069", "I043 Switch", "I043"},
1086     {"O070", "I044 Switch", "I044"},
1087     {"O071", "I045 Switch", "I045"},
1088
1089     {"O048", "I046 Switch", "I046"},
1090     {"O049", "I047 Switch", "I047"},
1091     {"O050", "I048 Switch", "I048"},
1092     {"O051", "I049 Switch", "I049"},
1093     {"O052", "I050 Switch", "I050"},
1094     {"O053", "I051 Switch", "I051"},
1095     {"O054", "I052 Switch", "I052"},
1096     {"O055", "I053 Switch", "I053"},
1097     {"O056", "I054 Switch", "I054"},
1098     {"O057", "I055 Switch", "I055"},
1099     {"O058", "I056 Switch", "I056"},
1100     {"O059", "I057 Switch", "I057"},
1101     {"O060", "I058 Switch", "I058"},
1102     {"O061", "I059 Switch", "I059"},
1103     {"O062", "I060 Switch", "I060"},
1104     {"O063", "I061 Switch", "I061"},
1105     {"O064", "I062 Switch", "I062"},
1106     {"O065", "I063 Switch", "I063"},
1107     {"O066", "I064 Switch", "I064"},
1108     {"O067", "I065 Switch", "I065"},
1109     {"O068", "I066 Switch", "I066"},
1110     {"O069", "I067 Switch", "I067"},
1111     {"O070", "I068 Switch", "I068"},
1112     {"O071", "I069 Switch", "I069"},
1113
1114     {"O048", "I070 Switch", "I070"},
1115     {"O049", "I071 Switch", "I071"},
1116
1117     {"O072", "I020 Switch", "I020"},
1118     {"O073", "I021 Switch", "I021"},
1119
1120     {"O072", "I022 Switch", "I022"},
1121     {"O073", "I023 Switch", "I023"},
1122     {"O074", "I024 Switch", "I024"},
1123     {"O075", "I025 Switch", "I025"},
1124     {"O076", "I026 Switch", "I026"},
1125     {"O077", "I027 Switch", "I027"},
1126     {"O078", "I028 Switch", "I028"},
1127     {"O079", "I029 Switch", "I029"},
1128     {"O080", "I030 Switch", "I030"},
1129     {"O081", "I031 Switch", "I031"},
1130     {"O082", "I032 Switch", "I032"},
1131     {"O083", "I033 Switch", "I033"},
1132     {"O084", "I034 Switch", "I034"},
1133     {"O085", "I035 Switch", "I035"},
1134     {"O086", "I036 Switch", "I036"},
1135     {"O087", "I037 Switch", "I037"},
1136     {"O088", "I038 Switch", "I038"},
1137     {"O089", "I039 Switch", "I039"},
1138     {"O090", "I040 Switch", "I040"},
1139     {"O091", "I041 Switch", "I041"},
1140     {"O092", "I042 Switch", "I042"},
1141     {"O093", "I043 Switch", "I043"},
1142     {"O094", "I044 Switch", "I044"},
1143     {"O095", "I045 Switch", "I045"},
1144
1145     {"O072", "I046 Switch", "I046"},
1146     {"O073", "I047 Switch", "I047"},
1147     {"O074", "I048 Switch", "I048"},
1148     {"O075", "I049 Switch", "I049"},
1149     {"O076", "I050 Switch", "I050"},
1150     {"O077", "I051 Switch", "I051"},
1151     {"O078", "I052 Switch", "I052"},
1152     {"O079", "I053 Switch", "I053"},
1153     {"O080", "I054 Switch", "I054"},
1154     {"O081", "I055 Switch", "I055"},
1155     {"O082", "I056 Switch", "I056"},
1156     {"O083", "I057 Switch", "I057"},
1157     {"O084", "I058 Switch", "I058"},
1158     {"O085", "I059 Switch", "I059"},
1159     {"O086", "I060 Switch", "I060"},
1160     {"O087", "I061 Switch", "I061"},
1161     {"O088", "I062 Switch", "I062"},
1162     {"O089", "I063 Switch", "I063"},
1163     {"O090", "I064 Switch", "I064"},
1164     {"O091", "I065 Switch", "I065"},
1165     {"O092", "I066 Switch", "I066"},
1166     {"O093", "I067 Switch", "I067"},
1167     {"O094", "I068 Switch", "I068"},
1168     {"O095", "I069 Switch", "I069"},
1169
1170     {"O072", "I070 Switch", "I070"},
1171     {"O073", "I071 Switch", "I071"},
1172
1173     {"HDMI_CH0_MUX", "CH0", "DL10"},
1174     {"HDMI_CH0_MUX", "CH1", "DL10"},
1175     {"HDMI_CH0_MUX", "CH2", "DL10"},
1176     {"HDMI_CH0_MUX", "CH3", "DL10"},
1177     {"HDMI_CH0_MUX", "CH4", "DL10"},
1178     {"HDMI_CH0_MUX", "CH5", "DL10"},
1179     {"HDMI_CH0_MUX", "CH6", "DL10"},
1180     {"HDMI_CH0_MUX", "CH7", "DL10"},
1181
1182     {"HDMI_CH1_MUX", "CH0", "DL10"},
1183     {"HDMI_CH1_MUX", "CH1", "DL10"},
1184     {"HDMI_CH1_MUX", "CH2", "DL10"},
1185     {"HDMI_CH1_MUX", "CH3", "DL10"},
1186     {"HDMI_CH1_MUX", "CH4", "DL10"},
1187     {"HDMI_CH1_MUX", "CH5", "DL10"},
1188     {"HDMI_CH1_MUX", "CH6", "DL10"},
1189     {"HDMI_CH1_MUX", "CH7", "DL10"},
1190
1191     {"HDMI_CH2_MUX", "CH0", "DL10"},
1192     {"HDMI_CH2_MUX", "CH1", "DL10"},
1193     {"HDMI_CH2_MUX", "CH2", "DL10"},
1194     {"HDMI_CH2_MUX", "CH3", "DL10"},
1195     {"HDMI_CH2_MUX", "CH4", "DL10"},
1196     {"HDMI_CH2_MUX", "CH5", "DL10"},
1197     {"HDMI_CH2_MUX", "CH6", "DL10"},
1198     {"HDMI_CH2_MUX", "CH7", "DL10"},
1199
1200     {"HDMI_CH3_MUX", "CH0", "DL10"},
1201     {"HDMI_CH3_MUX", "CH1", "DL10"},
1202     {"HDMI_CH3_MUX", "CH2", "DL10"},
1203     {"HDMI_CH3_MUX", "CH3", "DL10"},
1204     {"HDMI_CH3_MUX", "CH4", "DL10"},
1205     {"HDMI_CH3_MUX", "CH5", "DL10"},
1206     {"HDMI_CH3_MUX", "CH6", "DL10"},
1207     {"HDMI_CH3_MUX", "CH7", "DL10"},
1208
1209     {"HDMI_CH4_MUX", "CH0", "DL10"},
1210     {"HDMI_CH4_MUX", "CH1", "DL10"},
1211     {"HDMI_CH4_MUX", "CH2", "DL10"},
1212     {"HDMI_CH4_MUX", "CH3", "DL10"},
1213     {"HDMI_CH4_MUX", "CH4", "DL10"},
1214     {"HDMI_CH4_MUX", "CH5", "DL10"},
1215     {"HDMI_CH4_MUX", "CH6", "DL10"},
1216     {"HDMI_CH4_MUX", "CH7", "DL10"},
1217
1218     {"HDMI_CH5_MUX", "CH0", "DL10"},
1219     {"HDMI_CH5_MUX", "CH1", "DL10"},
1220     {"HDMI_CH5_MUX", "CH2", "DL10"},
1221     {"HDMI_CH5_MUX", "CH3", "DL10"},
1222     {"HDMI_CH5_MUX", "CH4", "DL10"},
1223     {"HDMI_CH5_MUX", "CH5", "DL10"},
1224     {"HDMI_CH5_MUX", "CH6", "DL10"},
1225     {"HDMI_CH5_MUX", "CH7", "DL10"},
1226
1227     {"HDMI_CH6_MUX", "CH0", "DL10"},
1228     {"HDMI_CH6_MUX", "CH1", "DL10"},
1229     {"HDMI_CH6_MUX", "CH2", "DL10"},
1230     {"HDMI_CH6_MUX", "CH3", "DL10"},
1231     {"HDMI_CH6_MUX", "CH4", "DL10"},
1232     {"HDMI_CH6_MUX", "CH5", "DL10"},
1233     {"HDMI_CH6_MUX", "CH6", "DL10"},
1234     {"HDMI_CH6_MUX", "CH7", "DL10"},
1235
1236     {"HDMI_CH7_MUX", "CH0", "DL10"},
1237     {"HDMI_CH7_MUX", "CH1", "DL10"},
1238     {"HDMI_CH7_MUX", "CH2", "DL10"},
1239     {"HDMI_CH7_MUX", "CH3", "DL10"},
1240     {"HDMI_CH7_MUX", "CH4", "DL10"},
1241     {"HDMI_CH7_MUX", "CH5", "DL10"},
1242     {"HDMI_CH7_MUX", "CH6", "DL10"},
1243     {"HDMI_CH7_MUX", "CH7", "DL10"},
1244
1245     {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
1246     {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
1247     {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
1248     {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
1249     {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
1250     {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
1251     {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
1252     {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
1253
1254     {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
1255     {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
1256     {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
1257     {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
1258     {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
1259     {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
1260     {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
1261     {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
1262
1263     {"ETDM3 Playback", NULL, "HDMI_OUT_MUX"},
1264     {"DPTX Playback", NULL, "DPTX_OUT_MUX"},
1265
1266     {"ETDM_OUTPUT", NULL, "DPTX Playback"},
1267     {"ETDM_OUTPUT", NULL, "ETDM1 Playback"},
1268     {"ETDM_OUTPUT", NULL, "ETDM2 Playback"},
1269     {"ETDM_OUTPUT", NULL, "ETDM3 Playback"},
1270     {"ETDM1 Capture", NULL, "ETDM_INPUT"},
1271     {"ETDM2 Capture", NULL, "ETDM_INPUT"},
1272 };
1273
1274 static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id)
1275 {
1276     int ret = 0;
1277     struct etdm_con_reg etdm_reg;
1278     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1279     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1280     unsigned long flags;
1281
1282     spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
1283     etdm_data->en_ref_cnt++;
1284     if (etdm_data->en_ref_cnt == 1) {
1285         ret = get_etdm_reg(dai_id, &etdm_reg);
1286         if (ret < 0)
1287             goto out;
1288
1289         regmap_update_bits(afe->regmap, etdm_reg.con0,
1290                    ETDM_CON0_EN, ETDM_CON0_EN);
1291     }
1292 out:
1293     spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
1294     return ret;
1295 }
1296
1297 static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id)
1298 {
1299     int ret = 0;
1300     struct etdm_con_reg etdm_reg;
1301     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1302     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1303     unsigned long flags;
1304
1305     spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
1306     if (etdm_data->en_ref_cnt > 0) {
1307         etdm_data->en_ref_cnt--;
1308         if (etdm_data->en_ref_cnt == 0) {
1309             ret = get_etdm_reg(dai_id, &etdm_reg);
1310             if (ret < 0)
1311                 goto out;
1312
1313             regmap_update_bits(afe->regmap, etdm_reg.con0,
1314                        ETDM_CON0_EN, 0);
1315         }
1316     }
1317 out:
1318     spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
1319     return ret;
1320 }
1321
1322 static int etdm_cowork_slv_sel(int id, int slave_mode)
1323 {
1324     if (slave_mode) {
1325         switch (id) {
1326         case MT8195_AFE_IO_ETDM1_IN:
1327             return COWORK_ETDM_IN1_S;
1328         case MT8195_AFE_IO_ETDM2_IN:
1329             return COWORK_ETDM_IN2_S;
1330         case MT8195_AFE_IO_ETDM1_OUT:
1331             return COWORK_ETDM_OUT1_S;
1332         case MT8195_AFE_IO_ETDM2_OUT:
1333             return COWORK_ETDM_OUT2_S;
1334         case MT8195_AFE_IO_ETDM3_OUT:
1335             return COWORK_ETDM_OUT3_S;
1336         default:
1337             return -EINVAL;
1338         }
1339     } else {
1340         switch (id) {
1341         case MT8195_AFE_IO_ETDM1_IN:
1342             return COWORK_ETDM_IN1_M;
1343         case MT8195_AFE_IO_ETDM2_IN:
1344             return COWORK_ETDM_IN2_M;
1345         case MT8195_AFE_IO_ETDM1_OUT:
1346             return COWORK_ETDM_OUT1_M;
1347         case MT8195_AFE_IO_ETDM2_OUT:
1348             return COWORK_ETDM_OUT2_M;
1349         case MT8195_AFE_IO_ETDM3_OUT:
1350             return COWORK_ETDM_OUT3_M;
1351         default:
1352             return -EINVAL;
1353         }
1354     }
1355 }
1356
1357 static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)
1358 {
1359     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1360     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1361     unsigned int reg = 0;
1362     unsigned int mask;
1363     unsigned int val;
1364     int cowork_source_sel;
1365
1366     if (etdm_data->cowork_source_id == COWORK_ETDM_NONE)
1367         return 0;
1368
1369     cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id,
1370                         etdm_data->slave_mode);
1371     if (cowork_source_sel < 0)
1372         return cowork_source_sel;
1373
1374     switch (dai_id) {
1375     case MT8195_AFE_IO_ETDM1_IN:
1376         reg = ETDM_COWORK_CON1;
1377         mask = ETDM_IN1_SLAVE_SEL_MASK;
1378         val = ETDM_IN1_SLAVE_SEL(cowork_source_sel);
1379         break;
1380     case MT8195_AFE_IO_ETDM2_IN:
1381         reg = ETDM_COWORK_CON2;
1382         mask = ETDM_IN2_SLAVE_SEL_MASK;
1383         val = ETDM_IN2_SLAVE_SEL(cowork_source_sel);
1384         break;
1385     case MT8195_AFE_IO_ETDM1_OUT:
1386         reg = ETDM_COWORK_CON0;
1387         mask = ETDM_OUT1_SLAVE_SEL_MASK;
1388         val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel);
1389         break;
1390     case MT8195_AFE_IO_ETDM2_OUT:
1391         reg = ETDM_COWORK_CON2;
1392         mask = ETDM_OUT2_SLAVE_SEL_MASK;
1393         val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel);
1394         break;
1395     case MT8195_AFE_IO_ETDM3_OUT:
1396         reg = ETDM_COWORK_CON2;
1397         mask = ETDM_OUT3_SLAVE_SEL_MASK;
1398         val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel);
1399         break;
1400     default:
1401         return 0;
1402     }
1403
1404     regmap_update_bits(afe->regmap, reg, mask, val);
1405
1406     return 0;
1407 }
1408
1409 static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id)
1410 {
1411     int cg_id = -1;
1412
1413     switch (dai_id) {
1414     case MT8195_AFE_IO_DPTX:
1415         cg_id = MT8195_CLK_AUD_HDMI_OUT;
1416         break;
1417     case MT8195_AFE_IO_ETDM1_IN:
1418         cg_id = MT8195_CLK_AUD_TDM_IN;
1419         break;
1420     case MT8195_AFE_IO_ETDM2_IN:
1421         cg_id = MT8195_CLK_AUD_I2SIN;
1422         break;
1423     case MT8195_AFE_IO_ETDM1_OUT:
1424         cg_id = MT8195_CLK_AUD_TDM_OUT;
1425         break;
1426     case MT8195_AFE_IO_ETDM2_OUT:
1427         cg_id = MT8195_CLK_AUD_I2S_OUT;
1428         break;
1429     case MT8195_AFE_IO_ETDM3_OUT:
1430         cg_id = MT8195_CLK_AUD_HDMI_OUT;
1431         break;
1432     default:
1433         break;
1434     }
1435
1436     return cg_id;
1437 }
1438
1439 static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id)
1440 {
1441     int clk_id = -1;
1442
1443     switch (dai_id) {
1444     case MT8195_AFE_IO_DPTX:
1445         clk_id = MT8195_CLK_TOP_DPTX_M_SEL;
1446         break;
1447     case MT8195_AFE_IO_ETDM1_IN:
1448         clk_id = MT8195_CLK_TOP_I2SI1_M_SEL;
1449         break;
1450     case MT8195_AFE_IO_ETDM2_IN:
1451         clk_id = MT8195_CLK_TOP_I2SI2_M_SEL;
1452         break;
1453     case MT8195_AFE_IO_ETDM1_OUT:
1454         clk_id = MT8195_CLK_TOP_I2SO1_M_SEL;
1455         break;
1456     case MT8195_AFE_IO_ETDM2_OUT:
1457         clk_id = MT8195_CLK_TOP_I2SO2_M_SEL;
1458         break;
1459     case MT8195_AFE_IO_ETDM3_OUT:
1460     default:
1461         break;
1462     }
1463
1464     return clk_id;
1465 }
1466
1467 static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id)
1468 {
1469     int clk_id = -1;
1470
1471     switch (dai_id) {
1472     case MT8195_AFE_IO_DPTX:
1473         clk_id = MT8195_CLK_TOP_APLL12_DIV9;
1474         break;
1475     case MT8195_AFE_IO_ETDM1_IN:
1476         clk_id = MT8195_CLK_TOP_APLL12_DIV0;
1477         break;
1478     case MT8195_AFE_IO_ETDM2_IN:
1479         clk_id = MT8195_CLK_TOP_APLL12_DIV1;
1480         break;
1481     case MT8195_AFE_IO_ETDM1_OUT:
1482         clk_id = MT8195_CLK_TOP_APLL12_DIV2;
1483         break;
1484     case MT8195_AFE_IO_ETDM2_OUT:
1485         clk_id = MT8195_CLK_TOP_APLL12_DIV3;
1486         break;
1487     case MT8195_AFE_IO_ETDM3_OUT:
1488     default:
1489         break;
1490     }
1491
1492     return clk_id;
1493 }
1494
1495 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id)
1496 {
1497     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1498     int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
1499
1500     if (clkdiv_id < 0)
1501         return -EINVAL;
1502
1503     mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]);
1504
1505     return 0;
1506 }
1507
1508 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id)
1509 {
1510     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1511     int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
1512
1513     if (clkdiv_id < 0)
1514         return -EINVAL;
1515
1516     mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]);
1517
1518     return 0;
1519 }
1520
1521 /* dai ops */
1522 static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
1523                 struct snd_soc_dai *dai)
1524 {
1525     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1526     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1527     struct mtk_dai_etdm_priv *mst_etdm_data;
1528     int cg_id;
1529     int mst_dai_id;
1530     int slv_dai_id;
1531     int i;
1532
1533     if (is_cowork_mode(dai)) {
1534         mst_dai_id = get_etdm_cowork_master_id(dai);
1535         mtk_dai_etdm_enable_mclk(afe, mst_dai_id);
1536
1537         cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
1538         if (cg_id >= 0)
1539             mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
1540
1541         mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
1542
1543         for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
1544             slv_dai_id = mst_etdm_data->cowork_slv_id[i];
1545             cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
1546             if (cg_id >= 0)
1547                 mt8195_afe_enable_clk(afe,
1548                               afe_priv->clk[cg_id]);
1549         }
1550     } else {
1551         mtk_dai_etdm_enable_mclk(afe, dai->id);
1552
1553         cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
1554         if (cg_id >= 0)
1555             mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
1556     }
1557
1558     return 0;
1559 }
1560
1561 static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
1562                   struct snd_soc_dai *dai)
1563 {
1564     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1565     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1566     struct mtk_dai_etdm_priv *mst_etdm_data;
1567     int cg_id;
1568     int mst_dai_id;
1569     int slv_dai_id;
1570     int i;
1571
1572     if (is_cowork_mode(dai)) {
1573         mst_dai_id = get_etdm_cowork_master_id(dai);
1574         cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
1575         if (cg_id >= 0)
1576             mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
1577
1578         mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
1579         for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
1580             slv_dai_id = mst_etdm_data->cowork_slv_id[i];
1581             cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
1582             if (cg_id >= 0)
1583                 mt8195_afe_disable_clk(afe,
1584                                afe_priv->clk[cg_id]);
1585         }
1586         mtk_dai_etdm_disable_mclk(afe, mst_dai_id);
1587     } else {
1588         cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
1589         if (cg_id >= 0)
1590             mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
1591
1592         mtk_dai_etdm_disable_mclk(afe, dai->id);
1593     }
1594 }
1595
1596 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe,
1597                   int dai_id, unsigned int rate)
1598 {
1599     unsigned int mode = 0;
1600     unsigned int reg = 0;
1601     unsigned int val = 0;
1602     unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO);
1603
1604     if (rate != 0)
1605         mode = mt8195_afe_fs_timing(rate);
1606
1607     switch (dai_id) {
1608     case MT8195_AFE_IO_ETDM1_IN:
1609         reg = ETDM_IN1_AFIFO_CON;
1610         if (rate == 0)
1611             mode = MT8195_ETDM_IN1_1X_EN;
1612         break;
1613     case MT8195_AFE_IO_ETDM2_IN:
1614         reg = ETDM_IN2_AFIFO_CON;
1615         if (rate == 0)
1616             mode = MT8195_ETDM_IN2_1X_EN;
1617         break;
1618     default:
1619         return -EINVAL;
1620     }
1621
1622     val = (mode | ETDM_IN_USE_AFIFO);
1623
1624     regmap_update_bits(afe->regmap, reg, mask, val);
1625     return 0;
1626 }
1627
1628 static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe,
1629                      unsigned int rate,
1630                      unsigned int channels,
1631                      int dai_id)
1632 {
1633     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1634     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1635     struct etdm_con_reg etdm_reg;
1636     bool slave_mode = etdm_data->slave_mode;
1637     unsigned int data_mode = etdm_data->data_mode;
1638     unsigned int lrck_width = etdm_data->lrck_width;
1639     unsigned int val = 0;
1640     unsigned int mask = 0;
1641     int i;
1642     int ret;
1643
1644     dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
1645         __func__, rate, channels, dai_id);
1646
1647     ret = get_etdm_reg(dai_id, &etdm_reg);
1648     if (ret < 0)
1649         return ret;
1650
1651     if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
1652         slave_mode = true;
1653
1654     /* afifo */
1655     if (slave_mode)
1656         mtk_dai_etdm_fifo_mode(afe, dai_id, 0);
1657     else
1658         mtk_dai_etdm_fifo_mode(afe, dai_id, rate);
1659
1660     /* con1 */
1661     if (lrck_width > 0) {
1662         mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE |
1663             ETDM_IN_CON1_LRCK_WIDTH_MASK);
1664         val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width);
1665     }
1666     regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
1667
1668     mask = 0;
1669     val = 0;
1670
1671     /* con2 */
1672     if (!slave_mode) {
1673         mask |= ETDM_IN_CON2_UPDATE_GAP_MASK;
1674         if (rate == 352800 || rate == 384000)
1675             val |= ETDM_IN_CON2_UPDATE_GAP(4);
1676         else
1677             val |= ETDM_IN_CON2_UPDATE_GAP(3);
1678     }
1679     mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE |
1680         ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK);
1681     if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) {
1682         val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE |
1683                ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels);
1684     }
1685     regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val);
1686
1687     mask = 0;
1688     val = 0;
1689
1690     /* con3 */
1691     mask |= ETDM_IN_CON3_DISABLE_OUT_MASK;
1692     for (i = 0; i < channels; i += 2) {
1693         if (etdm_data->in_disable_ch[i] &&
1694             etdm_data->in_disable_ch[i + 1])
1695             val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1);
1696     }
1697     if (!slave_mode) {
1698         mask |= ETDM_IN_CON3_FS_MASK;
1699         val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate));
1700     }
1701     regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val);
1702
1703     mask = 0;
1704     val = 0;
1705
1706     /* con4 */
1707     mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV |
1708         ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV);
1709     if (slave_mode) {
1710         if (etdm_data->lrck_inv)
1711             val |= ETDM_IN_CON4_SLAVE_LRCK_INV;
1712         if (etdm_data->bck_inv)
1713             val |= ETDM_IN_CON4_SLAVE_BCK_INV;
1714     } else {
1715         if (etdm_data->lrck_inv)
1716             val |= ETDM_IN_CON4_MASTER_LRCK_INV;
1717         if (etdm_data->bck_inv)
1718             val |= ETDM_IN_CON4_MASTER_BCK_INV;
1719     }
1720     regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
1721
1722     mask = 0;
1723     val = 0;
1724
1725     /* con5 */
1726     mask |= ETDM_IN_CON5_LR_SWAP_MASK;
1727     mask |= ETDM_IN_CON5_ENABLE_ODD_MASK;
1728     for (i = 0; i < channels; i += 2) {
1729         if (etdm_data->in_disable_ch[i] &&
1730             !etdm_data->in_disable_ch[i + 1]) {
1731             if (i == (channels - 2))
1732                 val |= ETDM_IN_CON5_LR_SWAP(15);
1733             else
1734                 val |= ETDM_IN_CON5_LR_SWAP(i >> 1);
1735             val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
1736         } else if (!etdm_data->in_disable_ch[i] &&
1737                etdm_data->in_disable_ch[i + 1]) {
1738             val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
1739         }
1740     }
1741     regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
1742     return 0;
1743 }
1744
1745 static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe,
1746                       unsigned int rate,
1747                       unsigned int channels,
1748                       int dai_id)
1749 {
1750     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1751     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1752     struct etdm_con_reg etdm_reg;
1753     bool slave_mode = etdm_data->slave_mode;
1754     unsigned int lrck_width = etdm_data->lrck_width;
1755     unsigned int val = 0;
1756     unsigned int mask = 0;
1757     int ret;
1758     int fs = 0;
1759
1760     dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
1761         __func__, rate, channels, dai_id);
1762
1763     ret = get_etdm_reg(dai_id, &etdm_reg);
1764     if (ret < 0)
1765         return ret;
1766
1767     if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
1768         slave_mode = true;
1769
1770     /* con0 */
1771     mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK;
1772     val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS);
1773     regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
1774
1775     mask = 0;
1776     val = 0;
1777
1778     /* con1 */
1779     if (lrck_width > 0) {
1780         mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE |
1781             ETDM_OUT_CON1_LRCK_WIDTH_MASK);
1782         val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width);
1783     }
1784     regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
1785
1786     mask = 0;
1787     val = 0;
1788
1789     if (slave_mode) {
1790         /* con2 */
1791         mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV |
1792             ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
1793         val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV |
1794             ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
1795         regmap_update_bits(afe->regmap, etdm_reg.con2,
1796                    mask, val);
1797         mask = 0;
1798         val = 0;
1799     } else {
1800         /* con4 */
1801         mask |= ETDM_OUT_CON4_FS_MASK;
1802         val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate));
1803     }
1804
1805     mask |= ETDM_OUT_CON4_RELATCH_EN_MASK;
1806     if (dai_id == MT8195_AFE_IO_ETDM1_OUT)
1807         fs = MT8195_ETDM_OUT1_1X_EN;
1808     else if (dai_id == MT8195_AFE_IO_ETDM2_OUT)
1809         fs = MT8195_ETDM_OUT2_1X_EN;
1810
1811     val |= ETDM_OUT_CON4_RELATCH_EN(fs);
1812
1813     regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
1814
1815     mask = 0;
1816     val = 0;
1817
1818     /* con5 */
1819     mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV |
1820         ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV);
1821     if (slave_mode) {
1822         if (etdm_data->lrck_inv)
1823             val |= ETDM_OUT_CON5_SLAVE_LRCK_INV;
1824         if (etdm_data->bck_inv)
1825             val |= ETDM_OUT_CON5_SLAVE_BCK_INV;
1826     } else {
1827         if (etdm_data->lrck_inv)
1828             val |= ETDM_OUT_CON5_MASTER_LRCK_INV;
1829         if (etdm_data->bck_inv)
1830             val |= ETDM_OUT_CON5_MASTER_BCK_INV;
1831     }
1832     regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
1833
1834     return 0;
1835 }
1836
1837 static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id)
1838 {
1839     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1840     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1841     int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);
1842     int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
1843     int apll;
1844     int apll_clk_id;
1845     struct etdm_con_reg etdm_reg;
1846     unsigned int val = 0;
1847     unsigned int mask = 0;
1848     int ret = 0;
1849
1850     if (clk_id < 0 || clkdiv_id < 0)
1851         return 0;
1852
1853     ret = get_etdm_reg(dai_id, &etdm_reg);
1854     if (ret < 0)
1855         return ret;
1856
1857     mask |= ETDM_CON1_MCLK_OUTPUT;
1858     if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
1859         val |= ETDM_CON1_MCLK_OUTPUT;
1860     regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
1861
1862     if (etdm_data->mclk_freq) {
1863         apll = etdm_data->mclk_apll;
1864         apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
1865         if (apll_clk_id < 0)
1866             return apll_clk_id;
1867
1868         /* select apll */
1869         ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id],
1870                         afe_priv->clk[apll_clk_id]);
1871         if (ret)
1872             return ret;
1873
1874         /* set rate */
1875         ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id],
1876                           etdm_data->mclk_freq);
1877     } else {
1878         if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
1879             dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__);
1880     }
1881     return ret;
1882 }
1883
1884 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe,
1885                   unsigned int rate,
1886                   unsigned int channels,
1887                   unsigned int bit_width,
1888                   int dai_id)
1889 {
1890     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1891     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
1892     struct etdm_con_reg etdm_reg;
1893     bool slave_mode = etdm_data->slave_mode;
1894     unsigned int etdm_channels;
1895     unsigned int val = 0;
1896     unsigned int mask = 0;
1897     unsigned int bck;
1898     unsigned int wlen = get_etdm_wlen(bit_width);
1899     int ret;
1900
1901     ret = get_etdm_reg(dai_id, &etdm_reg);
1902     if (ret < 0)
1903         return ret;
1904
1905     if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
1906         slave_mode = true;
1907
1908     dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n",
1909         __func__, etdm_data->format, etdm_data->data_mode,
1910         etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv,
1911         etdm_data->clock_mode, etdm_data->slave_mode);
1912     dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n",
1913         __func__, rate, channels, bit_width, dai_id);
1914
1915     etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ?
1916             get_etdm_ch_fixup(channels) : 2;
1917
1918     bck = rate * etdm_channels * wlen;
1919     if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) {
1920         dev_info(afe->dev, "%s bck rate %u not support\n",
1921              __func__, bck);
1922         return -EINVAL;
1923     }
1924
1925     /* con0 */
1926     mask |= ETDM_CON0_BIT_LEN_MASK;
1927     val |= ETDM_CON0_BIT_LEN(bit_width);
1928     mask |= ETDM_CON0_WORD_LEN_MASK;
1929     val |= ETDM_CON0_WORD_LEN(wlen);
1930     mask |= ETDM_CON0_FORMAT_MASK;
1931     val |= ETDM_CON0_FORMAT(etdm_data->format);
1932     mask |= ETDM_CON0_CH_NUM_MASK;
1933     val |= ETDM_CON0_CH_NUM(etdm_channels);
1934
1935     mask |= ETDM_CON0_SLAVE_MODE;
1936     if (slave_mode) {
1937         if (dai_id == MT8195_AFE_IO_ETDM1_OUT &&
1938             etdm_data->cowork_source_id == COWORK_ETDM_NONE) {
1939             dev_info(afe->dev, "%s id %d only support master mode\n",
1940                  __func__, dai_id);
1941             return -EINVAL;
1942         }
1943         val |= ETDM_CON0_SLAVE_MODE;
1944     }
1945     regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
1946
1947     if (get_etdm_dir(dai_id) == ETDM_IN)
1948         mtk_dai_etdm_in_configure(afe, rate, channels, dai_id);
1949     else
1950         mtk_dai_etdm_out_configure(afe, rate, channels, dai_id);
1951
1952     return 0;
1953 }
1954
1955 static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
1956                   struct snd_pcm_hw_params *params,
1957                   struct snd_soc_dai *dai)
1958 {
1959     int ret = 0;
1960     unsigned int rate = params_rate(params);
1961     unsigned int bit_width = params_width(params);
1962     unsigned int channels = params_channels(params);
1963     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1964     struct mt8195_afe_private *afe_priv = afe->platform_priv;
1965     struct mtk_dai_etdm_priv *mst_etdm_data;
1966     int mst_dai_id;
1967     int slv_dai_id;
1968     int i;
1969
1970     dev_dbg(afe->dev, "%s '%s' period %u-%u\n",
1971         __func__, snd_pcm_stream_str(substream),
1972         params_period_size(params), params_periods(params));
1973
1974     if (is_cowork_mode(dai)) {
1975         mst_dai_id = get_etdm_cowork_master_id(dai);
1976
1977         ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id);
1978         if (ret)
1979             return ret;
1980
1981         ret = mtk_dai_etdm_configure(afe, rate, channels,
1982                          bit_width, mst_dai_id);
1983         if (ret)
1984             return ret;
1985
1986         mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
1987         for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
1988             slv_dai_id = mst_etdm_data->cowork_slv_id[i];
1989             ret = mtk_dai_etdm_configure(afe, rate, channels,
1990                              bit_width, slv_dai_id);
1991             if (ret)
1992                 return ret;
1993
1994             ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id);
1995             if (ret)
1996                 return ret;
1997         }
1998     } else {
1999         ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
2000         if (ret)
2001             return ret;
2002
2003         ret = mtk_dai_etdm_configure(afe, rate, channels,
2004                          bit_width, dai->id);
2005     }
2006
2007     return ret;
2008 }
2009
2010 static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
2011                 struct snd_soc_dai *dai)
2012 {
2013     int ret = 0;
2014     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2015     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2016     struct mtk_dai_etdm_priv *mst_etdm_data;
2017     int mst_dai_id;
2018     int slv_dai_id;
2019     int i;
2020
2021     dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
2022     switch (cmd) {
2023     case SNDRV_PCM_TRIGGER_START:
2024     case SNDRV_PCM_TRIGGER_RESUME:
2025         if (is_cowork_mode(dai)) {
2026             mst_dai_id = get_etdm_cowork_master_id(dai);
2027             mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
2028
2029             //open master first
2030             ret |= mt8195_afe_enable_etdm(afe, mst_dai_id);
2031             for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
2032                 slv_dai_id = mst_etdm_data->cowork_slv_id[i];
2033                 ret |= mt8195_afe_enable_etdm(afe, slv_dai_id);
2034             }
2035         } else {
2036             ret = mt8195_afe_enable_etdm(afe, dai->id);
2037         }
2038         break;
2039     case SNDRV_PCM_TRIGGER_STOP:
2040     case SNDRV_PCM_TRIGGER_SUSPEND:
2041         if (is_cowork_mode(dai)) {
2042             mst_dai_id = get_etdm_cowork_master_id(dai);
2043             mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
2044
2045             for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
2046                 slv_dai_id = mst_etdm_data->cowork_slv_id[i];
2047                 ret |= mt8195_afe_disable_etdm(afe, slv_dai_id);
2048             }
2049             // close master at last
2050             ret |= mt8195_afe_disable_etdm(afe, mst_dai_id);
2051         } else {
2052             ret = mt8195_afe_disable_etdm(afe, dai->id);
2053         }
2054         break;
2055     default:
2056         break;
2057     }
2058     return ret;
2059 }
2060
2061 static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id)
2062 {
2063     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2064     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
2065     int apll;
2066     int apll_rate;
2067
2068     if (freq == 0) {
2069         etdm_data->mclk_freq = freq;
2070         return 0;
2071     }
2072
2073     apll = mt8195_afe_get_default_mclk_source_by_rate(freq);
2074     apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll);
2075
2076     if (freq > apll_rate) {
2077         dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate);
2078         return -EINVAL;
2079     }
2080
2081     if (apll_rate % freq != 0) {
2082         dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll);
2083         return -EINVAL;
2084     }
2085
2086     etdm_data->mclk_apll = apll;
2087     etdm_data->mclk_freq = freq;
2088
2089     return 0;
2090 }
2091
2092 static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai,
2093                    int clk_id, unsigned int freq, int dir)
2094 {
2095     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2096     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2097     struct mtk_dai_etdm_priv *etdm_data;
2098     int dai_id;
2099
2100     dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
2101         __func__, dai->id, freq, dir);
2102     if (is_cowork_mode(dai))
2103         dai_id = get_etdm_cowork_master_id(dai);
2104     else
2105         dai_id = dai->id;
2106
2107     etdm_data = afe_priv->dai_priv[dai_id];
2108     etdm_data->mclk_dir = dir;
2109     return mtk_dai_etdm_cal_mclk(afe, freq, dai_id);
2110 }
2111
2112 static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai,
2113                      unsigned int tx_mask, unsigned int rx_mask,
2114                      int slots, int slot_width)
2115 {
2116     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2117     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2118     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
2119
2120     dev_dbg(dai->dev, "%s id %d slot_width %d\n",
2121         __func__, dai->id, slot_width);
2122
2123     etdm_data->slots = slots;
2124     etdm_data->lrck_width = slot_width;
2125     return 0;
2126 }
2127
2128 static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2129 {
2130     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2131     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2132     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
2133
2134     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2135     case SND_SOC_DAIFMT_I2S:
2136         etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
2137         break;
2138     case SND_SOC_DAIFMT_LEFT_J:
2139         etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ;
2140         break;
2141     case SND_SOC_DAIFMT_RIGHT_J:
2142         etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ;
2143         break;
2144     case SND_SOC_DAIFMT_DSP_A:
2145         etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
2146         break;
2147     case SND_SOC_DAIFMT_DSP_B:
2148         etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
2149         break;
2150     default:
2151         return -EINVAL;
2152     }
2153
2154     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2155     case SND_SOC_DAIFMT_NB_NF:
2156         etdm_data->bck_inv = false;
2157         etdm_data->lrck_inv = false;
2158         break;
2159     case SND_SOC_DAIFMT_NB_IF:
2160         etdm_data->bck_inv = false;
2161         etdm_data->lrck_inv = true;
2162         break;
2163     case SND_SOC_DAIFMT_IB_NF:
2164         etdm_data->bck_inv = true;
2165         etdm_data->lrck_inv = false;
2166         break;
2167     case SND_SOC_DAIFMT_IB_IF:
2168         etdm_data->bck_inv = true;
2169         etdm_data->lrck_inv = true;
2170         break;
2171     default:
2172         return -EINVAL;
2173     }
2174
2175     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
2176     case SND_SOC_DAIFMT_BC_FC:
2177         etdm_data->slave_mode = true;
2178         break;
2179     case SND_SOC_DAIFMT_BP_FP:
2180         etdm_data->slave_mode = false;
2181         break;
2182     default:
2183         return -EINVAL;
2184     }
2185
2186     return 0;
2187 }
2188
2189 static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream,
2190                        struct snd_soc_dai *dai)
2191 {
2192     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2193     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2194     int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
2195
2196     if (cg_id >= 0)
2197         mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
2198
2199     mtk_dai_etdm_enable_mclk(afe, dai->id);
2200
2201     return 0;
2202 }
2203
2204 static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream,
2205                      struct snd_soc_dai *dai)
2206 {
2207     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2208     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2209     int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
2210
2211     mtk_dai_etdm_disable_mclk(afe, dai->id);
2212
2213     if (cg_id >= 0)
2214         mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
2215 }
2216
2217 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel)
2218 {
2219     switch (channel) {
2220     case 1 ... 2:
2221         return AFE_DPTX_CON_CH_EN_2CH;
2222     case 3 ... 4:
2223         return AFE_DPTX_CON_CH_EN_4CH;
2224     case 5 ... 6:
2225         return AFE_DPTX_CON_CH_EN_6CH;
2226     case 7 ... 8:
2227         return AFE_DPTX_CON_CH_EN_8CH;
2228     default:
2229         return AFE_DPTX_CON_CH_EN_2CH;
2230     }
2231 }
2232
2233 static unsigned int mtk_dai_get_dptx_ch(unsigned int ch)
2234 {
2235     return (ch > 2) ?
2236         AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH;
2237 }
2238
2239 static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format)
2240 {
2241     return snd_pcm_format_physical_width(format) <= 16 ?
2242         AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT;
2243 }
2244
2245 static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream,
2246                      struct snd_pcm_hw_params *params,
2247                      struct snd_soc_dai *dai)
2248 {
2249     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2250     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2251     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
2252     unsigned int rate = params_rate(params);
2253     unsigned int channels = params_channels(params);
2254     snd_pcm_format_t format = params_format(params);
2255     int width = snd_pcm_format_physical_width(format);
2256     int ret = 0;
2257
2258     /* dptx configure */
2259     if (dai->id == MT8195_AFE_IO_DPTX) {
2260         regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2261                    AFE_DPTX_CON_CH_EN_MASK,
2262                    mtk_dai_get_dptx_ch_en(channels));
2263         regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2264                    AFE_DPTX_CON_CH_NUM_MASK,
2265                    mtk_dai_get_dptx_ch(channels));
2266         regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2267                    AFE_DPTX_CON_16BIT_MASK,
2268                    mtk_dai_get_dptx_wlen(format));
2269
2270         if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) {
2271             etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN;
2272             channels = 8;
2273         } else {
2274             channels = 2;
2275         }
2276     } else {
2277         etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN;
2278     }
2279
2280     ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
2281     if (ret)
2282         return ret;
2283
2284     ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id);
2285
2286     return ret;
2287 }
2288
2289 static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream,
2290                        int cmd,
2291                        struct snd_soc_dai *dai)
2292 {
2293     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2294     int ret = 0;
2295
2296     dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
2297
2298     switch (cmd) {
2299     case SNDRV_PCM_TRIGGER_START:
2300     case SNDRV_PCM_TRIGGER_RESUME:
2301         /* enable dptx interface */
2302         if (dai->id == MT8195_AFE_IO_DPTX)
2303             regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2304                        AFE_DPTX_CON_ON_MASK,
2305                        AFE_DPTX_CON_ON);
2306
2307         /* enable etdm_out3 */
2308         ret = mt8195_afe_enable_etdm(afe, dai->id);
2309         break;
2310     case SNDRV_PCM_TRIGGER_STOP:
2311     case SNDRV_PCM_TRIGGER_SUSPEND:
2312         /* disable etdm_out3 */
2313         ret = mt8195_afe_disable_etdm(afe, dai->id);
2314
2315         /* disable dptx interface */
2316         if (dai->id == MT8195_AFE_IO_DPTX)
2317             regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2318                        AFE_DPTX_CON_ON_MASK, 0);
2319         break;
2320     default:
2321         return -EINVAL;
2322     }
2323
2324     return ret;
2325 }
2326
2327 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai,
2328                       int clk_id,
2329                       unsigned int freq,
2330                       int dir)
2331 {
2332     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2333     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2334     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
2335
2336     dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
2337         __func__, dai->id, freq, dir);
2338
2339     etdm_data->mclk_dir = dir;
2340     return mtk_dai_etdm_cal_mclk(afe, freq, dai->id);
2341 }
2342
2343 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
2344     .startup = mtk_dai_etdm_startup,
2345     .shutdown = mtk_dai_etdm_shutdown,
2346     .hw_params = mtk_dai_etdm_hw_params,
2347     .trigger = mtk_dai_etdm_trigger,
2348     .set_sysclk = mtk_dai_etdm_set_sysclk,
2349     .set_fmt = mtk_dai_etdm_set_fmt,
2350     .set_tdm_slot = mtk_dai_etdm_set_tdm_slot,
2351 };
2352
2353 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = {
2354     .startup    = mtk_dai_hdmitx_dptx_startup,
2355     .shutdown   = mtk_dai_hdmitx_dptx_shutdown,
2356     .hw_params  = mtk_dai_hdmitx_dptx_hw_params,
2357     .trigger    = mtk_dai_hdmitx_dptx_trigger,
2358     .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk,
2359     .set_fmt    = mtk_dai_etdm_set_fmt,
2360 };
2361
2362 /* dai driver */
2363 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000)
2364
2365 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
2366               SNDRV_PCM_FMTBIT_S24_LE |\
2367               SNDRV_PCM_FMTBIT_S32_LE)
2368
2369 static int mtk_dai_etdm_probe(struct snd_soc_dai *dai)
2370 {
2371     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2372     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2373     struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
2374
2375     dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id);
2376
2377     if (etdm_data->mclk_freq) {
2378         dev_dbg(afe->dev, "MCLK always on, rate %d\n",
2379             etdm_data->mclk_freq);
2380         pm_runtime_get_sync(afe->dev);
2381         mtk_dai_etdm_mclk_configure(afe, dai->id);
2382         mtk_dai_etdm_enable_mclk(afe, dai->id);
2383         pm_runtime_put_sync(afe->dev);
2384     }
2385     return 0;
2386 }
2387
2388 static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
2389     {
2390         .name = "DPTX",
2391         .id = MT8195_AFE_IO_DPTX,
2392         .playback = {
2393             .stream_name = "DPTX Playback",
2394             .channels_min = 1,
2395             .channels_max = 8,
2396             .rates = MTK_ETDM_RATES,
2397             .formats = MTK_ETDM_FORMATS,
2398         },
2399         .ops = &mtk_dai_hdmitx_dptx_ops,
2400     },
2401     {
2402         .name = "ETDM1_IN",
2403         .id = MT8195_AFE_IO_ETDM1_IN,
2404         .capture = {
2405             .stream_name = "ETDM1 Capture",
2406             .channels_min = 1,
2407             .channels_max = 24,
2408             .rates = MTK_ETDM_RATES,
2409             .formats = MTK_ETDM_FORMATS,
2410         },
2411         .ops = &mtk_dai_etdm_ops,
2412         .probe = mtk_dai_etdm_probe,
2413     },
2414     {
2415         .name = "ETDM2_IN",
2416         .id = MT8195_AFE_IO_ETDM2_IN,
2417         .capture = {
2418             .stream_name = "ETDM2 Capture",
2419             .channels_min = 1,
2420             .channels_max = 16,
2421             .rates = MTK_ETDM_RATES,
2422             .formats = MTK_ETDM_FORMATS,
2423         },
2424         .ops = &mtk_dai_etdm_ops,
2425         .probe = mtk_dai_etdm_probe,
2426     },
2427     {
2428         .name = "ETDM1_OUT",
2429         .id = MT8195_AFE_IO_ETDM1_OUT,
2430         .playback = {
2431             .stream_name = "ETDM1 Playback",
2432             .channels_min = 1,
2433             .channels_max = 24,
2434             .rates = MTK_ETDM_RATES,
2435             .formats = MTK_ETDM_FORMATS,
2436         },
2437         .ops = &mtk_dai_etdm_ops,
2438         .probe = mtk_dai_etdm_probe,
2439     },
2440     {
2441         .name = "ETDM2_OUT",
2442         .id = MT8195_AFE_IO_ETDM2_OUT,
2443         .playback = {
2444             .stream_name = "ETDM2 Playback",
2445             .channels_min = 1,
2446             .channels_max = 24,
2447             .rates = MTK_ETDM_RATES,
2448             .formats = MTK_ETDM_FORMATS,
2449         },
2450         .ops = &mtk_dai_etdm_ops,
2451         .probe = mtk_dai_etdm_probe,
2452     },
2453     {
2454         .name = "ETDM3_OUT",
2455         .id = MT8195_AFE_IO_ETDM3_OUT,
2456         .playback = {
2457             .stream_name = "ETDM3 Playback",
2458             .channels_min = 1,
2459             .channels_max = 8,
2460             .rates = MTK_ETDM_RATES,
2461             .formats = MTK_ETDM_FORMATS,
2462         },
2463         .ops = &mtk_dai_hdmitx_dptx_ops,
2464         .probe = mtk_dai_etdm_probe,
2465     },
2466 };
2467
2468 static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe)
2469 {
2470     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2471     struct mtk_dai_etdm_priv *etdm_data;
2472     struct mtk_dai_etdm_priv *mst_data;
2473     int i;
2474     int mst_dai_id;
2475
2476     for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
2477         etdm_data = afe_priv->dai_priv[i];
2478         if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) {
2479             mst_dai_id = etdm_data->cowork_source_id;
2480             mst_data = afe_priv->dai_priv[mst_dai_id];
2481             if (mst_data->cowork_source_id != COWORK_ETDM_NONE)
2482                 dev_info(afe->dev, "%s [%d] wrong sync source\n"
2483                      , __func__, i);
2484             mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i;
2485             mst_data->cowork_slv_count++;
2486         }
2487     }
2488 }
2489
2490 static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe)
2491 {
2492     const struct device_node *of_node = afe->dev->of_node;
2493     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2494     struct mtk_dai_etdm_priv *etdm_data;
2495     int i, j;
2496     char prop[48];
2497     u8 disable_chn[MT8195_ETDM_MAX_CHANNELS];
2498     int max_chn = MT8195_ETDM_MAX_CHANNELS;
2499     u32 sel;
2500     int ret;
2501     int dai_id;
2502     unsigned int sync_id;
2503     struct {
2504         const char *name;
2505         const unsigned int sync_id;
2506     } of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = {
2507         {"etdm-in1", ETDM_SYNC_FROM_IN1},
2508         {"etdm-in2", ETDM_SYNC_FROM_IN2},
2509         {"etdm-out1", ETDM_SYNC_FROM_OUT1},
2510         {"etdm-out2", ETDM_SYNC_FROM_OUT2},
2511         {"etdm-out3", ETDM_SYNC_FROM_OUT3},
2512     };
2513
2514     for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) {
2515         dai_id = ETDM_TO_DAI_ID(i);
2516         etdm_data = afe_priv->dai_priv[dai_id];
2517
2518         ret = snprintf(prop, sizeof(prop),
2519                    "mediatek,%s-mclk-always-on-rate",
2520                    of_afe_etdms[i].name);
2521         if (ret < 0) {
2522             dev_info(afe->dev, "%s snprintf err=%d\n",
2523                  __func__, ret);
2524             return;
2525         }
2526         ret = of_property_read_u32(of_node, prop, &sel);
2527         if (ret == 0) {
2528             etdm_data->mclk_dir = SND_SOC_CLOCK_OUT;
2529             if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id))
2530                 dev_info(afe->dev, "%s unsupported mclk %uHz\n",
2531                      __func__, sel);
2532         }
2533
2534         ret = snprintf(prop, sizeof(prop),
2535                    "mediatek,%s-multi-pin-mode",
2536                    of_afe_etdms[i].name);
2537         if (ret < 0) {
2538             dev_info(afe->dev, "%s snprintf err=%d\n",
2539                  __func__, ret);
2540             return;
2541         }
2542         etdm_data->data_mode = of_property_read_bool(of_node, prop);
2543
2544         ret = snprintf(prop, sizeof(prop),
2545                    "mediatek,%s-cowork-source",
2546                    of_afe_etdms[i].name);
2547         if (ret < 0) {
2548             dev_info(afe->dev, "%s snprintf err=%d\n",
2549                  __func__, ret);
2550             return;
2551         }
2552         ret = of_property_read_u32(of_node, prop, &sel);
2553         if (ret == 0) {
2554             if (sel >= MT8195_AFE_IO_ETDM_NUM) {
2555                 dev_info(afe->dev, "%s invalid id=%d\n",
2556                      __func__, sel);
2557                 etdm_data->cowork_source_id = COWORK_ETDM_NONE;
2558             } else {
2559                 sync_id = of_afe_etdms[sel].sync_id;
2560                 etdm_data->cowork_source_id =
2561                     sync_to_dai_id(sync_id);
2562             }
2563         } else {
2564             etdm_data->cowork_source_id = COWORK_ETDM_NONE;
2565         }
2566     }
2567
2568     /* etdm in only */
2569     for (i = 0; i < 2; i++) {
2570         ret = snprintf(prop, sizeof(prop),
2571                    "mediatek,%s-chn-disabled",
2572                    of_afe_etdms[i].name);
2573         if (ret < 0) {
2574             dev_info(afe->dev, "%s snprintf err=%d\n",
2575                  __func__, ret);
2576             return;
2577         }
2578         ret = of_property_read_variable_u8_array(of_node, prop,
2579                              disable_chn,
2580                              1, max_chn);
2581         if (ret < 0)
2582             continue;
2583
2584         for (j = 0; j < ret; j++) {
2585             if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS)
2586                 dev_info(afe->dev, "%s [%d] invalid chn %u\n",
2587                      __func__, j, disable_chn[j]);
2588             else
2589                 etdm_data->in_disable_ch[disable_chn[j]] = true;
2590         }
2591     }
2592     mt8195_etdm_update_sync_info(afe);
2593 }
2594
2595 static int init_etdm_priv_data(struct mtk_base_afe *afe)
2596 {
2597     struct mt8195_afe_private *afe_priv = afe->platform_priv;
2598     struct mtk_dai_etdm_priv *etdm_priv;
2599     int i;
2600
2601     for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
2602         etdm_priv = devm_kzalloc(afe->dev,
2603                      sizeof(struct mtk_dai_etdm_priv),
2604                      GFP_KERNEL);
2605         if (!etdm_priv)
2606             return -ENOMEM;
2607
2608         afe_priv->dai_priv[i] = etdm_priv;
2609     }
2610
2611     afe_priv->dai_priv[MT8195_AFE_IO_DPTX] =
2612         afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT];
2613
2614     mt8195_dai_etdm_parse_of(afe);
2615     return 0;
2616 }
2617
2618 int mt8195_dai_etdm_register(struct mtk_base_afe *afe)
2619 {
2620     struct mtk_base_afe_dai *dai;
2621
2622     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2623     if (!dai)
2624         return -ENOMEM;
2625
2626     list_add(&dai->list, &afe->sub_dais);
2627
2628     dai->dai_drivers = mtk_dai_etdm_driver;
2629     dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
2630
2631     dai->dapm_widgets = mtk_dai_etdm_widgets;
2632     dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
2633     dai->dapm_routes = mtk_dai_etdm_routes;
2634     dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
2635     dai->controls = mtk_dai_etdm_controls;
2636     dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls);
2637
2638     return init_etdm_priv_data(afe);
2639 }