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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MediaTek ALSA SoC Audio DAI ADDA Control
0004  *
0005  * Copyright (c) 2021 MediaTek Inc.
0006  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
0007  *         Trevor Wu <trevor.wu@mediatek.com>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/regmap.h>
0012 #include "mt8195-afe-clk.h"
0013 #include "mt8195-afe-common.h"
0014 #include "mt8195-reg.h"
0015 
0016 #define ADDA_DL_GAIN_LOOPBACK 0x1800
0017 #define ADDA_HIRES_THRES 48000
0018 
0019 enum {
0020     SUPPLY_SEQ_CLOCK_SEL,
0021     SUPPLY_SEQ_CLOCK_ON,
0022     SUPPLY_SEQ_ADDA_DL_ON,
0023     SUPPLY_SEQ_ADDA_MTKAIF_CFG,
0024     SUPPLY_SEQ_ADDA_UL_ON,
0025     SUPPLY_SEQ_ADDA_AFE_ON,
0026 };
0027 
0028 enum {
0029     MTK_AFE_ADDA_DL_RATE_8K = 0,
0030     MTK_AFE_ADDA_DL_RATE_11K = 1,
0031     MTK_AFE_ADDA_DL_RATE_12K = 2,
0032     MTK_AFE_ADDA_DL_RATE_16K = 3,
0033     MTK_AFE_ADDA_DL_RATE_22K = 4,
0034     MTK_AFE_ADDA_DL_RATE_24K = 5,
0035     MTK_AFE_ADDA_DL_RATE_32K = 6,
0036     MTK_AFE_ADDA_DL_RATE_44K = 7,
0037     MTK_AFE_ADDA_DL_RATE_48K = 8,
0038     MTK_AFE_ADDA_DL_RATE_96K = 9,
0039     MTK_AFE_ADDA_DL_RATE_192K = 10,
0040 };
0041 
0042 enum {
0043     MTK_AFE_ADDA_UL_RATE_8K = 0,
0044     MTK_AFE_ADDA_UL_RATE_16K = 1,
0045     MTK_AFE_ADDA_UL_RATE_32K = 2,
0046     MTK_AFE_ADDA_UL_RATE_48K = 3,
0047     MTK_AFE_ADDA_UL_RATE_96K = 4,
0048     MTK_AFE_ADDA_UL_RATE_192K = 5,
0049 };
0050 
0051 enum {
0052     DELAY_DATA_MISO1 = 0,
0053     DELAY_DATA_MISO0 = 1,
0054     DELAY_DATA_MISO2 = 1,
0055 };
0056 
0057 enum {
0058     MTK_AFE_ADDA,
0059     MTK_AFE_ADDA6,
0060 };
0061 
0062 struct mtk_dai_adda_priv {
0063     bool hires_required;
0064 };
0065 
0066 static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe,
0067                            unsigned int rate)
0068 {
0069     switch (rate) {
0070     case 8000:
0071         return MTK_AFE_ADDA_DL_RATE_8K;
0072     case 11025:
0073         return MTK_AFE_ADDA_DL_RATE_11K;
0074     case 12000:
0075         return MTK_AFE_ADDA_DL_RATE_12K;
0076     case 16000:
0077         return MTK_AFE_ADDA_DL_RATE_16K;
0078     case 22050:
0079         return MTK_AFE_ADDA_DL_RATE_22K;
0080     case 24000:
0081         return MTK_AFE_ADDA_DL_RATE_24K;
0082     case 32000:
0083         return MTK_AFE_ADDA_DL_RATE_32K;
0084     case 44100:
0085         return MTK_AFE_ADDA_DL_RATE_44K;
0086     case 48000:
0087         return MTK_AFE_ADDA_DL_RATE_48K;
0088     case 96000:
0089         return MTK_AFE_ADDA_DL_RATE_96K;
0090     case 192000:
0091         return MTK_AFE_ADDA_DL_RATE_192K;
0092     default:
0093         dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0094              __func__, rate);
0095         return MTK_AFE_ADDA_DL_RATE_48K;
0096     }
0097 }
0098 
0099 static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe,
0100                            unsigned int rate)
0101 {
0102     switch (rate) {
0103     case 8000:
0104         return MTK_AFE_ADDA_UL_RATE_8K;
0105     case 16000:
0106         return MTK_AFE_ADDA_UL_RATE_16K;
0107     case 32000:
0108         return MTK_AFE_ADDA_UL_RATE_32K;
0109     case 48000:
0110         return MTK_AFE_ADDA_UL_RATE_48K;
0111     case 96000:
0112         return MTK_AFE_ADDA_UL_RATE_96K;
0113     case 192000:
0114         return MTK_AFE_ADDA_UL_RATE_192K;
0115     default:
0116         dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0117              __func__, rate);
0118         return MTK_AFE_ADDA_UL_RATE_48K;
0119     }
0120 }
0121 
0122 static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe)
0123 {
0124     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0125     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0126     int delay_data;
0127     int delay_cycle;
0128     unsigned int mask = 0;
0129     unsigned int val = 0;
0130 
0131     /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
0132     mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
0133     val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
0134 
0135     regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
0136     regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val);
0137 
0138     mask = RG_RX_PROTOCOL2;
0139     val = RG_RX_PROTOCOL2;
0140     regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);
0141 
0142     if (!param->mtkaif_calibration_ok) {
0143         dev_info(afe->dev, "%s(), calibration fail\n",  __func__);
0144         return 0;
0145     }
0146 
0147     /* set delay for ch1, ch2 */
0148     if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >=
0149         param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
0150         delay_data = DELAY_DATA_MISO1;
0151         delay_cycle =
0152             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] -
0153             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
0154     } else {
0155         delay_data = DELAY_DATA_MISO0;
0156         delay_cycle =
0157             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
0158             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0];
0159     }
0160 
0161     val = 0;
0162     mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
0163     val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
0164            MTKAIF_RXIF_DELAY_CYCLE_MASK;
0165     val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
0166     regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
0167 
0168     /* set delay between ch3 and ch2 */
0169     if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >=
0170         param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
0171         delay_data = DELAY_DATA_MISO1;
0172         delay_cycle =
0173             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] -
0174             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
0175     } else {
0176         delay_data = DELAY_DATA_MISO2;
0177         delay_cycle =
0178             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
0179             param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2];
0180     }
0181 
0182     val = 0;
0183     mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
0184     val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
0185            MTKAIF_RXIF_DELAY_CYCLE_MASK;
0186     val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
0187     regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val);
0188 
0189     return 0;
0190 }
0191 
0192 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
0193                      struct snd_kcontrol *kcontrol,
0194                      int event)
0195 {
0196     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0197     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0198 
0199     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0200         __func__, w->name, event);
0201 
0202     switch (event) {
0203     case SND_SOC_DAPM_PRE_PMU:
0204         mt8195_adda_mtkaif_init(afe);
0205         break;
0206     default:
0207         break;
0208     }
0209 
0210     return 0;
0211 }
0212 
0213 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
0214                  struct snd_kcontrol *kcontrol,
0215                  int event)
0216 {
0217     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0218     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0219 
0220     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0221         __func__, w->name, event);
0222 
0223     switch (event) {
0224     case SND_SOC_DAPM_POST_PMD:
0225         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0226         usleep_range(125, 135);
0227         break;
0228     default:
0229         break;
0230     }
0231 
0232     return 0;
0233 }
0234 
0235 static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, int adda, bool dmic)
0236 {
0237     unsigned int reg = 0;
0238     unsigned int mask = 0;
0239     unsigned int val = 0;
0240 
0241     switch (adda) {
0242     case MTK_AFE_ADDA:
0243         reg = AFE_ADDA_UL_SRC_CON0;
0244         break;
0245     case MTK_AFE_ADDA6:
0246         reg = AFE_ADDA6_UL_SRC_CON0;
0247         break;
0248     default:
0249         dev_info(afe->dev, "%s(), wrong parameter\n",  __func__);
0250         return;
0251     }
0252 
0253     mask = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL |
0254         UL_MODE_3P25M_CH2_CTL);
0255 
0256     /* turn on dmic, ch1, ch2 */
0257     if (dmic)
0258         val = mask;
0259 
0260     regmap_update_bits(afe->regmap, reg, mask, val);
0261 }
0262 
0263 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
0264                  struct snd_kcontrol *kcontrol,
0265                  int event)
0266 {
0267     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0268     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0269     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0270     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0271 
0272     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0273         __func__, w->name, event);
0274 
0275     switch (event) {
0276     case SND_SOC_DAPM_PRE_PMU:
0277         mtk_adda_ul_mictype(afe, MTK_AFE_ADDA, param->mtkaif_dmic_on);
0278         break;
0279     case SND_SOC_DAPM_POST_PMD:
0280         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0281         usleep_range(125, 135);
0282         break;
0283     default:
0284         break;
0285     }
0286 
0287     return 0;
0288 }
0289 
0290 static int mtk_adda6_ul_event(struct snd_soc_dapm_widget *w,
0291                   struct snd_kcontrol *kcontrol,
0292                   int event)
0293 {
0294     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0295     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0296     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0297     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0298     unsigned int val;
0299 
0300     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0301         __func__, w->name, event);
0302 
0303     switch (event) {
0304     case SND_SOC_DAPM_PRE_PMU:
0305         mtk_adda_ul_mictype(afe, MTK_AFE_ADDA6, param->mtkaif_dmic_on);
0306 
0307         val = (param->mtkaif_adda6_only ?
0308             ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE : 0);
0309 
0310         regmap_update_bits(afe->regmap,
0311                    AFE_ADDA_MTKAIF_SYNCWORD_CFG,
0312                    ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE,
0313                    val);
0314         break;
0315     case SND_SOC_DAPM_POST_PMD:
0316         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0317         usleep_range(125, 135);
0318         break;
0319     default:
0320         break;
0321     }
0322 
0323     return 0;
0324 }
0325 
0326 static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w,
0327                  struct snd_kcontrol *kcontrol,
0328                  int event)
0329 {
0330     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0331     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0332     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0333     struct clk *clk = afe_priv->clk[MT8195_CLK_TOP_AUDIO_H_SEL];
0334     struct clk *clk_parent;
0335 
0336     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0337         __func__, w->name, event);
0338 
0339     switch (event) {
0340     case SND_SOC_DAPM_PRE_PMU:
0341         clk_parent = afe_priv->clk[MT8195_CLK_TOP_APLL1];
0342         break;
0343     case SND_SOC_DAPM_POST_PMD:
0344         clk_parent = afe_priv->clk[MT8195_CLK_XTAL_26M];
0345         break;
0346     default:
0347         return 0;
0348     }
0349     mt8195_afe_set_clk_parent(afe, clk, clk_parent);
0350 
0351     return 0;
0352 }
0353 
0354 static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
0355                                const char *name)
0356 {
0357     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0358     int dai_id;
0359 
0360     if (strstr(name, "aud_adc_hires"))
0361         dai_id = MT8195_AFE_IO_UL_SRC1;
0362     else if (strstr(name, "aud_adda6_adc_hires"))
0363         dai_id = MT8195_AFE_IO_UL_SRC2;
0364     else if (strstr(name, "aud_dac_hires"))
0365         dai_id = MT8195_AFE_IO_DL_SRC;
0366     else
0367         return NULL;
0368 
0369     return afe_priv->dai_priv[dai_id];
0370 }
0371 
0372 static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source,
0373                       struct snd_soc_dapm_widget *sink)
0374 {
0375     struct snd_soc_dapm_widget *w = source;
0376     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0377     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0378     struct mtk_dai_adda_priv *adda_priv;
0379 
0380     adda_priv = get_adda_priv_by_name(afe, w->name);
0381 
0382     if (!adda_priv) {
0383         dev_info(afe->dev, "adda_priv == NULL");
0384         return 0;
0385     }
0386 
0387     return (adda_priv->hires_required) ? 1 : 0;
0388 }
0389 
0390 static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = {
0391     SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0),
0392     SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0),
0393     SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0),
0394     SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0),
0395     SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0),
0396 };
0397 
0398 static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = {
0399     SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0),
0400     SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0),
0401     SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0),
0402     SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0),
0403     SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0),
0404 };
0405 
0406 static const char * const adda_dlgain_mux_map[] = {
0407     "Bypass", "Connect",
0408 };
0409 
0410 static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum,
0411                 SND_SOC_NOPM, 0,
0412                 adda_dlgain_mux_map);
0413 
0414 static const struct snd_kcontrol_new adda_dlgain_mux_control =
0415     SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum);
0416 
0417 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
0418     SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0),
0419     SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0),
0420     SND_SOC_DAPM_MIXER("I170", SND_SOC_NOPM, 0, 0, NULL, 0),
0421     SND_SOC_DAPM_MIXER("I171", SND_SOC_NOPM, 0, 0, NULL, 0),
0422 
0423     SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0,
0424                mtk_dai_adda_o176_mix,
0425                ARRAY_SIZE(mtk_dai_adda_o176_mix)),
0426     SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0,
0427                mtk_dai_adda_o177_mix,
0428                ARRAY_SIZE(mtk_dai_adda_o177_mix)),
0429 
0430     SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
0431                   AFE_ADDA_UL_DL_CON0,
0432                   ADDA_AFE_ON_SHIFT, 0,
0433                   NULL,
0434                   0),
0435 
0436     SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
0437                   AFE_ADDA_DL_SRC2_CON0,
0438                   DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0,
0439                   mtk_adda_dl_event,
0440                   SND_SOC_DAPM_POST_PMD),
0441 
0442     SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
0443                   AFE_ADDA_UL_SRC_CON0,
0444                   UL_SRC_ON_TMP_CTL_SHIFT, 0,
0445                   mtk_adda_ul_event,
0446                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0447 
0448     SND_SOC_DAPM_SUPPLY_S("ADDA6 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
0449                   AFE_ADDA6_UL_SRC_CON0,
0450                   UL_SRC_ON_TMP_CTL_SHIFT, 0,
0451                   mtk_adda6_ul_event,
0452                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0453 
0454     SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL,
0455                   SND_SOC_NOPM,
0456                   0, 0,
0457                   mtk_audio_hires_event,
0458                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0459 
0460     SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
0461                   SND_SOC_NOPM,
0462                   0, 0,
0463                   mtk_adda_mtkaif_cfg_event,
0464                   SND_SOC_DAPM_PRE_PMU),
0465 
0466     SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0,
0467              &adda_dlgain_mux_control),
0468 
0469     SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0,
0470              DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0),
0471 
0472     SND_SOC_DAPM_INPUT("ADDA_INPUT"),
0473     SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"),
0474 
0475     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"),
0476     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"),
0477     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc"),
0478     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"),
0479     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"),
0480     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_hires"),
0481 };
0482 
0483 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
0484     {"ADDA Capture", NULL, "ADDA Enable"},
0485     {"ADDA Capture", NULL, "ADDA Capture Enable"},
0486     {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
0487     {"ADDA Capture", NULL, "aud_adc"},
0488     {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect},
0489     {"aud_adc_hires", NULL, "AUDIO_HIRES"},
0490 
0491     {"ADDA6 Capture", NULL, "ADDA Enable"},
0492     {"ADDA6 Capture", NULL, "ADDA6 Capture Enable"},
0493     {"ADDA6 Capture", NULL, "ADDA_MTKAIF_CFG"},
0494     {"ADDA6 Capture", NULL, "aud_adda6_adc"},
0495     {"ADDA6 Capture", NULL, "aud_adda6_adc_hires",
0496     mtk_afe_adda_hires_connect},
0497     {"aud_adda6_adc_hires", NULL, "AUDIO_HIRES"},
0498 
0499     {"I168", NULL, "ADDA Capture"},
0500     {"I169", NULL, "ADDA Capture"},
0501     {"I170", NULL, "ADDA6 Capture"},
0502     {"I171", NULL, "ADDA6 Capture"},
0503 
0504     {"ADDA Playback", NULL, "ADDA Enable"},
0505     {"ADDA Playback", NULL, "ADDA Playback Enable"},
0506     {"ADDA Playback", NULL, "aud_dac"},
0507     {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect},
0508     {"aud_dac_hires", NULL, "AUDIO_HIRES"},
0509 
0510     {"DL_GAIN", NULL, "O176"},
0511     {"DL_GAIN", NULL, "O177"},
0512 
0513     {"DL_GAIN_MUX", "Bypass", "O176"},
0514     {"DL_GAIN_MUX", "Bypass", "O177"},
0515     {"DL_GAIN_MUX", "Connect", "DL_GAIN"},
0516 
0517     {"ADDA Playback", NULL, "DL_GAIN_MUX"},
0518 
0519     {"O176", "I000 Switch", "I000"},
0520     {"O177", "I001 Switch", "I001"},
0521 
0522     {"O176", "I002 Switch", "I002"},
0523     {"O177", "I003 Switch", "I003"},
0524 
0525     {"O176", "I020 Switch", "I020"},
0526     {"O177", "I021 Switch", "I021"},
0527 
0528     {"O176", "I022 Switch", "I022"},
0529     {"O177", "I023 Switch", "I023"},
0530 
0531     {"O176", "I070 Switch", "I070"},
0532     {"O177", "I071 Switch", "I071"},
0533 
0534     {"ADDA Capture", NULL, "ADDA_INPUT"},
0535     {"ADDA6 Capture", NULL, "ADDA_INPUT"},
0536     {"ADDA_OUTPUT", NULL, "ADDA Playback"},
0537 };
0538 
0539 static int mt8195_adda_dl_gain_put(struct snd_kcontrol *kcontrol,
0540                    struct snd_ctl_elem_value *ucontrol)
0541 {
0542     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0543     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0544     unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
0545     unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
0546     unsigned int value = (unsigned int)(ucontrol->value.integer.value[0]);
0547 
0548     regmap_update_bits(afe->regmap, reg, mask, DL_2_GAIN_CTL_PRE(value));
0549     return 0;
0550 }
0551 
0552 static int mt8195_adda_dl_gain_get(struct snd_kcontrol *kcontrol,
0553                    struct snd_ctl_elem_value *ucontrol)
0554 {
0555     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0556     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0557     unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
0558     unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
0559     unsigned int value = 0;
0560 
0561     regmap_read(afe->regmap, reg, &value);
0562 
0563     ucontrol->value.integer.value[0] = ((value & mask) >>
0564                         DL_2_GAIN_CTL_PRE_SHIFT);
0565     return 0;
0566 }
0567 
0568 static int mt8195_adda6_only_get(struct snd_kcontrol *kcontrol,
0569                  struct snd_ctl_elem_value *ucontrol)
0570 {
0571     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0572     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0573     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0574     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0575 
0576     ucontrol->value.integer.value[0] = param->mtkaif_adda6_only;
0577     return 0;
0578 }
0579 
0580 static int mt8195_adda6_only_set(struct snd_kcontrol *kcontrol,
0581                  struct snd_ctl_elem_value *ucontrol)
0582 {
0583     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0584     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0585     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0586     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0587     int mtkaif_adda6_only;
0588 
0589     mtkaif_adda6_only = ucontrol->value.integer.value[0];
0590 
0591     dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
0592          __func__, kcontrol->id.name, mtkaif_adda6_only);
0593 
0594     param->mtkaif_adda6_only = mtkaif_adda6_only;
0595 
0596     return 0;
0597 }
0598 
0599 static int mt8195_adda_dmic_get(struct snd_kcontrol *kcontrol,
0600                 struct snd_ctl_elem_value *ucontrol)
0601 {
0602     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0603     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0604     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0605     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0606 
0607     ucontrol->value.integer.value[0] = param->mtkaif_dmic_on;
0608     return 0;
0609 }
0610 
0611 static int mt8195_adda_dmic_set(struct snd_kcontrol *kcontrol,
0612                 struct snd_ctl_elem_value *ucontrol)
0613 {
0614     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0615     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0616     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0617     struct mtkaif_param *param = &afe_priv->mtkaif_params;
0618     int dmic_on;
0619 
0620     dmic_on = ucontrol->value.integer.value[0];
0621 
0622     dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
0623         __func__, kcontrol->id.name, dmic_on);
0624 
0625     param->mtkaif_dmic_on = dmic_on;
0626     return 0;
0627 }
0628 
0629 static const struct snd_kcontrol_new mtk_dai_adda_controls[] = {
0630     SOC_SINGLE_EXT("ADDA_DL_Gain", SND_SOC_NOPM, 0, 65535, 0,
0631                mt8195_adda_dl_gain_get, mt8195_adda_dl_gain_put),
0632     SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC", 0,
0633                 mt8195_adda_dmic_get, mt8195_adda_dmic_set),
0634     SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY", 0,
0635                 mt8195_adda6_only_get,
0636                 mt8195_adda6_only_set),
0637 };
0638 
0639 static int mtk_dai_da_configure(struct mtk_base_afe *afe,
0640                 unsigned int rate, int id)
0641 {
0642     unsigned int val = 0;
0643     unsigned int mask = 0;
0644 
0645     /* set sampling rate */
0646     mask |= DL_2_INPUT_MODE_CTL_MASK;
0647     val |= DL_2_INPUT_MODE_CTL(afe_adda_dl_rate_transform(afe, rate));
0648 
0649     /* turn off saturation */
0650     mask |= DL_2_CH1_SATURATION_EN_CTL;
0651     mask |= DL_2_CH2_SATURATION_EN_CTL;
0652 
0653     /* turn off mute function */
0654     mask |= DL_2_MUTE_CH1_OFF_CTL_PRE;
0655     mask |= DL_2_MUTE_CH2_OFF_CTL_PRE;
0656     val |= DL_2_MUTE_CH1_OFF_CTL_PRE;
0657     val |= DL_2_MUTE_CH2_OFF_CTL_PRE;
0658 
0659     /* set voice input data if input sample rate is 8k or 16k */
0660     mask |= DL_2_VOICE_MODE_CTL_PRE;
0661     if (rate == 8000 || rate == 16000)
0662         val |= DL_2_VOICE_MODE_CTL_PRE;
0663 
0664     regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val);
0665 
0666     mask = 0;
0667     val = 0;
0668 
0669     /* new 2nd sdm */
0670     mask |= DL_USE_NEW_2ND_SDM;
0671     val |= DL_USE_NEW_2ND_SDM;
0672     regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, mask, val);
0673 
0674     return 0;
0675 }
0676 
0677 static int mtk_dai_ad_configure(struct mtk_base_afe *afe,
0678                 unsigned int rate, int id)
0679 {
0680     unsigned int val = 0;
0681     unsigned int mask = 0;
0682 
0683     mask |= UL_VOICE_MODE_CTL_MASK;
0684     val |= UL_VOICE_MODE_CTL(afe_adda_ul_rate_transform(afe, rate));
0685 
0686     switch (id) {
0687     case MT8195_AFE_IO_UL_SRC1:
0688         regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
0689                    mask, val);
0690         break;
0691     case MT8195_AFE_IO_UL_SRC2:
0692         regmap_update_bits(afe->regmap, AFE_ADDA6_UL_SRC_CON0,
0693                    mask, val);
0694         break;
0695     default:
0696         break;
0697     }
0698     return 0;
0699 }
0700 
0701 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
0702                   struct snd_pcm_hw_params *params,
0703                   struct snd_soc_dai *dai)
0704 {
0705     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0706     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0707     struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id];
0708     unsigned int rate = params_rate(params);
0709     int id = dai->id;
0710     int ret = 0;
0711 
0712     dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
0713         __func__, id, substream->stream, rate);
0714 
0715     if (rate > ADDA_HIRES_THRES)
0716         adda_priv->hires_required = 1;
0717     else
0718         adda_priv->hires_required = 0;
0719 
0720     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0721         ret = mtk_dai_da_configure(afe, rate, id);
0722     else
0723         ret = mtk_dai_ad_configure(afe, rate, id);
0724 
0725     return ret;
0726 }
0727 
0728 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
0729     .hw_params = mtk_dai_adda_hw_params,
0730 };
0731 
0732 /* dai driver */
0733 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
0734                  SNDRV_PCM_RATE_96000 |\
0735                  SNDRV_PCM_RATE_192000)
0736 
0737 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
0738                 SNDRV_PCM_RATE_16000 |\
0739                 SNDRV_PCM_RATE_32000 |\
0740                 SNDRV_PCM_RATE_48000 |\
0741                 SNDRV_PCM_RATE_96000 |\
0742                 SNDRV_PCM_RATE_192000)
0743 
0744 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0745               SNDRV_PCM_FMTBIT_S24_LE |\
0746               SNDRV_PCM_FMTBIT_S32_LE)
0747 
0748 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
0749     {
0750         .name = "DL_SRC",
0751         .id = MT8195_AFE_IO_DL_SRC,
0752         .playback = {
0753             .stream_name = "ADDA Playback",
0754             .channels_min = 1,
0755             .channels_max = 2,
0756             .rates = MTK_ADDA_PLAYBACK_RATES,
0757             .formats = MTK_ADDA_FORMATS,
0758         },
0759         .ops = &mtk_dai_adda_ops,
0760     },
0761     {
0762         .name = "UL_SRC1",
0763         .id = MT8195_AFE_IO_UL_SRC1,
0764         .capture = {
0765             .stream_name = "ADDA Capture",
0766             .channels_min = 1,
0767             .channels_max = 2,
0768             .rates = MTK_ADDA_CAPTURE_RATES,
0769             .formats = MTK_ADDA_FORMATS,
0770         },
0771         .ops = &mtk_dai_adda_ops,
0772     },
0773     {
0774         .name = "UL_SRC2",
0775         .id = MT8195_AFE_IO_UL_SRC2,
0776         .capture = {
0777             .stream_name = "ADDA6 Capture",
0778             .channels_min = 1,
0779             .channels_max = 2,
0780             .rates = MTK_ADDA_CAPTURE_RATES,
0781             .formats = MTK_ADDA_FORMATS,
0782         },
0783         .ops = &mtk_dai_adda_ops,
0784     },
0785 };
0786 
0787 static int init_adda_priv_data(struct mtk_base_afe *afe)
0788 {
0789     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0790     struct mtk_dai_adda_priv *adda_priv;
0791     static const int adda_dai_list[] = {
0792         MT8195_AFE_IO_DL_SRC,
0793         MT8195_AFE_IO_UL_SRC1,
0794         MT8195_AFE_IO_UL_SRC2
0795     };
0796     int i;
0797 
0798     for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
0799         adda_priv = devm_kzalloc(afe->dev,
0800                      sizeof(struct mtk_dai_adda_priv),
0801                      GFP_KERNEL);
0802         if (!adda_priv)
0803             return -ENOMEM;
0804 
0805         afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
0806     }
0807 
0808     return 0;
0809 }
0810 
0811 int mt8195_dai_adda_register(struct mtk_base_afe *afe)
0812 {
0813     struct mtk_base_afe_dai *dai;
0814 
0815     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
0816     if (!dai)
0817         return -ENOMEM;
0818 
0819     list_add(&dai->list, &afe->sub_dais);
0820 
0821     dai->dai_drivers = mtk_dai_adda_driver;
0822     dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
0823 
0824     dai->dapm_widgets = mtk_dai_adda_widgets;
0825     dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
0826     dai->dapm_routes = mtk_dai_adda_routes;
0827     dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
0828     dai->controls = mtk_dai_adda_controls;
0829     dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls);
0830 
0831     return init_adda_priv_data(afe);
0832 }
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