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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* 0003 * mt8195-audsys-clk.h -- Mediatek 8195 audsys clock definition 0004 * 0005 * Copyright (c) 2021 MediaTek Inc. 0006 * Author: Trevor Wu <trevor.wu@mediatek.com> 0007 */ 0008 0009 #ifndef _MT8195_AUDSYS_CLK_H_ 0010 #define _MT8195_AUDSYS_CLK_H_ 0011 0012 int mt8195_audsys_clk_register(struct mtk_base_afe *afe); 0013 void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe); 0014 0015 #endif
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