mediatek/mt8195/mt8195-audsys-clk.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mt8195-audsys-clk.h  --  Mediatek 8195 audsys clock control
0004  *
0005  * Copyright (c) 2021 MediaTek Inc.
0006  * Author: Trevor Wu <trevor.wu@mediatek.com>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/clkdev.h>
0012 #include "mt8195-afe-common.h"
0013 #include "mt8195-audsys-clk.h"
0014 #include "mt8195-audsys-clkid.h"
0015 #include "mt8195-reg.h"
0016
0017 struct afe_gate {
0018     int id;
0019     const char *name;
0020     const char *parent_name;
0021     int reg;
0022     u8 bit;
0023     const struct clk_ops *ops;
0024     unsigned long flags;
0025     u8 cg_flags;
0026 };
0027
0028 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
0029         .id = _id,                  \
0030         .name = _name,                  \
0031         .parent_name = _parent,             \
0032         .reg = _reg,                    \
0033         .bit = _bit,                    \
0034         .flags = _flags,                \
0035         .cg_flags = _cgflags,               \
0036     }
0037
0038 #define GATE_AFE(_id, _name, _parent, _reg, _bit)       \
0039     GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit,     \
0040                CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
0041
0042 #define GATE_AUD0(_id, _name, _parent, _bit)            \
0043     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
0044
0045 #define GATE_AUD1(_id, _name, _parent, _bit)            \
0046     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
0047
0048 #define GATE_AUD3(_id, _name, _parent, _bit)            \
0049     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
0050
0051 #define GATE_AUD4(_id, _name, _parent, _bit)            \
0052     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
0053
0054 #define GATE_AUD5(_id, _name, _parent, _bit)            \
0055     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
0056
0057 #define GATE_AUD6(_id, _name, _parent, _bit)            \
0058     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
0059
0060 static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
0061     /* AUD0 */
0062     GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2),
0063     GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4),
0064     GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10),
0065     GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11),
0066     GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18),
0067     GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19),
0068     GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20),
0069     GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21),
0070     GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23),
0071     GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24),
0072     GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25),
0073     GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26),
0074     GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27),
0075     GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28),
0076     GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31),
0077
0078     /* AUD1 */
0079     GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2),
0080     GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10),
0081     GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11),
0082     GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12),
0083     GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13),
0084     GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14),
0085     GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16),
0086     GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17),
0087     GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_a1sys_hp", 18),
0088     GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 19),
0089
0090     /* AUD3 */
0091     GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5),
0092     GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7),
0093
0094     /* AUD4 */
0095     GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0),
0096     GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1),
0097     GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6),
0098     GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7),
0099     GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8),
0100     GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16),
0101     GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17),
0102     GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
0103     GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20),
0104     GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21),
0105     GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys_hf", 22),
0106     GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24),
0107     GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys_hf", 30),
0108     GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys_hf", 31),
0109
0110     /* AUD5 */
0111     GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0),
0112     GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1),
0113     GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2),
0114     GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3),
0115     GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4),
0116     GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5),
0117     GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7),
0118     GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8),
0119     GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9),
0120     GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18),
0121     GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19),
0122     GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22),
0123     GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23),
0124     GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24),
0125     GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26),
0126     GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27),
0127
0128     /* AUD6 */
0129     GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0),
0130     GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1),
0131     GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2),
0132     GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3),
0133     GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4),
0134     GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5),
0135     GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6),
0136     GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7),
0137     GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8),
0138     GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9),
0139     GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10),
0140     GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11),
0141     GATE_AUD6(CLK_AUD_GASRC12, "aud_gasrc12", "top_asm_h", 12),
0142     GATE_AUD6(CLK_AUD_GASRC13, "aud_gasrc13", "top_asm_h", 13),
0143     GATE_AUD6(CLK_AUD_GASRC14, "aud_gasrc14", "top_asm_h", 14),
0144     GATE_AUD6(CLK_AUD_GASRC15, "aud_gasrc15", "top_asm_h", 15),
0145     GATE_AUD6(CLK_AUD_GASRC16, "aud_gasrc16", "top_asm_h", 16),
0146     GATE_AUD6(CLK_AUD_GASRC17, "aud_gasrc17", "top_asm_h", 17),
0147     GATE_AUD6(CLK_AUD_GASRC18, "aud_gasrc18", "top_asm_h", 18),
0148     GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "top_asm_h", 19),
0149 };
0150
0151 int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
0152 {
0153     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0154     struct clk *clk;
0155     struct clk_lookup *cl;
0156     int i;
0157
0158     afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
0159                     sizeof(*afe_priv->lookup),
0160                     GFP_KERNEL);
0161
0162     if (!afe_priv->lookup)
0163         return -ENOMEM;
0164
0165     for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
0166         const struct afe_gate *gate = &aud_clks[i];
0167
0168         clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
0169                     gate->flags, afe->base_addr + gate->reg,
0170                     gate->bit, gate->cg_flags, NULL);
0171
0172         if (IS_ERR(clk)) {
0173             dev_err(afe->dev, "Failed to register clk %s: %ld\n",
0174                 gate->name, PTR_ERR(clk));
0175             continue;
0176         }
0177
0178         /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
0179         cl = kzalloc(sizeof(*cl), GFP_KERNEL);
0180         if (!cl)
0181             return -ENOMEM;
0182
0183         cl->clk = clk;
0184         cl->con_id = gate->name;
0185         cl->dev_id = dev_name(afe->dev);
0186         clkdev_add(cl);
0187
0188         afe_priv->lookup[i] = cl;
0189     }
0190
0191     return 0;
0192 }
0193
0194 void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe)
0195 {
0196     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0197     struct clk *clk;
0198     struct clk_lookup *cl;
0199     int i;
0200
0201     if (!afe_priv)
0202         return;
0203
0204     for (i = 0; i < CLK_AUD_NR_CLK; i++) {
0205         cl = afe_priv->lookup[i];
0206         if (!cl)
0207             continue;
0208
0209         clk = cl->clk;
0210         clk_unregister_gate(clk);
0211
0212         clkdev_drop(cl);
0213     }
0214 }