mediatek/mt8195/mt8195-afe-common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt8195-afe-common.h  --  Mediatek 8195 audio driver definitions
0004  *
0005  * Copyright (c) 2021 MediaTek Inc.
0006  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
0007  *         Trevor Wu <trevor.wu@mediatek.com>
0008  */
0009
0010 #ifndef _MT_8195_AFE_COMMON_H_
0011 #define _MT_8195_AFE_COMMON_H_
0012
0013 #include <sound/soc.h>
0014 #include <linux/list.h>
0015 #include <linux/regmap.h>
0016 #include "../common/mtk-base-afe.h"
0017
0018 enum {
0019     MT8195_DAI_START,
0020     MT8195_AFE_MEMIF_START = MT8195_DAI_START,
0021     MT8195_AFE_MEMIF_DL2 = MT8195_AFE_MEMIF_START,
0022     MT8195_AFE_MEMIF_DL3,
0023     MT8195_AFE_MEMIF_DL6,
0024     MT8195_AFE_MEMIF_DL7,
0025     MT8195_AFE_MEMIF_DL8,
0026     MT8195_AFE_MEMIF_DL10,
0027     MT8195_AFE_MEMIF_DL11,
0028     MT8195_AFE_MEMIF_UL_START,
0029     MT8195_AFE_MEMIF_UL1 = MT8195_AFE_MEMIF_UL_START,
0030     MT8195_AFE_MEMIF_UL2,
0031     MT8195_AFE_MEMIF_UL3,
0032     MT8195_AFE_MEMIF_UL4,
0033     MT8195_AFE_MEMIF_UL5,
0034     MT8195_AFE_MEMIF_UL6,
0035     MT8195_AFE_MEMIF_UL8,
0036     MT8195_AFE_MEMIF_UL9,
0037     MT8195_AFE_MEMIF_UL10,
0038     MT8195_AFE_MEMIF_END,
0039     MT8195_AFE_MEMIF_NUM = (MT8195_AFE_MEMIF_END - MT8195_AFE_MEMIF_START),
0040     MT8195_AFE_IO_START = MT8195_AFE_MEMIF_END,
0041     MT8195_AFE_IO_DL_SRC = MT8195_AFE_IO_START,
0042     MT8195_AFE_IO_DPTX,
0043     MT8195_AFE_IO_ETDM_START,
0044     MT8195_AFE_IO_ETDM1_IN = MT8195_AFE_IO_ETDM_START,
0045     MT8195_AFE_IO_ETDM2_IN,
0046     MT8195_AFE_IO_ETDM1_OUT,
0047     MT8195_AFE_IO_ETDM2_OUT,
0048     MT8195_AFE_IO_ETDM3_OUT,
0049     MT8195_AFE_IO_ETDM_END,
0050     MT8195_AFE_IO_ETDM_NUM =
0051         (MT8195_AFE_IO_ETDM_END - MT8195_AFE_IO_ETDM_START),
0052     MT8195_AFE_IO_PCM = MT8195_AFE_IO_ETDM_END,
0053     MT8195_AFE_IO_UL_SRC1,
0054     MT8195_AFE_IO_UL_SRC2,
0055     MT8195_AFE_IO_END,
0056     MT8195_AFE_IO_NUM = (MT8195_AFE_IO_END - MT8195_AFE_IO_START),
0057     MT8195_DAI_END = MT8195_AFE_IO_END,
0058     MT8195_DAI_NUM = (MT8195_DAI_END - MT8195_DAI_START),
0059 };
0060
0061 enum {
0062     MT8195_TOP_CG_A1SYS_TIMING,
0063     MT8195_TOP_CG_A2SYS_TIMING,
0064     MT8195_TOP_CG_26M_TIMING,
0065     MT8195_TOP_CG_NUM,
0066 };
0067
0068 enum {
0069     MT8195_AFE_IRQ_1,
0070     MT8195_AFE_IRQ_2,
0071     MT8195_AFE_IRQ_3,
0072     MT8195_AFE_IRQ_8,
0073     MT8195_AFE_IRQ_9,
0074     MT8195_AFE_IRQ_10,
0075     MT8195_AFE_IRQ_13,
0076     MT8195_AFE_IRQ_14,
0077     MT8195_AFE_IRQ_15,
0078     MT8195_AFE_IRQ_16,
0079     MT8195_AFE_IRQ_17,
0080     MT8195_AFE_IRQ_18,
0081     MT8195_AFE_IRQ_19,
0082     MT8195_AFE_IRQ_20,
0083     MT8195_AFE_IRQ_21,
0084     MT8195_AFE_IRQ_22,
0085     MT8195_AFE_IRQ_23,
0086     MT8195_AFE_IRQ_24,
0087     MT8195_AFE_IRQ_25,
0088     MT8195_AFE_IRQ_26,
0089     MT8195_AFE_IRQ_27,
0090     MT8195_AFE_IRQ_28,
0091     MT8195_AFE_IRQ_NUM,
0092 };
0093
0094 enum {
0095     MT8195_ETDM_OUT1_1X_EN = 9,
0096     MT8195_ETDM_OUT2_1X_EN = 10,
0097     MT8195_ETDM_OUT3_1X_EN = 11,
0098     MT8195_ETDM_IN1_1X_EN = 12,
0099     MT8195_ETDM_IN2_1X_EN = 13,
0100     MT8195_ETDM_IN1_NX_EN = 25,
0101     MT8195_ETDM_IN2_NX_EN = 26,
0102 };
0103
0104 enum {
0105     MT8195_MTKAIF_MISO_0,
0106     MT8195_MTKAIF_MISO_1,
0107     MT8195_MTKAIF_MISO_2,
0108     MT8195_MTKAIF_MISO_NUM,
0109 };
0110
0111 struct mtk_dai_memif_irq_priv {
0112     unsigned int asys_timing_sel;
0113 };
0114
0115 struct mtkaif_param {
0116     bool mtkaif_calibration_ok;
0117     int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
0118     int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
0119     int mtkaif_dmic_on;
0120     int mtkaif_adda6_only;
0121 };
0122
0123 struct clk;
0124
0125 struct mt8195_afe_private {
0126     struct clk **clk;
0127     struct clk_lookup **lookup;
0128     struct regmap *topckgen;
0129     int pm_runtime_bypass_reg_ctl;
0130 #ifdef CONFIG_DEBUG_FS
0131     struct dentry **debugfs_dentry;
0132 #endif
0133     int afe_on_ref_cnt;
0134     int top_cg_ref_cnt[MT8195_TOP_CG_NUM];
0135     spinlock_t afe_ctrl_lock;   /* Lock for afe control */
0136     struct mtk_dai_memif_irq_priv irq_priv[MT8195_AFE_IRQ_NUM];
0137     struct mtkaif_param mtkaif_params;
0138
0139     /* dai */
0140     void *dai_priv[MT8195_DAI_NUM];
0141 };
0142
0143 int mt8195_afe_fs_timing(unsigned int rate);
0144 /* dai register */
0145 int mt8195_dai_adda_register(struct mtk_base_afe *afe);
0146 int mt8195_dai_etdm_register(struct mtk_base_afe *afe);
0147 int mt8195_dai_pcm_register(struct mtk_base_afe *afe);
0148
0149 #define MT8195_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \
0150 { \
0151     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0152     .info = snd_soc_info_enum_double, \
0153     .get = xhandler_get, .put = xhandler_put, \
0154     .device = id, \
0155     .private_value = (unsigned long)&xenum, \
0156 }
0157
0158 #endif