mediatek/mt8195/mt8195-afe-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt8195-afe-clk.h  --  Mediatek 8195 afe clock ctrl definition
0004  *
0005  * Copyright (c) 2021 MediaTek Inc.
0006  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
0007  *         Trevor Wu <trevor.wu@mediatek.com>
0008  */
0009
0010 #ifndef _MT8195_AFE_CLK_H_
0011 #define _MT8195_AFE_CLK_H_
0012
0013 enum {
0014     /* xtal */
0015     MT8195_CLK_XTAL_26M,
0016     /* divider */
0017     MT8195_CLK_TOP_APLL1,
0018     MT8195_CLK_TOP_APLL2,
0019     MT8195_CLK_TOP_APLL12_DIV0,
0020     MT8195_CLK_TOP_APLL12_DIV1,
0021     MT8195_CLK_TOP_APLL12_DIV2,
0022     MT8195_CLK_TOP_APLL12_DIV3,
0023     MT8195_CLK_TOP_APLL12_DIV9,
0024     /* mux */
0025     MT8195_CLK_TOP_A1SYS_HP_SEL,
0026     MT8195_CLK_TOP_AUD_INTBUS_SEL,
0027     MT8195_CLK_TOP_AUDIO_H_SEL,
0028     MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
0029     MT8195_CLK_TOP_DPTX_M_SEL,
0030     MT8195_CLK_TOP_I2SO1_M_SEL,
0031     MT8195_CLK_TOP_I2SO2_M_SEL,
0032     MT8195_CLK_TOP_I2SI1_M_SEL,
0033     MT8195_CLK_TOP_I2SI2_M_SEL,
0034     /* clock gate */
0035     MT8195_CLK_INFRA_AO_AUDIO_26M_B,
0036     MT8195_CLK_SCP_ADSP_AUDIODSP,
0037     MT8195_CLK_AUD_AFE,
0038     MT8195_CLK_AUD_APLL1_TUNER,
0039     MT8195_CLK_AUD_APLL2_TUNER,
0040     MT8195_CLK_AUD_APLL,
0041     MT8195_CLK_AUD_APLL2,
0042     MT8195_CLK_AUD_DAC,
0043     MT8195_CLK_AUD_ADC,
0044     MT8195_CLK_AUD_DAC_HIRES,
0045     MT8195_CLK_AUD_A1SYS_HP,
0046     MT8195_CLK_AUD_ADC_HIRES,
0047     MT8195_CLK_AUD_ADDA6_ADC,
0048     MT8195_CLK_AUD_ADDA6_ADC_HIRES,
0049     MT8195_CLK_AUD_I2SIN,
0050     MT8195_CLK_AUD_TDM_IN,
0051     MT8195_CLK_AUD_I2S_OUT,
0052     MT8195_CLK_AUD_TDM_OUT,
0053     MT8195_CLK_AUD_HDMI_OUT,
0054     MT8195_CLK_AUD_ASRC11,
0055     MT8195_CLK_AUD_ASRC12,
0056     MT8195_CLK_AUD_A1SYS,
0057     MT8195_CLK_AUD_A2SYS,
0058     MT8195_CLK_AUD_PCMIF,
0059     MT8195_CLK_AUD_MEMIF_UL1,
0060     MT8195_CLK_AUD_MEMIF_UL2,
0061     MT8195_CLK_AUD_MEMIF_UL3,
0062     MT8195_CLK_AUD_MEMIF_UL4,
0063     MT8195_CLK_AUD_MEMIF_UL5,
0064     MT8195_CLK_AUD_MEMIF_UL6,
0065     MT8195_CLK_AUD_MEMIF_UL8,
0066     MT8195_CLK_AUD_MEMIF_UL9,
0067     MT8195_CLK_AUD_MEMIF_UL10,
0068     MT8195_CLK_AUD_MEMIF_DL2,
0069     MT8195_CLK_AUD_MEMIF_DL3,
0070     MT8195_CLK_AUD_MEMIF_DL6,
0071     MT8195_CLK_AUD_MEMIF_DL7,
0072     MT8195_CLK_AUD_MEMIF_DL8,
0073     MT8195_CLK_AUD_MEMIF_DL10,
0074     MT8195_CLK_AUD_MEMIF_DL11,
0075     MT8195_CLK_NUM,
0076 };
0077
0078 enum {
0079     MT8195_MCK_SEL_26M,
0080     MT8195_MCK_SEL_APLL1,
0081     MT8195_MCK_SEL_APLL2,
0082     MT8195_MCK_SEL_APLL3,
0083     MT8195_MCK_SEL_APLL4,
0084     MT8195_MCK_SEL_APLL5,
0085     MT8195_MCK_SEL_HDMIRX_APLL,
0086     MT8195_MCK_SEL_NUM,
0087 };
0088
0089 enum {
0090     MT8195_AUD_PLL1,
0091     MT8195_AUD_PLL2,
0092     MT8195_AUD_PLL3,
0093     MT8195_AUD_PLL4,
0094     MT8195_AUD_PLL5,
0095     MT8195_AUD_PLL_NUM,
0096 };
0097
0098 struct mtk_base_afe;
0099
0100 int mt8195_afe_get_mclk_source_clk_id(int sel);
0101 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
0102 int mt8195_afe_get_default_mclk_source_by_rate(int rate);
0103 int mt8195_afe_init_clock(struct mtk_base_afe *afe);
0104 void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
0105 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
0106 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
0107 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
0108 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
0109 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
0110 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
0111 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
0112                 unsigned int rate);
0113 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
0114                   struct clk *parent);
0115 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
0116 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
0117 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
0118 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
0119
0120 #endif