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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mt8195-afe-clk.c  --  Mediatek 8195 afe clock ctrl
0004  *
0005  * Copyright (c) 2021 MediaTek Inc.
0006  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
0007  *         Trevor Wu <trevor.wu@mediatek.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 
0012 #include "mt8195-afe-common.h"
0013 #include "mt8195-afe-clk.h"
0014 #include "mt8195-reg.h"
0015 #include "mt8195-audsys-clk.h"
0016 
0017 static const char *aud_clks[MT8195_CLK_NUM] = {
0018     /* xtal */
0019     [MT8195_CLK_XTAL_26M] = "clk26m",
0020     /* divider */
0021     [MT8195_CLK_TOP_APLL1] = "apll1_ck",
0022     [MT8195_CLK_TOP_APLL2] = "apll2_ck",
0023     [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
0024     [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
0025     [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
0026     [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
0027     [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
0028     /* mux */
0029     [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
0030     [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
0031     [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
0032     [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
0033     [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
0034     [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
0035     [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
0036     [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
0037     [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
0038     /* clock gate */
0039     [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
0040     [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
0041     /* afe clock gate */
0042     [MT8195_CLK_AUD_AFE] = "aud_afe",
0043     [MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
0044     [MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
0045     [MT8195_CLK_AUD_APLL] = "aud_apll",
0046     [MT8195_CLK_AUD_APLL2] = "aud_apll2",
0047     [MT8195_CLK_AUD_DAC] = "aud_dac",
0048     [MT8195_CLK_AUD_ADC] = "aud_adc",
0049     [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
0050     [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
0051     [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
0052     [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
0053     [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
0054     [MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
0055     [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
0056     [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
0057     [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
0058     [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
0059     [MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
0060     [MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
0061     [MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
0062     [MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
0063     [MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
0064     [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
0065     [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
0066     [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
0067     [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
0068     [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
0069     [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
0070     [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
0071     [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
0072     [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
0073     [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
0074     [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
0075     [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
0076     [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
0077     [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
0078     [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
0079     [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
0080 };
0081 
0082 struct mt8195_afe_tuner_cfg {
0083     unsigned int id;
0084     int apll_div_reg;
0085     unsigned int apll_div_shift;
0086     unsigned int apll_div_maskbit;
0087     unsigned int apll_div_default;
0088     int ref_ck_sel_reg;
0089     unsigned int ref_ck_sel_shift;
0090     unsigned int ref_ck_sel_maskbit;
0091     unsigned int ref_ck_sel_default;
0092     int tuner_en_reg;
0093     unsigned int tuner_en_shift;
0094     unsigned int tuner_en_maskbit;
0095     int upper_bound_reg;
0096     unsigned int upper_bound_shift;
0097     unsigned int upper_bound_maskbit;
0098     unsigned int upper_bound_default;
0099     spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
0100     int ref_cnt;
0101 };
0102 
0103 static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = {
0104     [MT8195_AUD_PLL1] = {
0105         .id = MT8195_AUD_PLL1,
0106         .apll_div_reg = AFE_APLL_TUNER_CFG,
0107         .apll_div_shift = 4,
0108         .apll_div_maskbit = 0xf,
0109         .apll_div_default = 0x7,
0110         .ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
0111         .ref_ck_sel_shift = 1,
0112         .ref_ck_sel_maskbit = 0x3,
0113         .ref_ck_sel_default = 0x2,
0114         .tuner_en_reg = AFE_APLL_TUNER_CFG,
0115         .tuner_en_shift = 0,
0116         .tuner_en_maskbit = 0x1,
0117         .upper_bound_reg = AFE_APLL_TUNER_CFG,
0118         .upper_bound_shift = 8,
0119         .upper_bound_maskbit = 0xff,
0120         .upper_bound_default = 0x2,
0121     },
0122     [MT8195_AUD_PLL2] = {
0123         .id = MT8195_AUD_PLL2,
0124         .apll_div_reg = AFE_APLL_TUNER_CFG1,
0125         .apll_div_shift = 4,
0126         .apll_div_maskbit = 0xf,
0127         .apll_div_default = 0x7,
0128         .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
0129         .ref_ck_sel_shift = 1,
0130         .ref_ck_sel_maskbit = 0x3,
0131         .ref_ck_sel_default = 0x1,
0132         .tuner_en_reg = AFE_APLL_TUNER_CFG1,
0133         .tuner_en_shift = 0,
0134         .tuner_en_maskbit = 0x1,
0135         .upper_bound_reg = AFE_APLL_TUNER_CFG1,
0136         .upper_bound_shift = 8,
0137         .upper_bound_maskbit = 0xff,
0138         .upper_bound_default = 0x2,
0139     },
0140     [MT8195_AUD_PLL3] = {
0141         .id = MT8195_AUD_PLL3,
0142         .apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
0143         .apll_div_shift = 4,
0144         .apll_div_maskbit = 0x3f,
0145         .apll_div_default = 0x3,
0146         .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
0147         .ref_ck_sel_shift = 24,
0148         .ref_ck_sel_maskbit = 0x3,
0149         .ref_ck_sel_default = 0x0,
0150         .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
0151         .tuner_en_shift = 0,
0152         .tuner_en_maskbit = 0x1,
0153         .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
0154         .upper_bound_shift = 12,
0155         .upper_bound_maskbit = 0xff,
0156         .upper_bound_default = 0x4,
0157     },
0158     [MT8195_AUD_PLL4] = {
0159         .id = MT8195_AUD_PLL4,
0160         .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
0161         .apll_div_shift = 4,
0162         .apll_div_maskbit = 0x3f,
0163         .apll_div_default = 0x7,
0164         .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
0165         .ref_ck_sel_shift = 8,
0166         .ref_ck_sel_maskbit = 0x1,
0167         .ref_ck_sel_default = 0,
0168         .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
0169         .tuner_en_shift = 0,
0170         .tuner_en_maskbit = 0x1,
0171         .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
0172         .upper_bound_shift = 12,
0173         .upper_bound_maskbit = 0xff,
0174         .upper_bound_default = 0x4,
0175     },
0176     [MT8195_AUD_PLL5] = {
0177         .id = MT8195_AUD_PLL5,
0178         .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
0179         .apll_div_shift = 4,
0180         .apll_div_maskbit = 0x3f,
0181         .apll_div_default = 0x3,
0182         .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
0183         .ref_ck_sel_shift = 24,
0184         .ref_ck_sel_maskbit = 0x1,
0185         .ref_ck_sel_default = 0,
0186         .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
0187         .tuner_en_shift = 0,
0188         .tuner_en_maskbit = 0x1,
0189         .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
0190         .upper_bound_shift = 12,
0191         .upper_bound_maskbit = 0xff,
0192         .upper_bound_default = 0x4,
0193     },
0194 };
0195 
0196 static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id)
0197 {
0198     if (id >= MT8195_AUD_PLL_NUM)
0199         return NULL;
0200 
0201     return &mt8195_afe_tuner_cfgs[id];
0202 }
0203 
0204 static int mt8195_afe_init_apll_tuner(unsigned int id)
0205 {
0206     struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
0207 
0208     if (!cfg)
0209         return -EINVAL;
0210 
0211     cfg->ref_cnt = 0;
0212     spin_lock_init(&cfg->ctrl_lock);
0213 
0214     return 0;
0215 }
0216 
0217 static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe,
0218                        unsigned int id)
0219 {
0220     const struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
0221 
0222     if (!cfg)
0223         return -EINVAL;
0224 
0225     regmap_update_bits(afe->regmap, cfg->apll_div_reg,
0226                cfg->apll_div_maskbit << cfg->apll_div_shift,
0227                cfg->apll_div_default << cfg->apll_div_shift);
0228 
0229     regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg,
0230                cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
0231                cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
0232 
0233     regmap_update_bits(afe->regmap, cfg->upper_bound_reg,
0234                cfg->upper_bound_maskbit << cfg->upper_bound_shift,
0235                cfg->upper_bound_default << cfg->upper_bound_shift);
0236 
0237     return 0;
0238 }
0239 
0240 static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe,
0241                        unsigned int id)
0242 {
0243     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0244 
0245     switch (id) {
0246     case MT8195_AUD_PLL1:
0247         mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
0248         mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
0249         break;
0250     case MT8195_AUD_PLL2:
0251         mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
0252         mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
0253         break;
0254     default:
0255         break;
0256     }
0257 
0258     return 0;
0259 }
0260 
0261 static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe,
0262                     unsigned int id)
0263 {
0264     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0265 
0266     switch (id) {
0267     case MT8195_AUD_PLL1:
0268         mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
0269         mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
0270         break;
0271     case MT8195_AUD_PLL2:
0272         mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
0273         mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
0274         break;
0275     default:
0276         break;
0277     }
0278 
0279     return 0;
0280 }
0281 
0282 static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe,
0283                     unsigned int id)
0284 {
0285     struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
0286     unsigned long flags;
0287     int ret;
0288 
0289     if (!cfg)
0290         return -EINVAL;
0291 
0292     ret = mt8195_afe_setup_apll_tuner(afe, id);
0293     if (ret)
0294         return ret;
0295 
0296     ret = mt8195_afe_enable_tuner_clk(afe, id);
0297     if (ret)
0298         return ret;
0299 
0300     spin_lock_irqsave(&cfg->ctrl_lock, flags);
0301 
0302     cfg->ref_cnt++;
0303     if (cfg->ref_cnt == 1)
0304         regmap_update_bits(afe->regmap,
0305                    cfg->tuner_en_reg,
0306                    cfg->tuner_en_maskbit << cfg->tuner_en_shift,
0307                    1 << cfg->tuner_en_shift);
0308 
0309     spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
0310 
0311     return 0;
0312 }
0313 
0314 static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe,
0315                      unsigned int id)
0316 {
0317     struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
0318     unsigned long flags;
0319     int ret;
0320 
0321     if (!cfg)
0322         return -EINVAL;
0323 
0324     spin_lock_irqsave(&cfg->ctrl_lock, flags);
0325 
0326     cfg->ref_cnt--;
0327     if (cfg->ref_cnt == 0)
0328         regmap_update_bits(afe->regmap,
0329                    cfg->tuner_en_reg,
0330                    cfg->tuner_en_maskbit << cfg->tuner_en_shift,
0331                    0 << cfg->tuner_en_shift);
0332     else if (cfg->ref_cnt < 0)
0333         cfg->ref_cnt = 0;
0334 
0335     spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
0336 
0337     ret = mt8195_afe_disable_tuner_clk(afe, id);
0338     if (ret)
0339         return ret;
0340 
0341     return 0;
0342 }
0343 
0344 int mt8195_afe_get_mclk_source_clk_id(int sel)
0345 {
0346     switch (sel) {
0347     case MT8195_MCK_SEL_26M:
0348         return MT8195_CLK_XTAL_26M;
0349     case MT8195_MCK_SEL_APLL1:
0350         return MT8195_CLK_TOP_APLL1;
0351     case MT8195_MCK_SEL_APLL2:
0352         return MT8195_CLK_TOP_APLL2;
0353     default:
0354         return -EINVAL;
0355     }
0356 }
0357 
0358 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
0359 {
0360     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0361     int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
0362 
0363     if (clk_id < 0) {
0364         dev_dbg(afe->dev, "invalid clk id\n");
0365         return 0;
0366     }
0367 
0368     return clk_get_rate(afe_priv->clk[clk_id]);
0369 }
0370 
0371 int mt8195_afe_get_default_mclk_source_by_rate(int rate)
0372 {
0373     return ((rate % 8000) == 0) ?
0374         MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
0375 }
0376 
0377 int mt8195_afe_init_clock(struct mtk_base_afe *afe)
0378 {
0379     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0380     int i, ret;
0381 
0382     mt8195_audsys_clk_register(afe);
0383 
0384     afe_priv->clk =
0385         devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
0386                  GFP_KERNEL);
0387     if (!afe_priv->clk)
0388         return -ENOMEM;
0389 
0390     for (i = 0; i < MT8195_CLK_NUM; i++) {
0391         afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
0392         if (IS_ERR(afe_priv->clk[i])) {
0393             dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
0394                 __func__, aud_clks[i],
0395                 PTR_ERR(afe_priv->clk[i]));
0396             return PTR_ERR(afe_priv->clk[i]);
0397         }
0398     }
0399 
0400     /* initial tuner */
0401     for (i = 0; i < MT8195_AUD_PLL_NUM; i++) {
0402         ret = mt8195_afe_init_apll_tuner(i);
0403         if (ret) {
0404             dev_dbg(afe->dev, "%s(), init apll_tuner%d failed",
0405                 __func__, (i + 1));
0406             return -EINVAL;
0407         }
0408     }
0409 
0410     return 0;
0411 }
0412 
0413 void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
0414 {
0415     mt8195_audsys_clk_unregister(afe);
0416 }
0417 
0418 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
0419 {
0420     int ret;
0421 
0422     if (clk) {
0423         ret = clk_prepare_enable(clk);
0424         if (ret) {
0425             dev_dbg(afe->dev, "%s(), failed to enable clk\n",
0426                 __func__);
0427             return ret;
0428         }
0429     } else {
0430         dev_dbg(afe->dev, "NULL clk\n");
0431     }
0432     return 0;
0433 }
0434 EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
0435 
0436 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
0437 {
0438     if (clk)
0439         clk_disable_unprepare(clk);
0440     else
0441         dev_dbg(afe->dev, "NULL clk\n");
0442 }
0443 EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
0444 
0445 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
0446 {
0447     int ret;
0448 
0449     if (clk) {
0450         ret = clk_prepare(clk);
0451         if (ret) {
0452             dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
0453                 __func__);
0454             return ret;
0455         }
0456     } else {
0457         dev_dbg(afe->dev, "NULL clk\n");
0458     }
0459     return 0;
0460 }
0461 
0462 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
0463 {
0464     if (clk)
0465         clk_unprepare(clk);
0466     else
0467         dev_dbg(afe->dev, "NULL clk\n");
0468 }
0469 
0470 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
0471 {
0472     int ret;
0473 
0474     if (clk) {
0475         ret = clk_enable(clk);
0476         if (ret) {
0477             dev_dbg(afe->dev, "%s(), failed to clk enable\n",
0478                 __func__);
0479             return ret;
0480         }
0481     } else {
0482         dev_dbg(afe->dev, "NULL clk\n");
0483     }
0484     return 0;
0485 }
0486 
0487 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
0488 {
0489     if (clk)
0490         clk_disable(clk);
0491     else
0492         dev_dbg(afe->dev, "NULL clk\n");
0493 }
0494 
0495 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
0496                 unsigned int rate)
0497 {
0498     int ret;
0499 
0500     if (clk) {
0501         ret = clk_set_rate(clk, rate);
0502         if (ret) {
0503             dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
0504                 __func__);
0505             return ret;
0506         }
0507     }
0508 
0509     return 0;
0510 }
0511 
0512 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
0513                   struct clk *parent)
0514 {
0515     int ret;
0516 
0517     if (clk && parent) {
0518         ret = clk_set_parent(clk, parent);
0519         if (ret) {
0520             dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
0521                 __func__);
0522             return ret;
0523         }
0524     }
0525 
0526     return 0;
0527 }
0528 
0529 static unsigned int get_top_cg_reg(unsigned int cg_type)
0530 {
0531     switch (cg_type) {
0532     case MT8195_TOP_CG_A1SYS_TIMING:
0533     case MT8195_TOP_CG_A2SYS_TIMING:
0534     case MT8195_TOP_CG_26M_TIMING:
0535         return ASYS_TOP_CON;
0536     default:
0537         return 0;
0538     }
0539 }
0540 
0541 static unsigned int get_top_cg_mask(unsigned int cg_type)
0542 {
0543     switch (cg_type) {
0544     case MT8195_TOP_CG_A1SYS_TIMING:
0545         return ASYS_TOP_CON_A1SYS_TIMING_ON;
0546     case MT8195_TOP_CG_A2SYS_TIMING:
0547         return ASYS_TOP_CON_A2SYS_TIMING_ON;
0548     case MT8195_TOP_CG_26M_TIMING:
0549         return ASYS_TOP_CON_26M_TIMING_ON;
0550     default:
0551         return 0;
0552     }
0553 }
0554 
0555 static unsigned int get_top_cg_on_val(unsigned int cg_type)
0556 {
0557     switch (cg_type) {
0558     case MT8195_TOP_CG_A1SYS_TIMING:
0559     case MT8195_TOP_CG_A2SYS_TIMING:
0560     case MT8195_TOP_CG_26M_TIMING:
0561         return get_top_cg_mask(cg_type);
0562     default:
0563         return 0;
0564     }
0565 }
0566 
0567 static unsigned int get_top_cg_off_val(unsigned int cg_type)
0568 {
0569     switch (cg_type) {
0570     case MT8195_TOP_CG_A1SYS_TIMING:
0571     case MT8195_TOP_CG_A2SYS_TIMING:
0572     case MT8195_TOP_CG_26M_TIMING:
0573         return 0;
0574     default:
0575         return get_top_cg_mask(cg_type);
0576     }
0577 }
0578 
0579 static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
0580 {
0581     unsigned int reg = get_top_cg_reg(cg_type);
0582     unsigned int mask = get_top_cg_mask(cg_type);
0583     unsigned int val = get_top_cg_on_val(cg_type);
0584 
0585     regmap_update_bits(afe->regmap, reg, mask, val);
0586     return 0;
0587 }
0588 
0589 static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
0590 {
0591     unsigned int reg = get_top_cg_reg(cg_type);
0592     unsigned int mask = get_top_cg_mask(cg_type);
0593     unsigned int val = get_top_cg_off_val(cg_type);
0594 
0595     regmap_update_bits(afe->regmap, reg, mask, val);
0596     return 0;
0597 }
0598 
0599 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
0600 {
0601     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0602     int i;
0603     static const unsigned int clk_array[] = {
0604         MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
0605         MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
0606         MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
0607         MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
0608         MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
0609         MT8195_CLK_AUD_AFE, /* AFE HW master switch */
0610         MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
0611         MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
0612     };
0613 
0614     for (i = 0; i < ARRAY_SIZE(clk_array); i++)
0615         mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
0616 
0617     return 0;
0618 }
0619 
0620 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
0621 {
0622     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0623     int i;
0624     static const unsigned int clk_array[] = {
0625         MT8195_CLK_AUD_A1SYS,
0626         MT8195_CLK_AUD_A1SYS_HP,
0627         MT8195_CLK_AUD_AFE,
0628         MT8195_CLK_INFRA_AO_AUDIO_26M_B,
0629         MT8195_CLK_TOP_AUD_INTBUS_SEL,
0630         MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
0631         MT8195_CLK_TOP_AUDIO_H_SEL,
0632         MT8195_CLK_SCP_ADSP_AUDIODSP,
0633     };
0634 
0635     for (i = 0; i < ARRAY_SIZE(clk_array); i++)
0636         mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
0637 
0638     return 0;
0639 }
0640 
0641 static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
0642 {
0643     regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
0644     return 0;
0645 }
0646 
0647 static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
0648 {
0649     regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
0650     return 0;
0651 }
0652 
0653 static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
0654 {
0655     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0656     int i;
0657     static const unsigned int clk_array[] = {
0658         MT8195_CLK_AUD_A1SYS,
0659         MT8195_CLK_AUD_A2SYS,
0660     };
0661     static const unsigned int cg_array[] = {
0662         MT8195_TOP_CG_A1SYS_TIMING,
0663         MT8195_TOP_CG_A2SYS_TIMING,
0664         MT8195_TOP_CG_26M_TIMING,
0665     };
0666 
0667     for (i = 0; i < ARRAY_SIZE(clk_array); i++)
0668         mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
0669 
0670     for (i = 0; i < ARRAY_SIZE(cg_array); i++)
0671         mt8195_afe_enable_top_cg(afe, cg_array[i]);
0672 
0673     return 0;
0674 }
0675 
0676 static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
0677 {
0678     struct mt8195_afe_private *afe_priv = afe->platform_priv;
0679     int i;
0680     static const unsigned int clk_array[] = {
0681         MT8195_CLK_AUD_A2SYS,
0682         MT8195_CLK_AUD_A1SYS,
0683     };
0684     static const unsigned int cg_array[] = {
0685         MT8195_TOP_CG_26M_TIMING,
0686         MT8195_TOP_CG_A2SYS_TIMING,
0687         MT8195_TOP_CG_A1SYS_TIMING,
0688     };
0689 
0690     for (i = 0; i < ARRAY_SIZE(cg_array); i++)
0691         mt8195_afe_disable_top_cg(afe, cg_array[i]);
0692 
0693     for (i = 0; i < ARRAY_SIZE(clk_array); i++)
0694         mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
0695 
0696     return 0;
0697 }
0698 
0699 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
0700 {
0701     mt8195_afe_enable_timing_sys(afe);
0702 
0703     mt8195_afe_enable_afe_on(afe);
0704 
0705     mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1);
0706     mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2);
0707 
0708     return 0;
0709 }
0710 
0711 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
0712 {
0713     mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2);
0714     mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1);
0715 
0716     mt8195_afe_disable_afe_on(afe);
0717 
0718     mt8195_afe_disable_timing_sys(afe);
0719 
0720     return 0;
0721 }
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