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0009 #ifndef _MT8192_INTERCONNECTION_H_
0010 #define _MT8192_INTERCONNECTION_H_
0011
0012
0013 #define I_I2S0_CH1 0
0014 #define I_I2S0_CH2 1
0015 #define I_ADDA_UL_CH1 3
0016 #define I_ADDA_UL_CH2 4
0017 #define I_DL1_CH1 5
0018 #define I_DL1_CH2 6
0019 #define I_DL2_CH1 7
0020 #define I_DL2_CH2 8
0021 #define I_PCM_1_CAP_CH1 9
0022 #define I_GAIN1_OUT_CH1 10
0023 #define I_GAIN1_OUT_CH2 11
0024 #define I_GAIN2_OUT_CH1 12
0025 #define I_GAIN2_OUT_CH2 13
0026 #define I_PCM_2_CAP_CH1 14
0027 #define I_ADDA_UL_CH3 17
0028 #define I_ADDA_UL_CH4 18
0029 #define I_DL12_CH1 19
0030 #define I_DL12_CH2 20
0031 #define I_PCM_2_CAP_CH2 21
0032 #define I_PCM_1_CAP_CH2 22
0033 #define I_DL3_CH1 23
0034 #define I_DL3_CH2 24
0035 #define I_I2S2_CH1 25
0036 #define I_I2S2_CH2 26
0037 #define I_I2S2_CH3 27
0038 #define I_I2S2_CH4 28
0039
0040
0041 #define I_32_OFFSET 32
0042 #define I_CONNSYS_I2S_CH1 (34 - I_32_OFFSET)
0043 #define I_CONNSYS_I2S_CH2 (35 - I_32_OFFSET)
0044 #define I_SRC_1_OUT_CH1 (36 - I_32_OFFSET)
0045 #define I_SRC_1_OUT_CH2 (37 - I_32_OFFSET)
0046 #define I_SRC_2_OUT_CH1 (38 - I_32_OFFSET)
0047 #define I_SRC_2_OUT_CH2 (39 - I_32_OFFSET)
0048 #define I_DL4_CH1 (40 - I_32_OFFSET)
0049 #define I_DL4_CH2 (41 - I_32_OFFSET)
0050 #define I_DL5_CH1 (42 - I_32_OFFSET)
0051 #define I_DL5_CH2 (43 - I_32_OFFSET)
0052 #define I_DL6_CH1 (44 - I_32_OFFSET)
0053 #define I_DL6_CH2 (45 - I_32_OFFSET)
0054 #define I_DL7_CH1 (46 - I_32_OFFSET)
0055 #define I_DL7_CH2 (47 - I_32_OFFSET)
0056 #define I_DL8_CH1 (48 - I_32_OFFSET)
0057 #define I_DL8_CH2 (49 - I_32_OFFSET)
0058 #define I_DL9_CH1 (50 - I_32_OFFSET)
0059 #define I_DL9_CH2 (51 - I_32_OFFSET)
0060 #define I_I2S6_CH1 (52 - I_32_OFFSET)
0061 #define I_I2S6_CH2 (53 - I_32_OFFSET)
0062 #define I_I2S8_CH1 (54 - I_32_OFFSET)
0063 #define I_I2S8_CH2 (55 - I_32_OFFSET)
0064
0065 #endif