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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // MediaTek ALSA SoC Audio DAI ADDA Control
0004 //
0005 // Copyright (c) 2020 MediaTek Inc.
0006 // Author: Shane Chien <shane.chien@mediatek.com>
0007 //
0008 
0009 #include <linux/delay.h>
0010 #include <linux/regmap.h>
0011 
0012 #include "mt8192-afe-clk.h"
0013 #include "mt8192-afe-common.h"
0014 #include "mt8192-afe-gpio.h"
0015 #include "mt8192-interconnection.h"
0016 
0017 enum {
0018     UL_IIR_SW = 0,
0019     UL_IIR_5HZ,
0020     UL_IIR_10HZ,
0021     UL_IIR_25HZ,
0022     UL_IIR_50HZ,
0023     UL_IIR_75HZ,
0024 };
0025 
0026 enum {
0027     AUDIO_SDM_LEVEL_MUTE = 0,
0028     AUDIO_SDM_LEVEL_NORMAL = 0x1d,
0029     /* if you change level normal */
0030     /* you need to change formula of hp impedance and dc trim too */
0031 };
0032 
0033 enum {
0034     AUDIO_SDM_2ND = 0,
0035     AUDIO_SDM_3RD,
0036 };
0037 
0038 enum {
0039     DELAY_DATA_MISO1 = 0,
0040     DELAY_DATA_MISO2,
0041 };
0042 
0043 enum {
0044     MTK_AFE_ADDA_DL_RATE_8K = 0,
0045     MTK_AFE_ADDA_DL_RATE_11K = 1,
0046     MTK_AFE_ADDA_DL_RATE_12K = 2,
0047     MTK_AFE_ADDA_DL_RATE_16K = 3,
0048     MTK_AFE_ADDA_DL_RATE_22K = 4,
0049     MTK_AFE_ADDA_DL_RATE_24K = 5,
0050     MTK_AFE_ADDA_DL_RATE_32K = 6,
0051     MTK_AFE_ADDA_DL_RATE_44K = 7,
0052     MTK_AFE_ADDA_DL_RATE_48K = 8,
0053     MTK_AFE_ADDA_DL_RATE_96K = 9,
0054     MTK_AFE_ADDA_DL_RATE_192K = 10,
0055 };
0056 
0057 enum {
0058     MTK_AFE_ADDA_UL_RATE_8K = 0,
0059     MTK_AFE_ADDA_UL_RATE_16K = 1,
0060     MTK_AFE_ADDA_UL_RATE_32K = 2,
0061     MTK_AFE_ADDA_UL_RATE_48K = 3,
0062     MTK_AFE_ADDA_UL_RATE_96K = 4,
0063     MTK_AFE_ADDA_UL_RATE_192K = 5,
0064     MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
0065 };
0066 
0067 #define SDM_AUTO_RESET_THRESHOLD 0x190000
0068 
0069 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
0070                        unsigned int rate)
0071 {
0072     switch (rate) {
0073     case 8000:
0074         return MTK_AFE_ADDA_DL_RATE_8K;
0075     case 11025:
0076         return MTK_AFE_ADDA_DL_RATE_11K;
0077     case 12000:
0078         return MTK_AFE_ADDA_DL_RATE_12K;
0079     case 16000:
0080         return MTK_AFE_ADDA_DL_RATE_16K;
0081     case 22050:
0082         return MTK_AFE_ADDA_DL_RATE_22K;
0083     case 24000:
0084         return MTK_AFE_ADDA_DL_RATE_24K;
0085     case 32000:
0086         return MTK_AFE_ADDA_DL_RATE_32K;
0087     case 44100:
0088         return MTK_AFE_ADDA_DL_RATE_44K;
0089     case 48000:
0090         return MTK_AFE_ADDA_DL_RATE_48K;
0091     case 96000:
0092         return MTK_AFE_ADDA_DL_RATE_96K;
0093     case 192000:
0094         return MTK_AFE_ADDA_DL_RATE_192K;
0095     default:
0096         dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0097              __func__, rate);
0098         return MTK_AFE_ADDA_DL_RATE_48K;
0099     }
0100 }
0101 
0102 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
0103                        unsigned int rate)
0104 {
0105     switch (rate) {
0106     case 8000:
0107         return MTK_AFE_ADDA_UL_RATE_8K;
0108     case 16000:
0109         return MTK_AFE_ADDA_UL_RATE_16K;
0110     case 32000:
0111         return MTK_AFE_ADDA_UL_RATE_32K;
0112     case 48000:
0113         return MTK_AFE_ADDA_UL_RATE_48K;
0114     case 96000:
0115         return MTK_AFE_ADDA_UL_RATE_96K;
0116     case 192000:
0117         return MTK_AFE_ADDA_UL_RATE_192K;
0118     default:
0119         dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0120              __func__, rate);
0121         return MTK_AFE_ADDA_UL_RATE_48K;
0122     }
0123 }
0124 
0125 /* dai component */
0126 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
0127     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
0128     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0),
0129     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
0130     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
0131     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0),
0132     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0),
0133     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0),
0134     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0),
0135     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3,
0136                     I_ADDA_UL_CH3, 1, 0),
0137     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
0138                     I_ADDA_UL_CH2, 1, 0),
0139     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
0140                     I_ADDA_UL_CH1, 1, 0),
0141     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3,
0142                     I_GAIN1_OUT_CH1, 1, 0),
0143     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
0144                     I_PCM_1_CAP_CH1, 1, 0),
0145     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
0146                     I_PCM_2_CAP_CH1, 1, 0),
0147     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1,
0148                     I_SRC_1_OUT_CH1, 1, 0),
0149     SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1,
0150                     I_SRC_2_OUT_CH1, 1, 0),
0151 };
0152 
0153 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
0154     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
0155     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
0156     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0),
0157     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
0158     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
0159     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
0160     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
0161     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0),
0162     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0),
0163     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0),
0164     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0),
0165     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4,
0166                     I_ADDA_UL_CH3, 1, 0),
0167     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
0168                     I_ADDA_UL_CH2, 1, 0),
0169     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
0170                     I_ADDA_UL_CH1, 1, 0),
0171     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4,
0172                     I_GAIN1_OUT_CH2, 1, 0),
0173     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
0174                     I_PCM_1_CAP_CH1, 1, 0),
0175     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
0176                     I_PCM_2_CAP_CH1, 1, 0),
0177     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
0178                     I_PCM_1_CAP_CH2, 1, 0),
0179     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
0180                     I_PCM_2_CAP_CH2, 1, 0),
0181     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1,
0182                     I_SRC_1_OUT_CH2, 1, 0),
0183     SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1,
0184                     I_SRC_2_OUT_CH2, 1, 0),
0185 };
0186 
0187 static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
0188     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0),
0189     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0),
0190     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0),
0191     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0),
0192     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0),
0193     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0),
0194     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0),
0195     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52,
0196                     I_ADDA_UL_CH3, 1, 0),
0197     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52,
0198                     I_ADDA_UL_CH2, 1, 0),
0199     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52,
0200                     I_ADDA_UL_CH1, 1, 0),
0201     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52,
0202                     I_GAIN1_OUT_CH1, 1, 0),
0203     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52,
0204                     I_PCM_1_CAP_CH1, 1, 0),
0205     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52,
0206                     I_PCM_2_CAP_CH1, 1, 0),
0207 };
0208 
0209 static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
0210     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0),
0211     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0),
0212     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0),
0213     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0),
0214     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0),
0215     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0),
0216     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0),
0217     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0),
0218     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0),
0219     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0),
0220     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53,
0221                     I_ADDA_UL_CH3, 1, 0),
0222     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53,
0223                     I_ADDA_UL_CH2, 1, 0),
0224     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53,
0225                     I_ADDA_UL_CH1, 1, 0),
0226     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53,
0227                     I_GAIN1_OUT_CH2, 1, 0),
0228     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53,
0229                     I_PCM_1_CAP_CH1, 1, 0),
0230     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53,
0231                     I_PCM_2_CAP_CH1, 1, 0),
0232     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53,
0233                     I_PCM_1_CAP_CH2, 1, 0),
0234     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53,
0235                     I_PCM_2_CAP_CH2, 1, 0),
0236 };
0237 
0238 static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = {
0239     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19,
0240                     I_ADDA_UL_CH1, 1, 0),
0241 };
0242 
0243 static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = {
0244     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20,
0245                     I_ADDA_UL_CH2, 1, 0),
0246 };
0247 
0248 enum {
0249     SUPPLY_SEQ_ADDA_AFE_ON,
0250     SUPPLY_SEQ_ADDA_DL_ON,
0251     SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
0252     SUPPLY_SEQ_ADDA_MTKAIF_CFG,
0253     SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
0254     SUPPLY_SEQ_ADDA_FIFO,
0255     SUPPLY_SEQ_ADDA_AP_DMIC,
0256     SUPPLY_SEQ_ADDA_UL_ON,
0257 };
0258 
0259 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
0260 {
0261     unsigned int reg;
0262 
0263     switch (id) {
0264     case MT8192_DAI_ADDA:
0265     case MT8192_DAI_AP_DMIC:
0266         reg = AFE_ADDA_UL_SRC_CON0;
0267         break;
0268     case MT8192_DAI_ADDA_CH34:
0269     case MT8192_DAI_AP_DMIC_CH34:
0270         reg = AFE_ADDA6_UL_SRC_CON0;
0271         break;
0272     default:
0273         return -EINVAL;
0274     }
0275 
0276     /* dmic mode, 3.25M*/
0277     regmap_update_bits(afe->regmap, reg,
0278                DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
0279                0x0);
0280     regmap_update_bits(afe->regmap, reg,
0281                DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
0282                0x0);
0283 
0284     /* turn on dmic, ch1, ch2 */
0285     regmap_update_bits(afe->regmap, reg,
0286                UL_SDM_3_LEVEL_CTL_MASK_SFT,
0287                0x1 << UL_SDM_3_LEVEL_CTL_SFT);
0288     regmap_update_bits(afe->regmap, reg,
0289                UL_MODE_3P25M_CH1_CTL_MASK_SFT,
0290                0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
0291     regmap_update_bits(afe->regmap, reg,
0292                UL_MODE_3P25M_CH2_CTL_MASK_SFT,
0293                0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
0294     return 0;
0295 }
0296 
0297 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
0298                  struct snd_kcontrol *kcontrol,
0299                  int event)
0300 {
0301     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0302     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0303     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0304     int mtkaif_dmic = afe_priv->mtkaif_dmic;
0305 
0306     dev_info(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
0307          __func__, w->name, event, mtkaif_dmic);
0308 
0309     switch (event) {
0310     case SND_SOC_DAPM_PRE_PMU:
0311         mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
0312 
0313         /* update setting to dmic */
0314         if (mtkaif_dmic) {
0315             /* mtkaif_rxif_data_mode = 1, dmic */
0316             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0317                        0x1, 0x1);
0318 
0319             /* dmic mode, 3.25M*/
0320             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0321                        MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
0322                        0x0);
0323             mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA);
0324         }
0325         break;
0326     case SND_SOC_DAPM_POST_PMD:
0327         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0328         usleep_range(125, 135);
0329         mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
0330         break;
0331     default:
0332         break;
0333     }
0334 
0335     return 0;
0336 }
0337 
0338 static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w,
0339                   struct snd_kcontrol *kcontrol,
0340                   int event)
0341 {
0342     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0343     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0344     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0345     int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34;
0346     int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only;
0347 
0348     dev_info(afe->dev,
0349          "%s(), name %s, event 0x%x, mtkaif_dmic %d, mtkaif_adda6_only %d\n",
0350          __func__, w->name, event, mtkaif_dmic, mtkaif_adda6_only);
0351 
0352     switch (event) {
0353     case SND_SOC_DAPM_PRE_PMU:
0354         mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
0355                     1);
0356 
0357         /* update setting to dmic */
0358         if (mtkaif_dmic) {
0359             /* mtkaif_rxif_data_mode = 1, dmic */
0360             regmap_update_bits(afe->regmap,
0361                        AFE_ADDA6_MTKAIF_RX_CFG0,
0362                        0x1, 0x1);
0363 
0364             /* dmic mode, 3.25M*/
0365             regmap_update_bits(afe->regmap,
0366                        AFE_ADDA6_MTKAIF_RX_CFG0,
0367                        MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
0368                        0x0);
0369             mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA_CH34);
0370         }
0371 
0372         /* when using adda6 without adda enabled,
0373          * RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or
0374          * data cannot be received.
0375          */
0376         if (mtkaif_adda6_only) {
0377             regmap_update_bits(afe->regmap,
0378                        AFE_ADDA_MTKAIF_SYNCWORD_CFG,
0379                        0x1 << 23, 0x1 << 23);
0380         }
0381         break;
0382     case SND_SOC_DAPM_POST_PMD:
0383         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0384         usleep_range(125, 135);
0385         mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
0386                     1);
0387 
0388         /* reset dmic */
0389         afe_priv->mtkaif_dmic_ch34 = 0;
0390 
0391         if (mtkaif_adda6_only) {
0392             regmap_update_bits(afe->regmap,
0393                        AFE_ADDA_MTKAIF_SYNCWORD_CFG,
0394                        0x1 << 23, 0x0 << 23);
0395         }
0396         break;
0397     default:
0398         break;
0399     }
0400 
0401     return 0;
0402 }
0403 
0404 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
0405                   struct snd_kcontrol *kcontrol,
0406                   int event)
0407 {
0408     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0409     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0410     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0411 
0412     switch (event) {
0413     case SND_SOC_DAPM_PRE_PMU:
0414         if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
0415             regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
0416         else
0417             regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30);
0418         break;
0419     default:
0420         break;
0421     }
0422 
0423     return 0;
0424 }
0425 
0426 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
0427                      struct snd_kcontrol *kcontrol,
0428                      int event)
0429 {
0430     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0431     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0432     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0433     int delay_data;
0434     int delay_cycle;
0435 
0436     switch (event) {
0437     case SND_SOC_DAPM_PRE_PMU:
0438         if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
0439             /* set protocol 2 */
0440             regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0441                      0x00010000);
0442             regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
0443                      0x00010000);
0444 
0445             if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 &&
0446                 (afe_priv->mtkaif_chosen_phase[0] < 0 ||
0447                  afe_priv->mtkaif_chosen_phase[1] < 0)) {
0448                 dev_warn(afe->dev,
0449                      "%s(), mtkaif_chosen_phase[0/1]:%d/%d\n",
0450                      __func__,
0451                      afe_priv->mtkaif_chosen_phase[0],
0452                      afe_priv->mtkaif_chosen_phase[1]);
0453                 break;
0454             } else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 &&
0455                    afe_priv->mtkaif_chosen_phase[2] < 0) {
0456                 dev_warn(afe->dev,
0457                      "%s(), mtkaif_chosen_phase[2]:%d\n",
0458                      __func__,
0459                      afe_priv->mtkaif_chosen_phase[2]);
0460                 break;
0461             }
0462 
0463             /* mtkaif_rxif_clkinv_adc inverse for calibration */
0464             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0465                        MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
0466                        0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
0467             regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
0468                        MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
0469                        0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
0470 
0471             /* set delay for ch12 */
0472             if (afe_priv->mtkaif_phase_cycle[0] >=
0473                 afe_priv->mtkaif_phase_cycle[1]) {
0474                 delay_data = DELAY_DATA_MISO1;
0475                 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
0476                           afe_priv->mtkaif_phase_cycle[1];
0477             } else {
0478                 delay_data = DELAY_DATA_MISO2;
0479                 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
0480                           afe_priv->mtkaif_phase_cycle[0];
0481             }
0482 
0483             regmap_update_bits(afe->regmap,
0484                        AFE_ADDA_MTKAIF_RX_CFG2,
0485                        MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
0486                        delay_data <<
0487                        MTKAIF_RXIF_DELAY_DATA_SFT);
0488 
0489             regmap_update_bits(afe->regmap,
0490                        AFE_ADDA_MTKAIF_RX_CFG2,
0491                        MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
0492                        delay_cycle <<
0493                        MTKAIF_RXIF_DELAY_CYCLE_SFT);
0494 
0495             /* set delay between ch3 and ch2 */
0496             if (afe_priv->mtkaif_phase_cycle[2] >=
0497                 afe_priv->mtkaif_phase_cycle[1]) {
0498                 delay_data = DELAY_DATA_MISO1;  /* ch3 */
0499                 delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
0500                           afe_priv->mtkaif_phase_cycle[1];
0501             } else {
0502                 delay_data = DELAY_DATA_MISO2;  /* ch2 */
0503                 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
0504                           afe_priv->mtkaif_phase_cycle[2];
0505             }
0506 
0507             regmap_update_bits(afe->regmap,
0508                        AFE_ADDA6_MTKAIF_RX_CFG2,
0509                        MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
0510                        delay_data <<
0511                        MTKAIF_RXIF_DELAY_DATA_SFT);
0512             regmap_update_bits(afe->regmap,
0513                        AFE_ADDA6_MTKAIF_RX_CFG2,
0514                        MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
0515                        delay_cycle <<
0516                        MTKAIF_RXIF_DELAY_CYCLE_SFT);
0517         } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
0518             regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0519                      0x00010000);
0520             regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
0521                      0x00010000);
0522         } else {
0523             regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
0524             regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 0x0);
0525         }
0526         break;
0527     default:
0528         break;
0529     }
0530 
0531     return 0;
0532 }
0533 
0534 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
0535                  struct snd_kcontrol *kcontrol,
0536                  int event)
0537 {
0538     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0539     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0540 
0541     dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
0542          __func__, w->name, event);
0543 
0544     switch (event) {
0545     case SND_SOC_DAPM_PRE_PMU:
0546         mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
0547         break;
0548     case SND_SOC_DAPM_POST_PMD:
0549         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0550         usleep_range(125, 135);
0551         mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
0552         break;
0553     default:
0554         break;
0555     }
0556 
0557     return 0;
0558 }
0559 
0560 static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w,
0561                   struct snd_kcontrol *kcontrol,
0562                   int event)
0563 {
0564     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0565     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0566 
0567     dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
0568          __func__, w->name, event);
0569 
0570     switch (event) {
0571     case SND_SOC_DAPM_PRE_PMU:
0572         mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
0573                     0);
0574         break;
0575     case SND_SOC_DAPM_POST_PMD:
0576         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0577         usleep_range(125, 135);
0578         mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
0579                     0);
0580         break;
0581     default:
0582         break;
0583     }
0584 
0585     return 0;
0586 }
0587 
0588 /* stf */
0589 static int stf_positive_gain_get(struct snd_kcontrol *kcontrol,
0590                  struct snd_ctl_elem_value *ucontrol)
0591 {
0592     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0593     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0594     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0595 
0596     ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db;
0597     return 0;
0598 }
0599 
0600 static int stf_positive_gain_set(struct snd_kcontrol *kcontrol,
0601                  struct snd_ctl_elem_value *ucontrol)
0602 {
0603     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0604     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0605     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0606     int gain_db = ucontrol->value.integer.value[0];
0607 
0608     afe_priv->stf_positive_gain_db = gain_db;
0609 
0610     if (gain_db >= 0 && gain_db <= 24) {
0611         regmap_update_bits(afe->regmap,
0612                    AFE_SIDETONE_GAIN,
0613                    POSITIVE_GAIN_MASK_SFT,
0614                    (gain_db / 6) << POSITIVE_GAIN_SFT);
0615     } else {
0616         dev_warn(afe->dev, "%s(), gain_db %d invalid\n",
0617              __func__, gain_db);
0618     }
0619     return 0;
0620 }
0621 
0622 static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol,
0623                 struct snd_ctl_elem_value *ucontrol)
0624 {
0625     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0626     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0627     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0628 
0629     ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
0630     return 0;
0631 }
0632 
0633 static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol,
0634                 struct snd_ctl_elem_value *ucontrol)
0635 {
0636     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0637     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0638     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0639     int dmic_on;
0640 
0641     dmic_on = ucontrol->value.integer.value[0];
0642 
0643     dev_info(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
0644          __func__, kcontrol->id.name, dmic_on);
0645 
0646     afe_priv->mtkaif_dmic = dmic_on;
0647     afe_priv->mtkaif_dmic_ch34 = dmic_on;
0648     return 0;
0649 }
0650 
0651 static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol,
0652                  struct snd_ctl_elem_value *ucontrol)
0653 {
0654     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0655     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0656     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0657 
0658     ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only;
0659     return 0;
0660 }
0661 
0662 static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol,
0663                  struct snd_ctl_elem_value *ucontrol)
0664 {
0665     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0666     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0667     struct mt8192_afe_private *afe_priv = afe->platform_priv;
0668     int mtkaif_adda6_only;
0669 
0670     mtkaif_adda6_only = ucontrol->value.integer.value[0];
0671 
0672     dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
0673          __func__, kcontrol->id.name, mtkaif_adda6_only);
0674 
0675     afe_priv->mtkaif_adda6_only = mtkaif_adda6_only;
0676     return 0;
0677 }
0678 
0679 static const struct snd_kcontrol_new mtk_adda_controls[] = {
0680     SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN,
0681            SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0),
0682     SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 100, 0,
0683                stf_positive_gain_get, stf_positive_gain_set),
0684     SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
0685            DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
0686     SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
0687                 mt8192_adda_dmic_get, mt8192_adda_dmic_set),
0688     SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0,
0689                 mt8192_adda6_only_get, mt8192_adda6_only_set),
0690 };
0691 
0692 static const struct snd_kcontrol_new stf_ctl =
0693     SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
0694 
0695 static const u16 stf_coeff_table_16k[] = {
0696     0x049C, 0x09E8, 0x09E0, 0x089C,
0697     0xFF54, 0xF488, 0xEAFC, 0xEBAC,
0698     0xfA40, 0x17AC, 0x3D1C, 0x6028,
0699     0x7538
0700 };
0701 
0702 static const u16 stf_coeff_table_32k[] = {
0703     0xFE52, 0x0042, 0x00C5, 0x0194,
0704     0x029A, 0x03B7, 0x04BF, 0x057D,
0705     0x05BE, 0x0555, 0x0426, 0x0230,
0706     0xFF92, 0xFC89, 0xF973, 0xF6C6,
0707     0xF500, 0xF49D, 0xF603, 0xF970,
0708     0xFEF3, 0x065F, 0x0F4F, 0x1928,
0709     0x2329, 0x2C80, 0x345E, 0x3A0D,
0710     0x3D08
0711 };
0712 
0713 static const u16 stf_coeff_table_48k[] = {
0714     0x0401, 0xFFB0, 0xFF5A, 0xFECE,
0715     0xFE10, 0xFD28, 0xFC21, 0xFB08,
0716     0xF9EF, 0xF8E8, 0xF80A, 0xF76C,
0717     0xF724, 0xF746, 0xF7E6, 0xF90F,
0718     0xFACC, 0xFD1E, 0xFFFF, 0x0364,
0719     0x0737, 0x0B62, 0x0FC1, 0x1431,
0720     0x188A, 0x1CA4, 0x2056, 0x237D,
0721     0x25F9, 0x27B0, 0x2890
0722 };
0723 
0724 static int mtk_stf_event(struct snd_soc_dapm_widget *w,
0725              struct snd_kcontrol *kcontrol,
0726              int event)
0727 {
0728     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0729     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0730 
0731     size_t half_tap_num;
0732     const u16 *stf_coeff_table;
0733     unsigned int ul_rate, reg_value;
0734     size_t coef_addr;
0735 
0736     regmap_read(afe->regmap, AFE_ADDA_UL_SRC_CON0, &ul_rate);
0737     ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT;
0738     ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK;
0739 
0740     if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) {
0741         half_tap_num = ARRAY_SIZE(stf_coeff_table_48k);
0742         stf_coeff_table = stf_coeff_table_48k;
0743     } else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) {
0744         half_tap_num = ARRAY_SIZE(stf_coeff_table_32k);
0745         stf_coeff_table = stf_coeff_table_32k;
0746     } else {
0747         half_tap_num = ARRAY_SIZE(stf_coeff_table_16k);
0748         stf_coeff_table = stf_coeff_table_16k;
0749     }
0750 
0751     regmap_read(afe->regmap, AFE_SIDETONE_CON1, &reg_value);
0752 
0753     dev_info(afe->dev, "%s(), name %s, event 0x%x, ul_rate 0x%x, AFE_SIDETONE_CON1 0x%x\n",
0754          __func__, w->name, event, ul_rate, reg_value);
0755 
0756     switch (event) {
0757     case SND_SOC_DAPM_PRE_PMU:
0758         /* set side tone gain = 0 */
0759         regmap_update_bits(afe->regmap,
0760                    AFE_SIDETONE_GAIN,
0761                    SIDE_TONE_GAIN_MASK_SFT,
0762                    0);
0763         regmap_update_bits(afe->regmap,
0764                    AFE_SIDETONE_GAIN,
0765                    POSITIVE_GAIN_MASK_SFT,
0766                    0);
0767         /* don't bypass stf */
0768         regmap_update_bits(afe->regmap,
0769                    AFE_SIDETONE_CON1,
0770                    0x1f << 27,
0771                    0x0);
0772         /* set stf half tap num */
0773         regmap_update_bits(afe->regmap,
0774                    AFE_SIDETONE_CON1,
0775                    SIDE_TONE_HALF_TAP_NUM_MASK_SFT,
0776                    half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT);
0777 
0778         /* set side tone coefficient */
0779         regmap_read(afe->regmap, AFE_SIDETONE_CON0, &reg_value);
0780         for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) {
0781             bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
0782             bool new_w_ready = 0;
0783             int try_cnt = 0;
0784 
0785             regmap_update_bits(afe->regmap,
0786                        AFE_SIDETONE_CON0,
0787                        0x39FFFFF,
0788                        (1 << R_W_EN_SFT) |
0789                        (1 << R_W_SEL_SFT) |
0790                        (0 << SEL_CH2_SFT) |
0791                        (coef_addr <<
0792                        SIDE_TONE_COEFFICIENT_ADDR_SFT) |
0793                        stf_coeff_table[coef_addr]);
0794 
0795             /* wait until flag write_ready changed */
0796             for (try_cnt = 0; try_cnt < 10; try_cnt++) {
0797                 regmap_read(afe->regmap,
0798                         AFE_SIDETONE_CON0, &reg_value);
0799                 new_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
0800 
0801                 /* flip => ok */
0802                 if (new_w_ready == old_w_ready) {
0803                     udelay(3);
0804                     if (try_cnt == 9) {
0805                         dev_warn(afe->dev,
0806                              "%s(), write coeff not ready",
0807                              __func__);
0808                     }
0809                 } else {
0810                     break;
0811                 }
0812             }
0813             /* need write -> read -> write to write next coeff */
0814             regmap_update_bits(afe->regmap,
0815                        AFE_SIDETONE_CON0,
0816                        R_W_SEL_MASK_SFT,
0817                        0x0);
0818         }
0819         break;
0820     case SND_SOC_DAPM_POST_PMD:
0821         /* bypass stf */
0822         regmap_update_bits(afe->regmap,
0823                    AFE_SIDETONE_CON1,
0824                    0x1f << 27,
0825                    0x1f << 27);
0826 
0827         /* set side tone gain = 0 */
0828         regmap_update_bits(afe->regmap,
0829                    AFE_SIDETONE_GAIN,
0830                    SIDE_TONE_GAIN_MASK_SFT,
0831                    0);
0832         regmap_update_bits(afe->regmap,
0833                    AFE_SIDETONE_GAIN,
0834                    POSITIVE_GAIN_MASK_SFT,
0835                    0);
0836         break;
0837     default:
0838         break;
0839     }
0840 
0841     return 0;
0842 }
0843 
0844 /* stf mux */
0845 enum {
0846     STF_SRC_ADDA_ADDA6 = 0,
0847     STF_SRC_O19O20,
0848 };
0849 
0850 static const char *const stf_o19o20_mux_map[] = {
0851     "ADDA_ADDA6",
0852     "O19O20",
0853 };
0854 
0855 static int stf_o19o20_mux_map_value[] = {
0856     STF_SRC_ADDA_ADDA6,
0857     STF_SRC_O19O20,
0858 };
0859 
0860 static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum,
0861                   AFE_SIDETONE_CON1,
0862                   STF_SOURCE_FROM_O19O20_SFT,
0863                   STF_SOURCE_FROM_O19O20_MASK,
0864                   stf_o19o20_mux_map,
0865                   stf_o19o20_mux_map_value);
0866 
0867 static const struct snd_kcontrol_new stf_o19O20_mux_control =
0868     SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum);
0869 
0870 enum {
0871     STF_SRC_ADDA = 0,
0872     STF_SRC_ADDA6,
0873 };
0874 
0875 static const char *const stf_adda_mux_map[] = {
0876     "ADDA",
0877     "ADDA6",
0878 };
0879 
0880 static int stf_adda_mux_map_value[] = {
0881     STF_SRC_ADDA,
0882     STF_SRC_ADDA6,
0883 };
0884 
0885 static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum,
0886                   AFE_SIDETONE_CON1,
0887                   STF_O19O20_OUT_EN_SEL_SFT,
0888                   STF_O19O20_OUT_EN_SEL_MASK,
0889                   stf_adda_mux_map,
0890                   stf_adda_mux_map_value);
0891 
0892 static const struct snd_kcontrol_new stf_adda_mux_control =
0893     SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum);
0894 
0895 /* ADDA UL MUX */
0896 enum {
0897     ADDA_UL_MUX_MTKAIF = 0,
0898     ADDA_UL_MUX_AP_DMIC,
0899     ADDA_UL_MUX_MASK = 0x1,
0900 };
0901 
0902 static const char * const adda_ul_mux_map[] = {
0903     "MTKAIF", "AP_DMIC"
0904 };
0905 
0906 static int adda_ul_map_value[] = {
0907     ADDA_UL_MUX_MTKAIF,
0908     ADDA_UL_MUX_AP_DMIC,
0909 };
0910 
0911 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
0912                   SND_SOC_NOPM,
0913                   0,
0914                   ADDA_UL_MUX_MASK,
0915                   adda_ul_mux_map,
0916                   adda_ul_map_value);
0917 
0918 static const struct snd_kcontrol_new adda_ul_mux_control =
0919     SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
0920 
0921 static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
0922     SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
0923 
0924 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
0925     /* inter-connections */
0926     SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
0927                mtk_adda_dl_ch1_mix,
0928                ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
0929     SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
0930                mtk_adda_dl_ch2_mix,
0931                ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
0932 
0933     SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
0934                mtk_adda_dl_ch3_mix,
0935                ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
0936     SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
0937                mtk_adda_dl_ch4_mix,
0938                ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
0939 
0940     SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
0941                   AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
0942                   NULL, 0),
0943 
0944     SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
0945                   AFE_ADDA_DL_SRC2_CON0,
0946                   DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
0947                   mtk_adda_dl_event,
0948                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0949     SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable",
0950                   SUPPLY_SEQ_ADDA_DL_ON,
0951                   AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
0952                   DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
0953                   mtk_adda_ch34_dl_event,
0954                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0955 
0956     SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
0957                   AFE_ADDA_UL_SRC_CON0,
0958                   UL_SRC_ON_TMP_CTL_SFT, 0,
0959                   mtk_adda_ul_event,
0960                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0961     SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
0962                   AFE_ADDA6_UL_SRC_CON0,
0963                   UL_SRC_ON_TMP_CTL_SFT, 0,
0964                   mtk_adda_ch34_ul_event,
0965                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0966 
0967     SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
0968                   AFE_AUD_PAD_TOP,
0969                   RG_RX_FIFO_ON_SFT, 0,
0970                   mtk_adda_pad_top_event,
0971                   SND_SOC_DAPM_PRE_PMU),
0972     SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
0973                   SND_SOC_NOPM, 0, 0,
0974                   mtk_adda_mtkaif_cfg_event,
0975                   SND_SOC_DAPM_PRE_PMU),
0976     SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
0977                   SND_SOC_NOPM, 0, 0,
0978                   mtk_adda_mtkaif_cfg_event,
0979                   SND_SOC_DAPM_PRE_PMU),
0980 
0981     SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
0982                   AFE_ADDA_UL_SRC_CON0,
0983                   UL_AP_DMIC_ON_SFT, 0,
0984                   NULL, 0),
0985     SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
0986                   AFE_ADDA6_UL_SRC_CON0,
0987                   UL_AP_DMIC_ON_SFT, 0,
0988                   NULL, 0),
0989 
0990     SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
0991                   AFE_ADDA_UL_DL_CON0,
0992                   AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
0993                   NULL, 0),
0994     SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
0995                   AFE_ADDA_UL_DL_CON0,
0996                   AFE_ADDA6_FIFO_AUTO_RST_SFT, 1,
0997                   NULL, 0),
0998 
0999     SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
1000              &adda_ul_mux_control),
1001     SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
1002              &adda_ch34_ul_mux_control),
1003 
1004     SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
1005     SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"),
1006 
1007     /* stf */
1008     SND_SOC_DAPM_SWITCH_E("Sidetone Filter",
1009                   AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0,
1010                   &stf_ctl,
1011                   mtk_stf_event,
1012                   SND_SOC_DAPM_PRE_PMU |
1013                   SND_SOC_DAPM_POST_PMD),
1014     SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0,
1015              &stf_o19O20_mux_control),
1016     SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0,
1017              &stf_adda_mux_control),
1018     SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0,
1019                mtk_stf_ch1_mix,
1020                ARRAY_SIZE(mtk_stf_ch1_mix)),
1021     SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0,
1022                mtk_stf_ch2_mix,
1023                ARRAY_SIZE(mtk_stf_ch2_mix)),
1024     SND_SOC_DAPM_OUTPUT("STF_OUTPUT"),
1025 
1026     /* clock */
1027     SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
1028 
1029     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
1030     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
1031     SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"),
1032     SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"),
1033 
1034     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
1035     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"),
1036 };
1037 
1038 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
1039     /* playback */
1040     {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
1041     {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
1042     {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
1043 
1044     {"ADDA_DL_CH1", "DL12_CH1", "DL12"},
1045     {"ADDA_DL_CH2", "DL12_CH2", "DL12"},
1046 
1047     {"ADDA_DL_CH1", "DL6_CH1", "DL6"},
1048     {"ADDA_DL_CH2", "DL6_CH2", "DL6"},
1049 
1050     {"ADDA_DL_CH1", "DL8_CH1", "DL8"},
1051     {"ADDA_DL_CH2", "DL8_CH2", "DL8"},
1052 
1053     {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
1054     {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
1055     {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
1056 
1057     {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
1058     {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
1059     {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
1060 
1061     {"ADDA_DL_CH1", "DL4_CH1", "DL4"},
1062     {"ADDA_DL_CH2", "DL4_CH2", "DL4"},
1063 
1064     {"ADDA_DL_CH1", "DL5_CH1", "DL5"},
1065     {"ADDA_DL_CH2", "DL5_CH2", "DL5"},
1066 
1067     {"ADDA Playback", NULL, "ADDA_DL_CH1"},
1068     {"ADDA Playback", NULL, "ADDA_DL_CH2"},
1069 
1070     {"ADDA Playback", NULL, "ADDA Enable"},
1071     {"ADDA Playback", NULL, "ADDA Playback Enable"},
1072 
1073     {"ADDA_DL_CH3", "DL1_CH1", "DL1"},
1074     {"ADDA_DL_CH4", "DL1_CH1", "DL1"},
1075     {"ADDA_DL_CH4", "DL1_CH2", "DL1"},
1076 
1077     {"ADDA_DL_CH3", "DL12_CH1", "DL12"},
1078     {"ADDA_DL_CH4", "DL12_CH2", "DL12"},
1079 
1080     {"ADDA_DL_CH3", "DL6_CH1", "DL6"},
1081     {"ADDA_DL_CH4", "DL6_CH2", "DL6"},
1082 
1083     {"ADDA_DL_CH3", "DL2_CH1", "DL2"},
1084     {"ADDA_DL_CH4", "DL2_CH1", "DL2"},
1085     {"ADDA_DL_CH4", "DL2_CH2", "DL2"},
1086 
1087     {"ADDA_DL_CH3", "DL3_CH1", "DL3"},
1088     {"ADDA_DL_CH4", "DL3_CH1", "DL3"},
1089     {"ADDA_DL_CH4", "DL3_CH2", "DL3"},
1090 
1091     {"ADDA_DL_CH3", "DL4_CH1", "DL4"},
1092     {"ADDA_DL_CH4", "DL4_CH2", "DL4"},
1093 
1094     {"ADDA_DL_CH3", "DL5_CH1", "DL5"},
1095     {"ADDA_DL_CH4", "DL5_CH2", "DL5"},
1096 
1097     {"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"},
1098     {"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"},
1099 
1100     {"ADDA CH34 Playback", NULL, "ADDA Enable"},
1101     {"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"},
1102 
1103     /* capture */
1104     {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
1105     {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
1106 
1107     {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"},
1108     {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
1109 
1110     {"ADDA Capture", NULL, "ADDA Enable"},
1111     {"ADDA Capture", NULL, "ADDA Capture Enable"},
1112     {"ADDA Capture", NULL, "AUD_PAD_TOP"},
1113     {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
1114 
1115     {"AP DMIC Capture", NULL, "ADDA Enable"},
1116     {"AP DMIC Capture", NULL, "ADDA Capture Enable"},
1117     {"AP DMIC Capture", NULL, "ADDA_FIFO"},
1118     {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
1119 
1120     {"ADDA CH34 Capture", NULL, "ADDA Enable"},
1121     {"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1122     {"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"},
1123     {"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"},
1124 
1125     {"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
1126     {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1127     {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"},
1128     {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
1129 
1130     {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
1131     {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"},
1132 
1133     /* sidetone filter */
1134     {"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"},
1135     {"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"},
1136 
1137     {"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"},
1138     {"STF_O19O20_MUX", "O19O20", "STF_CH1"},
1139     {"STF_O19O20_MUX", "O19O20", "STF_CH2"},
1140 
1141     {"Sidetone Filter", "Switch", "STF_O19O20_MUX"},
1142     {"STF_OUTPUT", NULL, "Sidetone Filter"},
1143     {"ADDA Playback", NULL, "Sidetone Filter"},
1144     {"ADDA CH34 Playback", NULL, "Sidetone Filter"},
1145 
1146     /* clk */
1147     {"ADDA Playback", NULL, "aud_dac_clk"},
1148     {"ADDA Playback", NULL, "aud_dac_predis_clk"},
1149 
1150     {"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"},
1151     {"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"},
1152 
1153     {"ADDA Capture Enable", NULL, "aud_adc_clk"},
1154     {"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"},
1155 };
1156 
1157 /* dai ops */
1158 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
1159                   struct snd_pcm_hw_params *params,
1160                   struct snd_soc_dai *dai)
1161 {
1162     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1163     unsigned int rate = params_rate(params);
1164     int id = dai->id;
1165 
1166     dev_info(afe->dev, "%s(), id %d, stream %d, rate %d\n",
1167          __func__,
1168          id,
1169          substream->stream,
1170          rate);
1171 
1172     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1173         unsigned int dl_src2_con0 = 0;
1174         unsigned int dl_src2_con1 = 0;
1175 
1176         /* set sampling rate */
1177         dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
1178                    DL_2_INPUT_MODE_CTL_SFT;
1179 
1180         /* set output mode, UP_SAMPLING_RATE_X8 */
1181         dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
1182 
1183         /* turn off mute function */
1184         dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
1185         dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
1186 
1187         /* set voice input data if input sample rate is 8k or 16k */
1188         if (rate == 8000 || rate == 16000)
1189             dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT;
1190 
1191         /* SA suggest apply -0.3db to audio/speech path */
1192         dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
1193                    DL_2_GAIN_CTL_PRE_SFT;
1194 
1195         /* turn on down-link gain */
1196         dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT);
1197 
1198         if (id == MT8192_DAI_ADDA) {
1199             /* clean predistortion */
1200             regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
1201             regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
1202 
1203             regmap_write(afe->regmap,
1204                      AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
1205             regmap_write(afe->regmap,
1206                      AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
1207 
1208             /* set sdm gain */
1209             regmap_update_bits(afe->regmap,
1210                        AFE_ADDA_DL_SDM_DCCOMP_CON,
1211                        ATTGAIN_CTL_MASK_SFT,
1212                        AUDIO_SDM_LEVEL_NORMAL <<
1213                        ATTGAIN_CTL_SFT);
1214 
1215             /* 2nd sdm */
1216             regmap_update_bits(afe->regmap,
1217                        AFE_ADDA_DL_SDM_DCCOMP_CON,
1218                        USE_3RD_SDM_MASK_SFT,
1219                        AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1220 
1221             /* sdm auto reset */
1222             regmap_write(afe->regmap,
1223                      AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1224                      SDM_AUTO_RESET_THRESHOLD);
1225             regmap_update_bits(afe->regmap,
1226                        AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1227                        ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1228                        0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT);
1229         } else {
1230             /* clean predistortion */
1231             regmap_write(afe->regmap,
1232                      AFE_ADDA_3RD_DAC_PREDIS_CON0, 0);
1233             regmap_write(afe->regmap,
1234                      AFE_ADDA_3RD_DAC_PREDIS_CON1, 0);
1235 
1236             regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
1237                      dl_src2_con0);
1238             regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1,
1239                      dl_src2_con1);
1240 
1241             /* set sdm gain */
1242             regmap_update_bits(afe->regmap,
1243                        AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1244                        ATTGAIN_CTL_MASK_SFT,
1245                        AUDIO_SDM_LEVEL_NORMAL <<
1246                        ATTGAIN_CTL_SFT);
1247 
1248             /* 2nd sdm */
1249             regmap_update_bits(afe->regmap,
1250                        AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1251                        USE_3RD_SDM_MASK_SFT,
1252                        AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1253 
1254             /* sdm auto reset */
1255             regmap_write(afe->regmap,
1256                      AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1257                      SDM_AUTO_RESET_THRESHOLD);
1258             regmap_update_bits(afe->regmap,
1259                        AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1260                        ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1261                        0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT);
1262         }
1263     } else {
1264         unsigned int voice_mode = 0;
1265         unsigned int ul_src_con0 = 0;   /* default value */
1266 
1267         voice_mode = adda_ul_rate_transform(afe, rate);
1268 
1269         ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
1270 
1271         /* enable iir */
1272         ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
1273                    UL_IIR_ON_TMP_CTL_MASK_SFT;
1274         ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
1275                    UL_IIRMODE_CTL_MASK_SFT;
1276 
1277         switch (id) {
1278         case MT8192_DAI_ADDA:
1279         case MT8192_DAI_AP_DMIC:
1280             /* 35Hz @ 48k */
1281             regmap_write(afe->regmap,
1282                      AFE_ADDA_IIR_COEF_02_01, 0x00000000);
1283             regmap_write(afe->regmap,
1284                      AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
1285             regmap_write(afe->regmap,
1286                      AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
1287             regmap_write(afe->regmap,
1288                      AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
1289             regmap_write(afe->regmap,
1290                      AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
1291 
1292             regmap_write(afe->regmap,
1293                      AFE_ADDA_UL_SRC_CON0, ul_src_con0);
1294 
1295             /* Using Internal ADC */
1296             regmap_update_bits(afe->regmap,
1297                        AFE_ADDA_TOP_CON0,
1298                        0x1 << 0,
1299                        0x0 << 0);
1300 
1301             /* mtkaif_rxif_data_mode = 0, amic */
1302             regmap_update_bits(afe->regmap,
1303                        AFE_ADDA_MTKAIF_RX_CFG0,
1304                        0x1 << 0,
1305                        0x0 << 0);
1306             break;
1307         case MT8192_DAI_ADDA_CH34:
1308         case MT8192_DAI_AP_DMIC_CH34:
1309             /* 35Hz @ 48k */
1310             regmap_write(afe->regmap,
1311                      AFE_ADDA6_IIR_COEF_02_01, 0x00000000);
1312             regmap_write(afe->regmap,
1313                      AFE_ADDA6_IIR_COEF_04_03, 0x00003FB8);
1314             regmap_write(afe->regmap,
1315                      AFE_ADDA6_IIR_COEF_06_05, 0x3FB80000);
1316             regmap_write(afe->regmap,
1317                      AFE_ADDA6_IIR_COEF_08_07, 0x3FB80000);
1318             regmap_write(afe->regmap,
1319                      AFE_ADDA6_IIR_COEF_10_09, 0x0000C048);
1320 
1321             regmap_write(afe->regmap,
1322                      AFE_ADDA6_UL_SRC_CON0, ul_src_con0);
1323 
1324             /* Using Internal ADC */
1325             regmap_update_bits(afe->regmap,
1326                        AFE_ADDA6_TOP_CON0,
1327                        0x1 << 0,
1328                        0x0 << 0);
1329 
1330             /* mtkaif_rxif_data_mode = 0, amic */
1331             regmap_update_bits(afe->regmap,
1332                        AFE_ADDA6_MTKAIF_RX_CFG0,
1333                        0x1 << 0,
1334                        0x0 << 0);
1335             break;
1336         default:
1337             break;
1338         }
1339 
1340         /* ap dmic */
1341         switch (id) {
1342         case MT8192_DAI_AP_DMIC:
1343         case MT8192_DAI_AP_DMIC_CH34:
1344             mtk_adda_ul_src_dmic(afe, id);
1345             break;
1346         default:
1347             break;
1348         }
1349     }
1350 
1351     return 0;
1352 }
1353 
1354 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
1355     .hw_params = mtk_dai_adda_hw_params,
1356 };
1357 
1358 /* dai driver */
1359 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
1360                  SNDRV_PCM_RATE_96000 |\
1361                  SNDRV_PCM_RATE_192000)
1362 
1363 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1364                 SNDRV_PCM_RATE_16000 |\
1365                 SNDRV_PCM_RATE_32000 |\
1366                 SNDRV_PCM_RATE_48000 |\
1367                 SNDRV_PCM_RATE_96000 |\
1368                 SNDRV_PCM_RATE_192000)
1369 
1370 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1371               SNDRV_PCM_FMTBIT_S24_LE |\
1372               SNDRV_PCM_FMTBIT_S32_LE)
1373 
1374 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
1375     {
1376         .name = "ADDA",
1377         .id = MT8192_DAI_ADDA,
1378         .playback = {
1379             .stream_name = "ADDA Playback",
1380             .channels_min = 1,
1381             .channels_max = 2,
1382             .rates = MTK_ADDA_PLAYBACK_RATES,
1383             .formats = MTK_ADDA_FORMATS,
1384         },
1385         .capture = {
1386             .stream_name = "ADDA Capture",
1387             .channels_min = 1,
1388             .channels_max = 2,
1389             .rates = MTK_ADDA_CAPTURE_RATES,
1390             .formats = MTK_ADDA_FORMATS,
1391         },
1392         .ops = &mtk_dai_adda_ops,
1393     },
1394     {
1395         .name = "ADDA_CH34",
1396         .id = MT8192_DAI_ADDA_CH34,
1397         .playback = {
1398             .stream_name = "ADDA CH34 Playback",
1399             .channels_min = 1,
1400             .channels_max = 2,
1401             .rates = MTK_ADDA_PLAYBACK_RATES,
1402             .formats = MTK_ADDA_FORMATS,
1403         },
1404         .capture = {
1405             .stream_name = "ADDA CH34 Capture",
1406             .channels_min = 1,
1407             .channels_max = 2,
1408             .rates = MTK_ADDA_CAPTURE_RATES,
1409             .formats = MTK_ADDA_FORMATS,
1410         },
1411         .ops = &mtk_dai_adda_ops,
1412     },
1413     {
1414         .name = "AP_DMIC",
1415         .id = MT8192_DAI_AP_DMIC,
1416         .capture = {
1417             .stream_name = "AP DMIC Capture",
1418             .channels_min = 1,
1419             .channels_max = 2,
1420             .rates = MTK_ADDA_CAPTURE_RATES,
1421             .formats = MTK_ADDA_FORMATS,
1422         },
1423         .ops = &mtk_dai_adda_ops,
1424     },
1425     {
1426         .name = "AP_DMIC_CH34",
1427         .id = MT8192_DAI_AP_DMIC_CH34,
1428         .capture = {
1429             .stream_name = "AP DMIC CH34 Capture",
1430             .channels_min = 1,
1431             .channels_max = 2,
1432             .rates = MTK_ADDA_CAPTURE_RATES,
1433             .formats = MTK_ADDA_FORMATS,
1434         },
1435         .ops = &mtk_dai_adda_ops,
1436     },
1437 };
1438 
1439 int mt8192_dai_adda_register(struct mtk_base_afe *afe)
1440 {
1441     struct mtk_base_afe_dai *dai;
1442     struct mt8192_afe_private *afe_priv = afe->platform_priv;
1443 
1444     dev_info(afe->dev, "%s()\n", __func__);
1445 
1446     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1447     if (!dai)
1448         return -ENOMEM;
1449 
1450     list_add(&dai->list, &afe->sub_dais);
1451 
1452     dai->dai_drivers = mtk_dai_adda_driver;
1453     dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
1454 
1455     dai->controls = mtk_adda_controls;
1456     dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
1457     dai->dapm_widgets = mtk_dai_adda_widgets;
1458     dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
1459     dai->dapm_routes = mtk_dai_adda_routes;
1460     dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
1461 
1462     /* ap dmic priv share with adda */
1463     afe_priv->dai_priv[MT8192_DAI_AP_DMIC] =
1464         afe_priv->dai_priv[MT8192_DAI_ADDA];
1465     afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] =
1466         afe_priv->dai_priv[MT8192_DAI_ADDA_CH34];
1467 
1468     return 0;
1469 }
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