Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Mediatek ALSA SoC AFE platform driver for 8192
0004 //
0005 // Copyright (c) 2020 MediaTek Inc.
0006 // Author: Shane Chien <shane.chien@mediatek.com>
0007 //
0008 
0009 #include <linux/delay.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/module.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/reset.h>
0017 #include <sound/soc.h>
0018 
0019 #include "../common/mtk-afe-fe-dai.h"
0020 #include "../common/mtk-afe-platform-driver.h"
0021 
0022 #include "mt8192-afe-common.h"
0023 #include "mt8192-afe-clk.h"
0024 #include "mt8192-afe-gpio.h"
0025 #include "mt8192-interconnection.h"
0026 
0027 static const struct snd_pcm_hardware mt8192_afe_hardware = {
0028     .info = (SNDRV_PCM_INFO_MMAP |
0029          SNDRV_PCM_INFO_INTERLEAVED |
0030          SNDRV_PCM_INFO_MMAP_VALID),
0031     .formats = (SNDRV_PCM_FMTBIT_S16_LE |
0032             SNDRV_PCM_FMTBIT_S24_LE |
0033             SNDRV_PCM_FMTBIT_S32_LE),
0034     .period_bytes_min = 96,
0035     .period_bytes_max = 4 * 48 * 1024,
0036     .periods_min = 2,
0037     .periods_max = 256,
0038     .buffer_bytes_max = 4 * 48 * 1024,
0039     .fifo_size = 0,
0040 };
0041 
0042 static int mt8192_memif_fs(struct snd_pcm_substream *substream,
0043                unsigned int rate)
0044 {
0045     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0046     struct snd_soc_component *component =
0047         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0048     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0049     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0050 
0051     return mt8192_rate_transform(afe->dev, rate, id);
0052 }
0053 
0054 static int mt8192_get_dai_fs(struct mtk_base_afe *afe,
0055                  int dai_id, unsigned int rate)
0056 {
0057     return mt8192_rate_transform(afe->dev, rate, dai_id);
0058 }
0059 
0060 static int mt8192_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
0061 {
0062     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0063     struct snd_soc_component *component =
0064         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0065     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0066 
0067     return mt8192_general_rate_transform(afe->dev, rate);
0068 }
0069 
0070 static int mt8192_get_memif_pbuf_size(struct snd_pcm_substream *substream)
0071 {
0072     struct snd_pcm_runtime *runtime = substream->runtime;
0073 
0074     if ((runtime->period_size * 1000) / runtime->rate > 10)
0075         return MT8192_MEMIF_PBUF_SIZE_256_BYTES;
0076     else
0077         return MT8192_MEMIF_PBUF_SIZE_32_BYTES;
0078 }
0079 
0080 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
0081                SNDRV_PCM_RATE_88200 |\
0082                SNDRV_PCM_RATE_96000 |\
0083                SNDRV_PCM_RATE_176400 |\
0084                SNDRV_PCM_RATE_192000)
0085 
0086 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
0087                SNDRV_PCM_RATE_16000 |\
0088                SNDRV_PCM_RATE_32000 |\
0089                SNDRV_PCM_RATE_48000)
0090 
0091 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0092              SNDRV_PCM_FMTBIT_S24_LE |\
0093              SNDRV_PCM_FMTBIT_S32_LE)
0094 
0095 static struct snd_soc_dai_driver mt8192_memif_dai_driver[] = {
0096     /* FE DAIs: memory intefaces to CPU */
0097     {
0098         .name = "DL1",
0099         .id = MT8192_MEMIF_DL1,
0100         .playback = {
0101             .stream_name = "DL1",
0102             .channels_min = 1,
0103             .channels_max = 2,
0104             .rates = MTK_PCM_RATES,
0105             .formats = MTK_PCM_FORMATS,
0106         },
0107         .ops = &mtk_afe_fe_ops,
0108     },
0109     {
0110         .name = "DL12",
0111         .id = MT8192_MEMIF_DL12,
0112         .playback = {
0113             .stream_name = "DL12",
0114             .channels_min = 1,
0115             .channels_max = 2,
0116             .rates = MTK_PCM_RATES,
0117             .formats = MTK_PCM_FORMATS,
0118         },
0119         .ops = &mtk_afe_fe_ops,
0120     },
0121     {
0122         .name = "DL2",
0123         .id = MT8192_MEMIF_DL2,
0124         .playback = {
0125             .stream_name = "DL2",
0126             .channels_min = 1,
0127             .channels_max = 2,
0128             .rates = MTK_PCM_RATES,
0129             .formats = MTK_PCM_FORMATS,
0130         },
0131         .ops = &mtk_afe_fe_ops,
0132     },
0133     {
0134         .name = "DL3",
0135         .id = MT8192_MEMIF_DL3,
0136         .playback = {
0137             .stream_name = "DL3",
0138             .channels_min = 1,
0139             .channels_max = 2,
0140             .rates = MTK_PCM_RATES,
0141             .formats = MTK_PCM_FORMATS,
0142         },
0143         .ops = &mtk_afe_fe_ops,
0144     },
0145     {
0146         .name = "DL4",
0147         .id = MT8192_MEMIF_DL4,
0148         .playback = {
0149             .stream_name = "DL4",
0150             .channels_min = 1,
0151             .channels_max = 2,
0152             .rates = MTK_PCM_RATES,
0153             .formats = MTK_PCM_FORMATS,
0154         },
0155         .ops = &mtk_afe_fe_ops,
0156     },
0157     {
0158         .name = "DL5",
0159         .id = MT8192_MEMIF_DL5,
0160         .playback = {
0161             .stream_name = "DL5",
0162             .channels_min = 1,
0163             .channels_max = 2,
0164             .rates = MTK_PCM_RATES,
0165             .formats = MTK_PCM_FORMATS,
0166         },
0167         .ops = &mtk_afe_fe_ops,
0168     },
0169     {
0170         .name = "DL6",
0171         .id = MT8192_MEMIF_DL6,
0172         .playback = {
0173             .stream_name = "DL6",
0174             .channels_min = 1,
0175             .channels_max = 2,
0176             .rates = MTK_PCM_RATES,
0177             .formats = MTK_PCM_FORMATS,
0178         },
0179         .ops = &mtk_afe_fe_ops,
0180     },
0181     {
0182         .name = "DL7",
0183         .id = MT8192_MEMIF_DL7,
0184         .playback = {
0185             .stream_name = "DL7",
0186             .channels_min = 1,
0187             .channels_max = 2,
0188             .rates = MTK_PCM_RATES,
0189             .formats = MTK_PCM_FORMATS,
0190         },
0191         .ops = &mtk_afe_fe_ops,
0192     },
0193     {
0194         .name = "DL8",
0195         .id = MT8192_MEMIF_DL8,
0196         .playback = {
0197             .stream_name = "DL8",
0198             .channels_min = 1,
0199             .channels_max = 2,
0200             .rates = MTK_PCM_RATES,
0201             .formats = MTK_PCM_FORMATS,
0202         },
0203         .ops = &mtk_afe_fe_ops,
0204     },
0205     {
0206         .name = "DL9",
0207         .id = MT8192_MEMIF_DL9,
0208         .playback = {
0209             .stream_name = "DL9",
0210             .channels_min = 1,
0211             .channels_max = 2,
0212             .rates = MTK_PCM_RATES,
0213             .formats = MTK_PCM_FORMATS,
0214         },
0215         .ops = &mtk_afe_fe_ops,
0216     },
0217     {
0218         .name = "UL1",
0219         .id = MT8192_MEMIF_VUL12,
0220         .capture = {
0221             .stream_name = "UL1",
0222             .channels_min = 1,
0223             .channels_max = 4,
0224             .rates = MTK_PCM_RATES,
0225             .formats = MTK_PCM_FORMATS,
0226         },
0227         .ops = &mtk_afe_fe_ops,
0228     },
0229     {
0230         .name = "UL2",
0231         .id = MT8192_MEMIF_AWB,
0232         .capture = {
0233             .stream_name = "UL2",
0234             .channels_min = 1,
0235             .channels_max = 2,
0236             .rates = MTK_PCM_RATES,
0237             .formats = MTK_PCM_FORMATS,
0238         },
0239         .ops = &mtk_afe_fe_ops,
0240     },
0241     {
0242         .name = "UL3",
0243         .id = MT8192_MEMIF_VUL2,
0244         .capture = {
0245             .stream_name = "UL3",
0246             .channels_min = 1,
0247             .channels_max = 2,
0248             .rates = MTK_PCM_RATES,
0249             .formats = MTK_PCM_FORMATS,
0250         },
0251         .ops = &mtk_afe_fe_ops,
0252     },
0253     {
0254         .name = "UL4",
0255         .id = MT8192_MEMIF_AWB2,
0256         .capture = {
0257             .stream_name = "UL4",
0258             .channels_min = 1,
0259             .channels_max = 2,
0260             .rates = MTK_PCM_RATES,
0261             .formats = MTK_PCM_FORMATS,
0262         },
0263         .ops = &mtk_afe_fe_ops,
0264     },
0265     {
0266         .name = "UL5",
0267         .id = MT8192_MEMIF_VUL3,
0268         .capture = {
0269             .stream_name = "UL5",
0270             .channels_min = 1,
0271             .channels_max = 2,
0272             .rates = MTK_PCM_RATES,
0273             .formats = MTK_PCM_FORMATS,
0274         },
0275         .ops = &mtk_afe_fe_ops,
0276     },
0277     {
0278         .name = "UL6",
0279         .id = MT8192_MEMIF_VUL4,
0280         .capture = {
0281             .stream_name = "UL6",
0282             .channels_min = 1,
0283             .channels_max = 2,
0284             .rates = MTK_PCM_RATES,
0285             .formats = MTK_PCM_FORMATS,
0286         },
0287         .ops = &mtk_afe_fe_ops,
0288     },
0289     {
0290         .name = "UL7",
0291         .id = MT8192_MEMIF_VUL5,
0292         .capture = {
0293             .stream_name = "UL7",
0294             .channels_min = 1,
0295             .channels_max = 2,
0296             .rates = MTK_PCM_RATES,
0297             .formats = MTK_PCM_FORMATS,
0298         },
0299         .ops = &mtk_afe_fe_ops,
0300     },
0301     {
0302         .name = "UL8",
0303         .id = MT8192_MEMIF_VUL6,
0304         .capture = {
0305             .stream_name = "UL8",
0306             .channels_min = 1,
0307             .channels_max = 2,
0308             .rates = MTK_PCM_RATES,
0309             .formats = MTK_PCM_FORMATS,
0310         },
0311         .ops = &mtk_afe_fe_ops,
0312     },
0313     {
0314         .name = "UL_MONO_1",
0315         .id = MT8192_MEMIF_MOD_DAI,
0316         .capture = {
0317             .stream_name = "UL_MONO_1",
0318             .channels_min = 1,
0319             .channels_max = 2,
0320             .rates = MTK_PCM_DAI_RATES,
0321             .formats = MTK_PCM_FORMATS,
0322         },
0323         .ops = &mtk_afe_fe_ops,
0324     },
0325     {
0326         .name = "UL_MONO_2",
0327         .id = MT8192_MEMIF_DAI,
0328         .capture = {
0329             .stream_name = "UL_MONO_2",
0330             .channels_min = 1,
0331             .channels_max = 2,
0332             .rates = MTK_PCM_DAI_RATES,
0333             .formats = MTK_PCM_FORMATS,
0334         },
0335         .ops = &mtk_afe_fe_ops,
0336     },
0337     {
0338         .name = "UL_MONO_3",
0339         .id = MT8192_MEMIF_DAI2,
0340         .capture = {
0341             .stream_name = "UL_MONO_3",
0342             .channels_min = 1,
0343             .channels_max = 2,
0344             .rates = MTK_PCM_DAI_RATES,
0345             .formats = MTK_PCM_FORMATS,
0346         },
0347         .ops = &mtk_afe_fe_ops,
0348     },
0349     {
0350         .name = "HDMI",
0351         .id = MT8192_MEMIF_HDMI,
0352         .playback = {
0353             .stream_name = "HDMI",
0354             .channels_min = 2,
0355             .channels_max = 8,
0356             .rates = MTK_PCM_RATES,
0357             .formats = MTK_PCM_FORMATS,
0358         },
0359         .ops = &mtk_afe_fe_ops,
0360     },
0361 };
0362 
0363 static int ul_tinyconn_event(struct snd_soc_dapm_widget *w,
0364                  struct snd_kcontrol *kcontrol,
0365                  int event)
0366 {
0367     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0368     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0369     unsigned int reg_shift;
0370     unsigned int reg_mask_shift;
0371 
0372     dev_info(afe->dev, "%s(), event 0x%x\n", __func__, event);
0373 
0374     if (strstr(w->name, "UL1")) {
0375         reg_shift = VUL1_USE_TINY_SFT;
0376         reg_mask_shift = VUL1_USE_TINY_MASK_SFT;
0377     } else if (strstr(w->name, "UL2")) {
0378         reg_shift = VUL2_USE_TINY_SFT;
0379         reg_mask_shift = VUL2_USE_TINY_MASK_SFT;
0380     } else if (strstr(w->name, "UL3")) {
0381         reg_shift = VUL12_USE_TINY_SFT;
0382         reg_mask_shift = VUL12_USE_TINY_MASK_SFT;
0383     } else if (strstr(w->name, "UL4")) {
0384         reg_shift = AWB2_USE_TINY_SFT;
0385         reg_mask_shift = AWB2_USE_TINY_MASK_SFT;
0386     } else {
0387         reg_shift = AWB2_USE_TINY_SFT;
0388         reg_mask_shift = AWB2_USE_TINY_MASK_SFT;
0389         dev_warn(afe->dev, "%s(), err widget name %s, default use UL4",
0390              __func__, w->name);
0391     }
0392 
0393     switch (event) {
0394     case SND_SOC_DAPM_PRE_PMU:
0395         regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift,
0396                    0x1 << reg_shift);
0397         break;
0398     case SND_SOC_DAPM_PRE_PMD:
0399         regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift,
0400                    0x0 << reg_shift);
0401         break;
0402     default:
0403         break;
0404     }
0405 
0406     return 0;
0407 }
0408 
0409 /* dma widget & routes*/
0410 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
0411     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
0412                     I_ADDA_UL_CH1, 1, 0),
0413     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN21,
0414                     I_ADDA_UL_CH2, 1, 0),
0415     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN21,
0416                     I_ADDA_UL_CH3, 1, 0),
0417 };
0418 
0419 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
0420     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN22,
0421                     I_ADDA_UL_CH1, 1, 0),
0422     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
0423                     I_ADDA_UL_CH2, 1, 0),
0424     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN22,
0425                     I_ADDA_UL_CH3, 1, 0),
0426     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN22,
0427                     I_ADDA_UL_CH4, 1, 0),
0428 };
0429 
0430 static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = {
0431     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,
0432                     I_ADDA_UL_CH1, 1, 0),
0433     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN9,
0434                     I_ADDA_UL_CH2, 1, 0),
0435     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN9,
0436                     I_ADDA_UL_CH3, 1, 0),
0437 };
0438 
0439 static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = {
0440     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN10,
0441                     I_ADDA_UL_CH1, 1, 0),
0442     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,
0443                     I_ADDA_UL_CH2, 1, 0),
0444     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN10,
0445                     I_ADDA_UL_CH3, 1, 0),
0446     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN10,
0447                     I_ADDA_UL_CH4, 1, 0),
0448 };
0449 
0450 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
0451     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN5,
0452                     I_I2S0_CH1, 1, 0),
0453     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
0454                     I_DL1_CH1, 1, 0),
0455     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN5,
0456                     I_DL12_CH1, 1, 0),
0457     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
0458                     I_DL2_CH1, 1, 0),
0459     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
0460                     I_DL3_CH1, 1, 0),
0461     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN5_1,
0462                     I_DL4_CH1, 1, 0),
0463     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN5_1,
0464                     I_DL5_CH1, 1, 0),
0465     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN5_1,
0466                     I_DL6_CH1, 1, 0),
0467     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN5,
0468                     I_PCM_1_CAP_CH1, 1, 0),
0469     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN5,
0470                     I_PCM_2_CAP_CH1, 1, 0),
0471     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
0472                     I_I2S2_CH1, 1, 0),
0473     SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH1", AFE_CONN5_1,
0474                     I_I2S6_CH1, 1, 0),
0475     SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH1", AFE_CONN5_1,
0476                     I_I2S8_CH1, 1, 0),
0477     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN5_1,
0478                     I_CONNSYS_I2S_CH1, 1, 0),
0479     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN5_1,
0480                     I_SRC_1_OUT_CH1, 1, 0),
0481 };
0482 
0483 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
0484     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN6,
0485                     I_I2S0_CH2, 1, 0),
0486     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
0487                     I_DL1_CH2, 1, 0),
0488     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN6,
0489                     I_DL12_CH2, 1, 0),
0490     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
0491                     I_DL2_CH2, 1, 0),
0492     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
0493                     I_DL3_CH2, 1, 0),
0494     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN6_1,
0495                     I_DL4_CH2, 1, 0),
0496     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN6_1,
0497                     I_DL5_CH2, 1, 0),
0498     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN6_1,
0499                     I_DL6_CH2, 1, 0),
0500     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN6,
0501                     I_PCM_1_CAP_CH1, 1, 0),
0502     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN6,
0503                     I_PCM_2_CAP_CH1, 1, 0),
0504     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
0505                     I_I2S2_CH2, 1, 0),
0506     SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH2", AFE_CONN6_1,
0507                     I_I2S6_CH2, 1, 0),
0508     SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH2", AFE_CONN6_1,
0509                     I_I2S8_CH2, 1, 0),
0510     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN6_1,
0511                     I_CONNSYS_I2S_CH2, 1, 0),
0512     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN6_1,
0513                     I_SRC_1_OUT_CH2, 1, 0),
0514 };
0515 
0516 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
0517     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN32_1,
0518                     I_CONNSYS_I2S_CH1, 1, 0),
0519     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN32,
0520                     I_DL1_CH1, 1, 0),
0521     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN32,
0522                     I_DL2_CH1, 1, 0),
0523 };
0524 
0525 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
0526     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN33_1,
0527                     I_CONNSYS_I2S_CH2, 1, 0),
0528 };
0529 
0530 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
0531     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
0532                     I_ADDA_UL_CH1, 1, 0),
0533     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN38,
0534                     I_I2S0_CH1, 1, 0),
0535 };
0536 
0537 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
0538     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
0539                     I_ADDA_UL_CH2, 1, 0),
0540     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN39,
0541                     I_I2S0_CH2, 1, 0),
0542 };
0543 
0544 static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
0545     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN44,
0546                     I_ADDA_UL_CH1, 1, 0),
0547 };
0548 
0549 static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
0550     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN45,
0551                     I_ADDA_UL_CH2, 1, 0),
0552 };
0553 
0554 static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
0555     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN46,
0556                     I_ADDA_UL_CH1, 1, 0),
0557     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN46,
0558                     I_DL1_CH1, 1, 0),
0559     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN46,
0560                     I_DL12_CH1, 1, 0),
0561     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN46_1,
0562                     I_DL6_CH1, 1, 0),
0563     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN46,
0564                     I_DL2_CH1, 1, 0),
0565     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN46,
0566                     I_DL3_CH1, 1, 0),
0567     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN46_1,
0568                     I_DL4_CH1, 1, 0),
0569     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN46,
0570                     I_PCM_1_CAP_CH1, 1, 0),
0571     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN46,
0572                     I_PCM_2_CAP_CH1, 1, 0),
0573 };
0574 
0575 static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
0576     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN47,
0577                     I_ADDA_UL_CH2, 1, 0),
0578     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN47,
0579                     I_DL1_CH2, 1, 0),
0580     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN47,
0581                     I_DL12_CH2, 1, 0),
0582     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN47_1,
0583                     I_DL6_CH2, 1, 0),
0584     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN47,
0585                     I_DL2_CH2, 1, 0),
0586     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN47,
0587                     I_DL3_CH2, 1, 0),
0588     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN47_1,
0589                     I_DL4_CH2, 1, 0),
0590     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN47,
0591                     I_PCM_1_CAP_CH1, 1, 0),
0592     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN47,
0593                     I_PCM_2_CAP_CH1, 1, 0),
0594 };
0595 
0596 static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
0597     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN48,
0598                     I_ADDA_UL_CH1, 1, 0),
0599 };
0600 
0601 static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
0602     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN49,
0603                     I_ADDA_UL_CH2, 1, 0),
0604 };
0605 
0606 static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
0607     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN50,
0608                     I_ADDA_UL_CH1, 1, 0),
0609 };
0610 
0611 static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
0612     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN51,
0613                     I_ADDA_UL_CH2, 1, 0),
0614 };
0615 
0616 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
0617     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN12,
0618                     I_PCM_1_CAP_CH1, 1, 0),
0619     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN12,
0620                     I_PCM_2_CAP_CH1, 1, 0),
0621 };
0622 
0623 static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {
0624     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,
0625                     I_ADDA_UL_CH1, 1, 0),
0626 };
0627 
0628 static const struct snd_kcontrol_new memif_ul_mono_3_mix[] = {
0629     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN35,
0630                     I_ADDA_UL_CH1, 1, 0),
0631 };
0632 
0633 /* TINYCONN MUX */
0634 enum {
0635     TINYCONN_CH1_MUX_I2S0 = 0x14,
0636     TINYCONN_CH2_MUX_I2S0 = 0x15,
0637     TINYCONN_CH1_MUX_I2S6 = 0x1a,
0638     TINYCONN_CH2_MUX_I2S6 = 0x1b,
0639     TINYCONN_CH1_MUX_I2S8 = 0x1c,
0640     TINYCONN_CH2_MUX_I2S8 = 0x1d,
0641     TINYCONN_MUX_NONE = 0x1f,
0642 };
0643 
0644 static const char * const tinyconn_mux_map[] = {
0645     "NONE",
0646     "I2S0_CH1",
0647     "I2S0_CH2",
0648     "I2S6_CH1",
0649     "I2S6_CH2",
0650     "I2S8_CH1",
0651     "I2S8_CH2",
0652 };
0653 
0654 static int tinyconn_mux_map_value[] = {
0655     TINYCONN_MUX_NONE,
0656     TINYCONN_CH1_MUX_I2S0,
0657     TINYCONN_CH2_MUX_I2S0,
0658     TINYCONN_CH1_MUX_I2S6,
0659     TINYCONN_CH2_MUX_I2S6,
0660     TINYCONN_CH1_MUX_I2S8,
0661     TINYCONN_CH2_MUX_I2S8,
0662 };
0663 
0664 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch1_mux_map_enum,
0665                   AFE_TINY_CONN0,
0666                   O_2_CFG_SFT,
0667                   O_2_CFG_MASK,
0668                   tinyconn_mux_map,
0669                   tinyconn_mux_map_value);
0670 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch2_mux_map_enum,
0671                   AFE_TINY_CONN0,
0672                   O_3_CFG_SFT,
0673                   O_3_CFG_MASK,
0674                   tinyconn_mux_map,
0675                   tinyconn_mux_map_value);
0676 
0677 static const struct snd_kcontrol_new ul4_tinyconn_ch1_mux_control =
0678     SOC_DAPM_ENUM("UL4_TINYCONN_CH1_MUX", ul4_tinyconn_ch1_mux_map_enum);
0679 static const struct snd_kcontrol_new ul4_tinyconn_ch2_mux_control =
0680     SOC_DAPM_ENUM("UL4_TINYCONN_CH2_MUX", ul4_tinyconn_ch2_mux_map_enum);
0681 
0682 static const struct snd_soc_dapm_widget mt8192_memif_widgets[] = {
0683     /* inter-connections */
0684     SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
0685                memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
0686     SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
0687                memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
0688     SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0,
0689                memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)),
0690     SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0,
0691                memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)),
0692 
0693     SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
0694                memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
0695     SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
0696                memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
0697 
0698     SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
0699                memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
0700     SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
0701                memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
0702 
0703     SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
0704                memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
0705     SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
0706                memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
0707     SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,
0708                &ul4_tinyconn_ch1_mux_control,
0709                ul_tinyconn_event,
0710                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
0711     SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,
0712                &ul4_tinyconn_ch2_mux_control,
0713                ul_tinyconn_event,
0714                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
0715 
0716     SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
0717                memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
0718     SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
0719                memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
0720 
0721     SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
0722                memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
0723     SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
0724                memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
0725 
0726     SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
0727                memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
0728     SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
0729                memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
0730 
0731     SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
0732                memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
0733     SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
0734                memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
0735 
0736     SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
0737                memif_ul_mono_1_mix,
0738                ARRAY_SIZE(memif_ul_mono_1_mix)),
0739 
0740     SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,
0741                memif_ul_mono_2_mix,
0742                ARRAY_SIZE(memif_ul_mono_2_mix)),
0743 
0744     SND_SOC_DAPM_MIXER("UL_MONO_3_CH1", SND_SOC_NOPM, 0, 0,
0745                memif_ul_mono_3_mix,
0746                ARRAY_SIZE(memif_ul_mono_3_mix)),
0747 
0748     SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"),
0749     SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"),
0750     SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"),
0751 };
0752 
0753 static const struct snd_soc_dapm_route mt8192_memif_routes[] = {
0754     {"UL1", NULL, "UL1_CH1"},
0755     {"UL1", NULL, "UL1_CH2"},
0756     {"UL1", NULL, "UL1_CH3"},
0757     {"UL1", NULL, "UL1_CH4"},
0758     {"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0759     {"UL1_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0760     {"UL1_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
0761     {"UL1_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0762     {"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0763     {"UL1_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
0764     {"UL1_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
0765     {"UL1_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0766     {"UL1_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0767     {"UL1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
0768     {"UL1_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0769     {"UL1_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0770     {"UL1_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
0771     {"UL1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
0772 
0773     {"UL2", NULL, "UL2_CH1"},
0774     {"UL2", NULL, "UL2_CH2"},
0775     {"UL2_CH1", "I2S0_CH1", "I2S0"},
0776     {"UL2_CH2", "I2S0_CH2", "I2S0"},
0777     {"UL2_CH1", "I2S2_CH1", "I2S2"},
0778     {"UL2_CH2", "I2S2_CH2", "I2S2"},
0779     {"UL2_CH1", "I2S6_CH1", "I2S6"},
0780     {"UL2_CH2", "I2S6_CH2", "I2S6"},
0781     {"UL2_CH1", "I2S8_CH1", "I2S8"},
0782     {"UL2_CH2", "I2S8_CH2", "I2S8"},
0783 
0784     {"UL2_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},
0785     {"UL2_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"},
0786     {"UL2_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},
0787     {"UL2_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"},
0788 
0789     {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
0790     {"UL_MONO_1_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},
0791     {"UL_MONO_1_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},
0792 
0793     {"UL_MONO_2", NULL, "UL_MONO_2_CH1"},
0794     {"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0795 
0796     {"UL_MONO_3", NULL, "UL_MONO_3_CH1"},
0797     {"UL_MONO_3_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0798 
0799     {"UL2_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"},
0800     {"UL2_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"},
0801 
0802     {"UL3", NULL, "UL3_CH1"},
0803     {"UL3", NULL, "UL3_CH2"},
0804     {"UL3_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"},
0805     {"UL3_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"},
0806 
0807     {"UL4", NULL, "UL4_CH1"},
0808     {"UL4", NULL, "UL4_CH2"},
0809     {"UL4", NULL, "UL4_TINYCONN_CH1_MUX"},
0810     {"UL4", NULL, "UL4_TINYCONN_CH2_MUX"},
0811     {"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0812     {"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0813     {"UL4_CH1", "I2S0_CH1", "I2S0"},
0814     {"UL4_CH2", "I2S0_CH2", "I2S0"},
0815     {"UL4_TINYCONN_CH1_MUX", "I2S0_CH1", "I2S0"},
0816     {"UL4_TINYCONN_CH2_MUX", "I2S0_CH2", "I2S0"},
0817 
0818     {"UL5", NULL, "UL5_CH1"},
0819     {"UL5", NULL, "UL5_CH2"},
0820     {"UL5_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0821     {"UL5_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0822 
0823     {"UL6", NULL, "UL6_CH1"},
0824     {"UL6", NULL, "UL6_CH2"},
0825 
0826     {"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0827     {"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0828     {"UL6_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},
0829     {"UL6_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"},
0830     {"UL6_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},
0831     {"UL6_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"},
0832 
0833     {"UL7", NULL, "UL7_CH1"},
0834     {"UL7", NULL, "UL7_CH2"},
0835     {"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0836     {"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0837 
0838     {"UL8", NULL, "UL8_CH1"},
0839     {"UL8", NULL, "UL8_CH2"},
0840     {"UL8_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
0841     {"UL8_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
0842 };
0843 
0844 static const struct mtk_base_memif_data memif_data[MT8192_MEMIF_NUM] = {
0845     [MT8192_MEMIF_DL1] = {
0846         .name = "DL1",
0847         .id = MT8192_MEMIF_DL1,
0848         .reg_ofs_base = AFE_DL1_BASE,
0849         .reg_ofs_cur = AFE_DL1_CUR,
0850         .reg_ofs_end = AFE_DL1_END,
0851         .reg_ofs_base_msb = AFE_DL1_BASE_MSB,
0852         .reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
0853         .reg_ofs_end_msb = AFE_DL1_END_MSB,
0854         .fs_reg = AFE_DL1_CON0,
0855         .fs_shift = DL1_MODE_SFT,
0856         .fs_maskbit = DL1_MODE_MASK,
0857         .mono_reg = AFE_DL1_CON0,
0858         .mono_shift = DL1_MONO_SFT,
0859         .enable_reg = AFE_DAC_CON0,
0860         .enable_shift = DL1_ON_SFT,
0861         .hd_reg = AFE_DL1_CON0,
0862         .hd_shift = DL1_HD_MODE_SFT,
0863         .hd_align_reg = AFE_DL1_CON0,
0864         .hd_align_mshift = DL1_HALIGN_SFT,
0865         .pbuf_reg = AFE_DL1_CON0,
0866         .pbuf_shift = DL1_PBUF_SIZE_SFT,
0867         .minlen_reg = AFE_DL1_CON0,
0868         .minlen_shift = DL1_MINLEN_SFT,
0869     },
0870     [MT8192_MEMIF_DL12] = {
0871         .name = "DL12",
0872         .id = MT8192_MEMIF_DL12,
0873         .reg_ofs_base = AFE_DL12_BASE,
0874         .reg_ofs_cur = AFE_DL12_CUR,
0875         .reg_ofs_end = AFE_DL12_END,
0876         .reg_ofs_base_msb = AFE_DL12_BASE_MSB,
0877         .reg_ofs_cur_msb = AFE_DL12_CUR_MSB,
0878         .reg_ofs_end_msb = AFE_DL12_END_MSB,
0879         .fs_reg = AFE_DL12_CON0,
0880         .fs_shift = DL12_MODE_SFT,
0881         .fs_maskbit = DL12_MODE_MASK,
0882         .mono_reg = AFE_DL12_CON0,
0883         .mono_shift = DL12_MONO_SFT,
0884         .enable_reg = AFE_DAC_CON0,
0885         .enable_shift = DL12_ON_SFT,
0886         .hd_reg = AFE_DL12_CON0,
0887         .hd_shift = DL12_HD_MODE_SFT,
0888         .hd_align_reg = AFE_DL12_CON0,
0889         .hd_align_mshift = DL12_HALIGN_SFT,
0890         .pbuf_reg = AFE_DL12_CON0,
0891         .pbuf_shift = DL12_PBUF_SIZE_SFT,
0892         .minlen_reg = AFE_DL12_CON0,
0893         .minlen_shift = DL12_MINLEN_SFT,
0894     },
0895     [MT8192_MEMIF_DL2] = {
0896         .name = "DL2",
0897         .id = MT8192_MEMIF_DL2,
0898         .reg_ofs_base = AFE_DL2_BASE,
0899         .reg_ofs_cur = AFE_DL2_CUR,
0900         .reg_ofs_end = AFE_DL2_END,
0901         .reg_ofs_base_msb = AFE_DL2_BASE_MSB,
0902         .reg_ofs_cur_msb = AFE_DL2_CUR_MSB,
0903         .reg_ofs_end_msb = AFE_DL2_END_MSB,
0904         .fs_reg = AFE_DL2_CON0,
0905         .fs_shift = DL2_MODE_SFT,
0906         .fs_maskbit = DL2_MODE_MASK,
0907         .mono_reg = AFE_DL2_CON0,
0908         .mono_shift = DL2_MONO_SFT,
0909         .enable_reg = AFE_DAC_CON0,
0910         .enable_shift = DL2_ON_SFT,
0911         .hd_reg = AFE_DL2_CON0,
0912         .hd_shift = DL2_HD_MODE_SFT,
0913         .hd_align_reg = AFE_DL2_CON0,
0914         .hd_align_mshift = DL2_HALIGN_SFT,
0915         .pbuf_reg = AFE_DL2_CON0,
0916         .pbuf_shift = DL2_PBUF_SIZE_SFT,
0917         .minlen_reg = AFE_DL2_CON0,
0918         .minlen_shift = DL2_MINLEN_SFT,
0919     },
0920     [MT8192_MEMIF_DL3] = {
0921         .name = "DL3",
0922         .id = MT8192_MEMIF_DL3,
0923         .reg_ofs_base = AFE_DL3_BASE,
0924         .reg_ofs_cur = AFE_DL3_CUR,
0925         .reg_ofs_end = AFE_DL3_END,
0926         .reg_ofs_base_msb = AFE_DL3_BASE_MSB,
0927         .reg_ofs_cur_msb = AFE_DL3_CUR_MSB,
0928         .reg_ofs_end_msb = AFE_DL3_END_MSB,
0929         .fs_reg = AFE_DL3_CON0,
0930         .fs_shift = DL3_MODE_SFT,
0931         .fs_maskbit = DL3_MODE_MASK,
0932         .mono_reg = AFE_DL3_CON0,
0933         .mono_shift = DL3_MONO_SFT,
0934         .enable_reg = AFE_DAC_CON0,
0935         .enable_shift = DL3_ON_SFT,
0936         .hd_reg = AFE_DL3_CON0,
0937         .hd_shift = DL3_HD_MODE_SFT,
0938         .hd_align_reg = AFE_DL3_CON0,
0939         .hd_align_mshift = DL3_HALIGN_SFT,
0940         .pbuf_reg = AFE_DL3_CON0,
0941         .pbuf_shift = DL3_PBUF_SIZE_SFT,
0942         .minlen_reg = AFE_DL3_CON0,
0943         .minlen_shift = DL3_MINLEN_SFT,
0944     },
0945     [MT8192_MEMIF_DL4] = {
0946         .name = "DL4",
0947         .id = MT8192_MEMIF_DL4,
0948         .reg_ofs_base = AFE_DL4_BASE,
0949         .reg_ofs_cur = AFE_DL4_CUR,
0950         .reg_ofs_end = AFE_DL4_END,
0951         .reg_ofs_base_msb = AFE_DL4_BASE_MSB,
0952         .reg_ofs_cur_msb = AFE_DL4_CUR_MSB,
0953         .reg_ofs_end_msb = AFE_DL4_END_MSB,
0954         .fs_reg = AFE_DL4_CON0,
0955         .fs_shift = DL4_MODE_SFT,
0956         .fs_maskbit = DL4_MODE_MASK,
0957         .mono_reg = AFE_DL4_CON0,
0958         .mono_shift = DL4_MONO_SFT,
0959         .enable_reg = AFE_DAC_CON0,
0960         .enable_shift = DL4_ON_SFT,
0961         .hd_reg = AFE_DL4_CON0,
0962         .hd_shift = DL4_HD_MODE_SFT,
0963         .hd_align_reg = AFE_DL4_CON0,
0964         .hd_align_mshift = DL4_HALIGN_SFT,
0965         .pbuf_reg = AFE_DL4_CON0,
0966         .pbuf_shift = DL4_PBUF_SIZE_SFT,
0967         .minlen_reg = AFE_DL4_CON0,
0968         .minlen_shift = DL4_MINLEN_SFT,
0969     },
0970     [MT8192_MEMIF_DL5] = {
0971         .name = "DL5",
0972         .id = MT8192_MEMIF_DL5,
0973         .reg_ofs_base = AFE_DL5_BASE,
0974         .reg_ofs_cur = AFE_DL5_CUR,
0975         .reg_ofs_end = AFE_DL5_END,
0976         .reg_ofs_base_msb = AFE_DL5_BASE_MSB,
0977         .reg_ofs_cur_msb = AFE_DL5_CUR_MSB,
0978         .reg_ofs_end_msb = AFE_DL5_END_MSB,
0979         .fs_reg = AFE_DL5_CON0,
0980         .fs_shift = DL5_MODE_SFT,
0981         .fs_maskbit = DL5_MODE_MASK,
0982         .mono_reg = AFE_DL5_CON0,
0983         .mono_shift = DL5_MONO_SFT,
0984         .enable_reg = AFE_DAC_CON0,
0985         .enable_shift = DL5_ON_SFT,
0986         .hd_reg = AFE_DL5_CON0,
0987         .hd_shift = DL5_HD_MODE_SFT,
0988         .hd_align_reg = AFE_DL5_CON0,
0989         .hd_align_mshift = DL5_HALIGN_SFT,
0990         .pbuf_reg = AFE_DL5_CON0,
0991         .pbuf_shift = DL5_PBUF_SIZE_SFT,
0992         .minlen_reg = AFE_DL5_CON0,
0993         .minlen_shift = DL5_MINLEN_SFT,
0994     },
0995     [MT8192_MEMIF_DL6] = {
0996         .name = "DL6",
0997         .id = MT8192_MEMIF_DL6,
0998         .reg_ofs_base = AFE_DL6_BASE,
0999         .reg_ofs_cur = AFE_DL6_CUR,
1000         .reg_ofs_end = AFE_DL6_END,
1001         .reg_ofs_base_msb = AFE_DL6_BASE_MSB,
1002         .reg_ofs_cur_msb = AFE_DL6_CUR_MSB,
1003         .reg_ofs_end_msb = AFE_DL6_END_MSB,
1004         .fs_reg = AFE_DL6_CON0,
1005         .fs_shift = DL6_MODE_SFT,
1006         .fs_maskbit = DL6_MODE_MASK,
1007         .mono_reg = AFE_DL6_CON0,
1008         .mono_shift = DL6_MONO_SFT,
1009         .enable_reg = AFE_DAC_CON0,
1010         .enable_shift = DL6_ON_SFT,
1011         .hd_reg = AFE_DL6_CON0,
1012         .hd_shift = DL6_HD_MODE_SFT,
1013         .hd_align_reg = AFE_DL6_CON0,
1014         .hd_align_mshift = DL6_HALIGN_SFT,
1015         .pbuf_reg = AFE_DL6_CON0,
1016         .pbuf_shift = DL6_PBUF_SIZE_SFT,
1017         .minlen_reg = AFE_DL6_CON0,
1018         .minlen_shift = DL6_MINLEN_SFT,
1019     },
1020     [MT8192_MEMIF_DL7] = {
1021         .name = "DL7",
1022         .id = MT8192_MEMIF_DL7,
1023         .reg_ofs_base = AFE_DL7_BASE,
1024         .reg_ofs_cur = AFE_DL7_CUR,
1025         .reg_ofs_end = AFE_DL7_END,
1026         .reg_ofs_base_msb = AFE_DL7_BASE_MSB,
1027         .reg_ofs_cur_msb = AFE_DL7_CUR_MSB,
1028         .reg_ofs_end_msb = AFE_DL7_END_MSB,
1029         .fs_reg = AFE_DL7_CON0,
1030         .fs_shift = DL7_MODE_SFT,
1031         .fs_maskbit = DL7_MODE_MASK,
1032         .mono_reg = AFE_DL7_CON0,
1033         .mono_shift = DL7_MONO_SFT,
1034         .enable_reg = AFE_DAC_CON0,
1035         .enable_shift = DL7_ON_SFT,
1036         .hd_reg = AFE_DL7_CON0,
1037         .hd_shift = DL7_HD_MODE_SFT,
1038         .hd_align_reg = AFE_DL7_CON0,
1039         .hd_align_mshift = DL7_HALIGN_SFT,
1040         .pbuf_reg = AFE_DL7_CON0,
1041         .pbuf_shift = DL7_PBUF_SIZE_SFT,
1042         .minlen_reg = AFE_DL7_CON0,
1043         .minlen_shift = DL7_MINLEN_SFT,
1044     },
1045     [MT8192_MEMIF_DL8] = {
1046         .name = "DL8",
1047         .id = MT8192_MEMIF_DL8,
1048         .reg_ofs_base = AFE_DL8_BASE,
1049         .reg_ofs_cur = AFE_DL8_CUR,
1050         .reg_ofs_end = AFE_DL8_END,
1051         .reg_ofs_base_msb = AFE_DL8_BASE_MSB,
1052         .reg_ofs_cur_msb = AFE_DL8_CUR_MSB,
1053         .reg_ofs_end_msb = AFE_DL8_END_MSB,
1054         .fs_reg = AFE_DL8_CON0,
1055         .fs_shift = DL8_MODE_SFT,
1056         .fs_maskbit = DL8_MODE_MASK,
1057         .mono_reg = AFE_DL8_CON0,
1058         .mono_shift = DL8_MONO_SFT,
1059         .enable_reg = AFE_DAC_CON0,
1060         .enable_shift = DL8_ON_SFT,
1061         .hd_reg = AFE_DL8_CON0,
1062         .hd_shift = DL8_HD_MODE_SFT,
1063         .hd_align_reg = AFE_DL8_CON0,
1064         .hd_align_mshift = DL8_HALIGN_SFT,
1065         .pbuf_reg = AFE_DL8_CON0,
1066         .pbuf_shift = DL8_PBUF_SIZE_SFT,
1067         .minlen_reg = AFE_DL8_CON0,
1068         .minlen_shift = DL8_MINLEN_SFT,
1069     },
1070     [MT8192_MEMIF_DL9] = {
1071         .name = "DL9",
1072         .id = MT8192_MEMIF_DL9,
1073         .reg_ofs_base = AFE_DL9_BASE,
1074         .reg_ofs_cur = AFE_DL9_CUR,
1075         .reg_ofs_end = AFE_DL9_END,
1076         .reg_ofs_base_msb = AFE_DL9_BASE_MSB,
1077         .reg_ofs_cur_msb = AFE_DL9_CUR_MSB,
1078         .reg_ofs_end_msb = AFE_DL9_END_MSB,
1079         .fs_reg = AFE_DL9_CON0,
1080         .fs_shift = DL9_MODE_SFT,
1081         .fs_maskbit = DL9_MODE_MASK,
1082         .mono_reg = AFE_DL9_CON0,
1083         .mono_shift = DL9_MONO_SFT,
1084         .enable_reg = AFE_DAC_CON0,
1085         .enable_shift = DL9_ON_SFT,
1086         .hd_reg = AFE_DL9_CON0,
1087         .hd_shift = DL9_HD_MODE_SFT,
1088         .hd_align_reg = AFE_DL9_CON0,
1089         .hd_align_mshift = DL9_HALIGN_SFT,
1090         .pbuf_reg = AFE_DL9_CON0,
1091         .pbuf_shift = DL9_PBUF_SIZE_SFT,
1092         .minlen_reg = AFE_DL9_CON0,
1093         .minlen_shift = DL9_MINLEN_SFT,
1094     },
1095     [MT8192_MEMIF_DAI] = {
1096         .name = "DAI",
1097         .id = MT8192_MEMIF_DAI,
1098         .reg_ofs_base = AFE_DAI_BASE,
1099         .reg_ofs_cur = AFE_DAI_CUR,
1100         .reg_ofs_end = AFE_DAI_END,
1101         .reg_ofs_base_msb = AFE_DAI_BASE_MSB,
1102         .reg_ofs_cur_msb = AFE_DAI_CUR_MSB,
1103         .reg_ofs_end_msb = AFE_DAI_END_MSB,
1104         .fs_reg = AFE_DAI_CON0,
1105         .fs_shift = DAI_MODE_SFT,
1106         .fs_maskbit = DAI_MODE_MASK,
1107         .mono_reg = AFE_DAI_CON0,
1108         .mono_shift = DAI_DUPLICATE_WR_SFT,
1109         .mono_invert = 1,
1110         .enable_reg = AFE_DAC_CON0,
1111         .enable_shift = DAI_ON_SFT,
1112         .hd_reg = AFE_DAI_CON0,
1113         .hd_shift = DAI_HD_MODE_SFT,
1114         .hd_align_reg = AFE_DAI_CON0,
1115         .hd_align_mshift = DAI_HALIGN_SFT,
1116     },
1117     [MT8192_MEMIF_MOD_DAI] = {
1118         .name = "MOD_DAI",
1119         .id = MT8192_MEMIF_MOD_DAI,
1120         .reg_ofs_base = AFE_MOD_DAI_BASE,
1121         .reg_ofs_cur = AFE_MOD_DAI_CUR,
1122         .reg_ofs_end = AFE_MOD_DAI_END,
1123         .reg_ofs_base_msb = AFE_MOD_DAI_BASE_MSB,
1124         .reg_ofs_cur_msb = AFE_MOD_DAI_CUR_MSB,
1125         .reg_ofs_end_msb = AFE_MOD_DAI_END_MSB,
1126         .fs_reg = AFE_MOD_DAI_CON0,
1127         .fs_shift = MOD_DAI_MODE_SFT,
1128         .fs_maskbit = MOD_DAI_MODE_MASK,
1129         .mono_reg = AFE_MOD_DAI_CON0,
1130         .mono_shift = MOD_DAI_DUPLICATE_WR_SFT,
1131         .mono_invert = 1,
1132         .enable_reg = AFE_DAC_CON0,
1133         .enable_shift = MOD_DAI_ON_SFT,
1134         .hd_reg = AFE_MOD_DAI_CON0,
1135         .hd_shift = MOD_DAI_HD_MODE_SFT,
1136         .hd_align_reg = AFE_MOD_DAI_CON0,
1137         .hd_align_mshift = MOD_DAI_HALIGN_SFT,
1138     },
1139     [MT8192_MEMIF_DAI2] = {
1140         .name = "DAI2",
1141         .id = MT8192_MEMIF_DAI2,
1142         .reg_ofs_base = AFE_DAI2_BASE,
1143         .reg_ofs_cur = AFE_DAI2_CUR,
1144         .reg_ofs_end = AFE_DAI2_END,
1145         .reg_ofs_base_msb = AFE_DAI2_BASE_MSB,
1146         .reg_ofs_cur_msb = AFE_DAI2_CUR_MSB,
1147         .reg_ofs_end_msb = AFE_DAI2_END_MSB,
1148         .fs_reg = AFE_DAI2_CON0,
1149         .fs_shift = DAI2_MODE_SFT,
1150         .fs_maskbit = DAI2_MODE_MASK,
1151         .mono_reg = AFE_DAI2_CON0,
1152         .mono_shift = DAI2_DUPLICATE_WR_SFT,
1153         .mono_invert = 1,
1154         .enable_reg = AFE_DAC_CON0,
1155         .enable_shift = DAI2_ON_SFT,
1156         .hd_reg = AFE_DAI2_CON0,
1157         .hd_shift = DAI2_HD_MODE_SFT,
1158         .hd_align_reg = AFE_DAI2_CON0,
1159         .hd_align_mshift = DAI2_HALIGN_SFT,
1160     },
1161     [MT8192_MEMIF_VUL12] = {
1162         .name = "VUL12",
1163         .id = MT8192_MEMIF_VUL12,
1164         .reg_ofs_base = AFE_VUL12_BASE,
1165         .reg_ofs_cur = AFE_VUL12_CUR,
1166         .reg_ofs_end = AFE_VUL12_END,
1167         .reg_ofs_base_msb = AFE_VUL12_BASE_MSB,
1168         .reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,
1169         .reg_ofs_end_msb = AFE_VUL12_END_MSB,
1170         .fs_reg = AFE_VUL12_CON0,
1171         .fs_shift = VUL12_MODE_SFT,
1172         .fs_maskbit = VUL12_MODE_MASK,
1173         .mono_reg = AFE_VUL12_CON0,
1174         .mono_shift = VUL12_MONO_SFT,
1175         .quad_ch_reg = AFE_VUL12_CON0,
1176         .quad_ch_shift = VUL12_4CH_EN_SFT,
1177         .quad_ch_mask = VUL12_4CH_EN_MASK,
1178         .enable_reg = AFE_DAC_CON0,
1179         .enable_shift = VUL12_ON_SFT,
1180         .hd_reg = AFE_VUL12_CON0,
1181         .hd_shift = VUL12_HD_MODE_SFT,
1182         .hd_align_reg = AFE_VUL12_CON0,
1183         .hd_align_mshift = VUL12_HALIGN_SFT,
1184     },
1185     [MT8192_MEMIF_VUL2] = {
1186         .name = "VUL2",
1187         .id = MT8192_MEMIF_VUL2,
1188         .reg_ofs_base = AFE_VUL2_BASE,
1189         .reg_ofs_cur = AFE_VUL2_CUR,
1190         .reg_ofs_end = AFE_VUL2_END,
1191         .reg_ofs_base_msb = AFE_VUL2_BASE_MSB,
1192         .reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,
1193         .reg_ofs_end_msb = AFE_VUL2_END_MSB,
1194         .fs_reg = AFE_VUL2_CON0,
1195         .fs_shift = VUL2_MODE_SFT,
1196         .fs_maskbit = VUL2_MODE_MASK,
1197         .mono_reg = AFE_VUL2_CON0,
1198         .mono_shift = VUL2_MONO_SFT,
1199         .enable_reg = AFE_DAC_CON0,
1200         .enable_shift = VUL2_ON_SFT,
1201         .hd_reg = AFE_VUL2_CON0,
1202         .hd_shift = VUL2_HD_MODE_SFT,
1203         .hd_align_reg = AFE_VUL2_CON0,
1204         .hd_align_mshift = VUL2_HALIGN_SFT,
1205     },
1206     [MT8192_MEMIF_AWB] = {
1207         .name = "AWB",
1208         .id = MT8192_MEMIF_AWB,
1209         .reg_ofs_base = AFE_AWB_BASE,
1210         .reg_ofs_cur = AFE_AWB_CUR,
1211         .reg_ofs_end = AFE_AWB_END,
1212         .reg_ofs_base_msb = AFE_AWB_BASE_MSB,
1213         .reg_ofs_cur_msb = AFE_AWB_CUR_MSB,
1214         .reg_ofs_end_msb = AFE_AWB_END_MSB,
1215         .fs_reg = AFE_AWB_CON0,
1216         .fs_shift = AWB_MODE_SFT,
1217         .fs_maskbit = AWB_MODE_MASK,
1218         .mono_reg = AFE_AWB_CON0,
1219         .mono_shift = AWB_MONO_SFT,
1220         .enable_reg = AFE_DAC_CON0,
1221         .enable_shift = AWB_ON_SFT,
1222         .hd_reg = AFE_AWB_CON0,
1223         .hd_shift = AWB_HD_MODE_SFT,
1224         .hd_align_reg = AFE_AWB_CON0,
1225         .hd_align_mshift = AWB_HALIGN_SFT,
1226     },
1227     [MT8192_MEMIF_AWB2] = {
1228         .name = "AWB2",
1229         .id = MT8192_MEMIF_AWB2,
1230         .reg_ofs_base = AFE_AWB2_BASE,
1231         .reg_ofs_cur = AFE_AWB2_CUR,
1232         .reg_ofs_end = AFE_AWB2_END,
1233         .reg_ofs_base_msb = AFE_AWB2_BASE_MSB,
1234         .reg_ofs_cur_msb = AFE_AWB2_CUR_MSB,
1235         .reg_ofs_end_msb = AFE_AWB2_END_MSB,
1236         .fs_reg = AFE_AWB2_CON0,
1237         .fs_shift = AWB2_MODE_SFT,
1238         .fs_maskbit = AWB2_MODE_MASK,
1239         .mono_reg = AFE_AWB2_CON0,
1240         .mono_shift = AWB2_MONO_SFT,
1241         .enable_reg = AFE_DAC_CON0,
1242         .enable_shift = AWB2_ON_SFT,
1243         .hd_reg = AFE_AWB2_CON0,
1244         .hd_shift = AWB2_HD_MODE_SFT,
1245         .hd_align_reg = AFE_AWB2_CON0,
1246         .hd_align_mshift = AWB2_HALIGN_SFT,
1247     },
1248     [MT8192_MEMIF_VUL3] = {
1249         .name = "VUL3",
1250         .id = MT8192_MEMIF_VUL3,
1251         .reg_ofs_base = AFE_VUL3_BASE,
1252         .reg_ofs_cur = AFE_VUL3_CUR,
1253         .reg_ofs_end = AFE_VUL3_END,
1254         .reg_ofs_base_msb = AFE_VUL3_BASE_MSB,
1255         .reg_ofs_cur_msb = AFE_VUL3_CUR_MSB,
1256         .reg_ofs_end_msb = AFE_VUL3_END_MSB,
1257         .fs_reg = AFE_VUL3_CON0,
1258         .fs_shift = VUL3_MODE_SFT,
1259         .fs_maskbit = VUL3_MODE_MASK,
1260         .mono_reg = AFE_VUL3_CON0,
1261         .mono_shift = VUL3_MONO_SFT,
1262         .enable_reg = AFE_DAC_CON0,
1263         .enable_shift = VUL3_ON_SFT,
1264         .hd_reg = AFE_VUL3_CON0,
1265         .hd_shift = VUL3_HD_MODE_SFT,
1266         .hd_align_reg = AFE_VUL3_CON0,
1267         .hd_align_mshift = VUL3_HALIGN_SFT,
1268     },
1269     [MT8192_MEMIF_VUL4] = {
1270         .name = "VUL4",
1271         .id = MT8192_MEMIF_VUL4,
1272         .reg_ofs_base = AFE_VUL4_BASE,
1273         .reg_ofs_cur = AFE_VUL4_CUR,
1274         .reg_ofs_end = AFE_VUL4_END,
1275         .reg_ofs_base_msb = AFE_VUL4_BASE_MSB,
1276         .reg_ofs_cur_msb = AFE_VUL4_CUR_MSB,
1277         .reg_ofs_end_msb = AFE_VUL4_END_MSB,
1278         .fs_reg = AFE_VUL4_CON0,
1279         .fs_shift = VUL4_MODE_SFT,
1280         .fs_maskbit = VUL4_MODE_MASK,
1281         .mono_reg = AFE_VUL4_CON0,
1282         .mono_shift = VUL4_MONO_SFT,
1283         .enable_reg = AFE_DAC_CON0,
1284         .enable_shift = VUL4_ON_SFT,
1285         .hd_reg = AFE_VUL4_CON0,
1286         .hd_shift = VUL4_HD_MODE_SFT,
1287         .hd_align_reg = AFE_VUL4_CON0,
1288         .hd_align_mshift = VUL4_HALIGN_SFT,
1289     },
1290     [MT8192_MEMIF_VUL5] = {
1291         .name = "VUL5",
1292         .id = MT8192_MEMIF_VUL5,
1293         .reg_ofs_base = AFE_VUL5_BASE,
1294         .reg_ofs_cur = AFE_VUL5_CUR,
1295         .reg_ofs_end = AFE_VUL5_END,
1296         .reg_ofs_base_msb = AFE_VUL5_BASE_MSB,
1297         .reg_ofs_cur_msb = AFE_VUL5_CUR_MSB,
1298         .reg_ofs_end_msb = AFE_VUL5_END_MSB,
1299         .fs_reg = AFE_VUL5_CON0,
1300         .fs_shift = VUL5_MODE_SFT,
1301         .fs_maskbit = VUL5_MODE_MASK,
1302         .mono_reg = AFE_VUL5_CON0,
1303         .mono_shift = VUL5_MONO_SFT,
1304         .enable_reg = AFE_DAC_CON0,
1305         .enable_shift = VUL5_ON_SFT,
1306         .hd_reg = AFE_VUL5_CON0,
1307         .hd_shift = VUL5_HD_MODE_SFT,
1308         .hd_align_reg = AFE_VUL5_CON0,
1309         .hd_align_mshift = VUL5_HALIGN_SFT,
1310     },
1311     [MT8192_MEMIF_VUL6] = {
1312         .name = "VUL6",
1313         .id = MT8192_MEMIF_VUL6,
1314         .reg_ofs_base = AFE_VUL6_BASE,
1315         .reg_ofs_cur = AFE_VUL6_CUR,
1316         .reg_ofs_end = AFE_VUL6_END,
1317         .reg_ofs_base_msb = AFE_VUL6_BASE_MSB,
1318         .reg_ofs_cur_msb = AFE_VUL6_CUR_MSB,
1319         .reg_ofs_end_msb = AFE_VUL6_END_MSB,
1320         .fs_reg = AFE_VUL6_CON0,
1321         .fs_shift = VUL6_MODE_SFT,
1322         .fs_maskbit = VUL6_MODE_MASK,
1323         .mono_reg = AFE_VUL6_CON0,
1324         .mono_shift = VUL6_MONO_SFT,
1325         .enable_reg = AFE_DAC_CON0,
1326         .enable_shift = VUL6_ON_SFT,
1327         .hd_reg = AFE_VUL6_CON0,
1328         .hd_shift = VUL6_HD_MODE_SFT,
1329         .hd_align_reg = AFE_VUL6_CON0,
1330         .hd_align_mshift = VUL6_HALIGN_SFT,
1331     },
1332     [MT8192_MEMIF_HDMI] = {
1333         .name = "HDMI",
1334         .id = MT8192_MEMIF_HDMI,
1335         .reg_ofs_base = AFE_HDMI_OUT_BASE,
1336         .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1337         .reg_ofs_end = AFE_HDMI_OUT_END,
1338         .reg_ofs_base_msb = AFE_HDMI_OUT_BASE_MSB,
1339         .reg_ofs_cur_msb = AFE_HDMI_OUT_CUR_MSB,
1340         .reg_ofs_end_msb = AFE_HDMI_OUT_END_MSB,
1341         .fs_reg = -1,
1342         .fs_shift = -1,
1343         .fs_maskbit = -1,
1344         .mono_reg = -1,
1345         .mono_shift = -1,
1346         .enable_reg = AFE_DAC_CON0,
1347         .enable_shift = HDMI_OUT_ON_SFT,
1348         .hd_reg = AFE_HDMI_OUT_CON0,
1349         .hd_shift = HDMI_OUT_HD_MODE_SFT,
1350         .hd_align_reg = AFE_HDMI_OUT_CON0,
1351         .hd_align_mshift = HDMI_OUT_HALIGN_SFT,
1352         .pbuf_reg = AFE_HDMI_OUT_CON0,
1353         .minlen_reg = AFE_HDMI_OUT_CON0,
1354         .minlen_shift = HDMI_OUT_MINLEN_SFT,
1355     },
1356 };
1357 
1358 static const struct mtk_base_irq_data irq_data[MT8192_IRQ_NUM] = {
1359     [MT8192_IRQ_0] = {
1360         .id = MT8192_IRQ_0,
1361         .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
1362         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1363         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1364         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1365         .irq_fs_shift = IRQ0_MCU_MODE_SFT,
1366         .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
1367         .irq_en_reg = AFE_IRQ_MCU_CON0,
1368         .irq_en_shift = IRQ0_MCU_ON_SFT,
1369         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1370         .irq_clr_shift = IRQ0_MCU_CLR_SFT,
1371     },
1372     [MT8192_IRQ_1] = {
1373         .id = MT8192_IRQ_1,
1374         .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
1375         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1376         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1377         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1378         .irq_fs_shift = IRQ1_MCU_MODE_SFT,
1379         .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
1380         .irq_en_reg = AFE_IRQ_MCU_CON0,
1381         .irq_en_shift = IRQ1_MCU_ON_SFT,
1382         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1383         .irq_clr_shift = IRQ1_MCU_CLR_SFT,
1384     },
1385     [MT8192_IRQ_2] = {
1386         .id = MT8192_IRQ_2,
1387         .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
1388         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1389         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1390         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1391         .irq_fs_shift = IRQ2_MCU_MODE_SFT,
1392         .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
1393         .irq_en_reg = AFE_IRQ_MCU_CON0,
1394         .irq_en_shift = IRQ2_MCU_ON_SFT,
1395         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1396         .irq_clr_shift = IRQ2_MCU_CLR_SFT,
1397     },
1398     [MT8192_IRQ_3] = {
1399         .id = MT8192_IRQ_3,
1400         .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
1401         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1402         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1403         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1404         .irq_fs_shift = IRQ3_MCU_MODE_SFT,
1405         .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
1406         .irq_en_reg = AFE_IRQ_MCU_CON0,
1407         .irq_en_shift = IRQ3_MCU_ON_SFT,
1408         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1409         .irq_clr_shift = IRQ3_MCU_CLR_SFT,
1410     },
1411     [MT8192_IRQ_4] = {
1412         .id = MT8192_IRQ_4,
1413         .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
1414         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1415         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1416         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1417         .irq_fs_shift = IRQ4_MCU_MODE_SFT,
1418         .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
1419         .irq_en_reg = AFE_IRQ_MCU_CON0,
1420         .irq_en_shift = IRQ4_MCU_ON_SFT,
1421         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1422         .irq_clr_shift = IRQ4_MCU_CLR_SFT,
1423     },
1424     [MT8192_IRQ_5] = {
1425         .id = MT8192_IRQ_5,
1426         .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
1427         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1428         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1429         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1430         .irq_fs_shift = IRQ5_MCU_MODE_SFT,
1431         .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
1432         .irq_en_reg = AFE_IRQ_MCU_CON0,
1433         .irq_en_shift = IRQ5_MCU_ON_SFT,
1434         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1435         .irq_clr_shift = IRQ5_MCU_CLR_SFT,
1436     },
1437     [MT8192_IRQ_6] = {
1438         .id = MT8192_IRQ_6,
1439         .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
1440         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1441         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1442         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1443         .irq_fs_shift = IRQ6_MCU_MODE_SFT,
1444         .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
1445         .irq_en_reg = AFE_IRQ_MCU_CON0,
1446         .irq_en_shift = IRQ6_MCU_ON_SFT,
1447         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1448         .irq_clr_shift = IRQ6_MCU_CLR_SFT,
1449     },
1450     [MT8192_IRQ_7] = {
1451         .id = MT8192_IRQ_7,
1452         .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
1453         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1454         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1455         .irq_fs_reg = AFE_IRQ_MCU_CON1,
1456         .irq_fs_shift = IRQ7_MCU_MODE_SFT,
1457         .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
1458         .irq_en_reg = AFE_IRQ_MCU_CON0,
1459         .irq_en_shift = IRQ7_MCU_ON_SFT,
1460         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1461         .irq_clr_shift = IRQ7_MCU_CLR_SFT,
1462     },
1463     [MT8192_IRQ_8] = {
1464         .id = MT8192_IRQ_8,
1465         .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
1466         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1467         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1468         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1469         .irq_fs_shift = IRQ8_MCU_MODE_SFT,
1470         .irq_fs_maskbit = IRQ8_MCU_MODE_MASK,
1471         .irq_en_reg = AFE_IRQ_MCU_CON0,
1472         .irq_en_shift = IRQ8_MCU_ON_SFT,
1473         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1474         .irq_clr_shift = IRQ8_MCU_CLR_SFT,
1475     },
1476     [MT8192_IRQ_9] = {
1477         .id = MT8192_IRQ_9,
1478         .irq_cnt_reg = AFE_IRQ_MCU_CNT9,
1479         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1480         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1481         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1482         .irq_fs_shift = IRQ9_MCU_MODE_SFT,
1483         .irq_fs_maskbit = IRQ9_MCU_MODE_MASK,
1484         .irq_en_reg = AFE_IRQ_MCU_CON0,
1485         .irq_en_shift = IRQ9_MCU_ON_SFT,
1486         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1487         .irq_clr_shift = IRQ9_MCU_CLR_SFT,
1488     },
1489     [MT8192_IRQ_10] = {
1490         .id = MT8192_IRQ_10,
1491         .irq_cnt_reg = AFE_IRQ_MCU_CNT10,
1492         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1493         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1494         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1495         .irq_fs_shift = IRQ10_MCU_MODE_SFT,
1496         .irq_fs_maskbit = IRQ10_MCU_MODE_MASK,
1497         .irq_en_reg = AFE_IRQ_MCU_CON0,
1498         .irq_en_shift = IRQ10_MCU_ON_SFT,
1499         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1500         .irq_clr_shift = IRQ10_MCU_CLR_SFT,
1501     },
1502     [MT8192_IRQ_11] = {
1503         .id = MT8192_IRQ_11,
1504         .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
1505         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1506         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1507         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1508         .irq_fs_shift = IRQ11_MCU_MODE_SFT,
1509         .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
1510         .irq_en_reg = AFE_IRQ_MCU_CON0,
1511         .irq_en_shift = IRQ11_MCU_ON_SFT,
1512         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1513         .irq_clr_shift = IRQ11_MCU_CLR_SFT,
1514     },
1515     [MT8192_IRQ_12] = {
1516         .id = MT8192_IRQ_12,
1517         .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
1518         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1519         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1520         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1521         .irq_fs_shift = IRQ12_MCU_MODE_SFT,
1522         .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
1523         .irq_en_reg = AFE_IRQ_MCU_CON0,
1524         .irq_en_shift = IRQ12_MCU_ON_SFT,
1525         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1526         .irq_clr_shift = IRQ12_MCU_CLR_SFT,
1527     },
1528     [MT8192_IRQ_13] = {
1529         .id = MT8192_IRQ_13,
1530         .irq_cnt_reg = AFE_IRQ_MCU_CNT13,
1531         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1532         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1533         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1534         .irq_fs_shift = IRQ13_MCU_MODE_SFT,
1535         .irq_fs_maskbit = IRQ13_MCU_MODE_MASK,
1536         .irq_en_reg = AFE_IRQ_MCU_CON0,
1537         .irq_en_shift = IRQ13_MCU_ON_SFT,
1538         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1539         .irq_clr_shift = IRQ13_MCU_CLR_SFT,
1540     },
1541     [MT8192_IRQ_14] = {
1542         .id = MT8192_IRQ_14,
1543         .irq_cnt_reg = AFE_IRQ_MCU_CNT14,
1544         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1545         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1546         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1547         .irq_fs_shift = IRQ14_MCU_MODE_SFT,
1548         .irq_fs_maskbit = IRQ14_MCU_MODE_MASK,
1549         .irq_en_reg = AFE_IRQ_MCU_CON0,
1550         .irq_en_shift = IRQ14_MCU_ON_SFT,
1551         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1552         .irq_clr_shift = IRQ14_MCU_CLR_SFT,
1553     },
1554     [MT8192_IRQ_15] = {
1555         .id = MT8192_IRQ_15,
1556         .irq_cnt_reg = AFE_IRQ_MCU_CNT15,
1557         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1558         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1559         .irq_fs_reg = AFE_IRQ_MCU_CON2,
1560         .irq_fs_shift = IRQ15_MCU_MODE_SFT,
1561         .irq_fs_maskbit = IRQ15_MCU_MODE_MASK,
1562         .irq_en_reg = AFE_IRQ_MCU_CON0,
1563         .irq_en_shift = IRQ15_MCU_ON_SFT,
1564         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1565         .irq_clr_shift = IRQ15_MCU_CLR_SFT,
1566     },
1567     [MT8192_IRQ_16] = {
1568         .id = MT8192_IRQ_16,
1569         .irq_cnt_reg = AFE_IRQ_MCU_CNT16,
1570         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1571         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1572         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1573         .irq_fs_shift = IRQ16_MCU_MODE_SFT,
1574         .irq_fs_maskbit = IRQ16_MCU_MODE_MASK,
1575         .irq_en_reg = AFE_IRQ_MCU_CON0,
1576         .irq_en_shift = IRQ16_MCU_ON_SFT,
1577         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1578         .irq_clr_shift = IRQ16_MCU_CLR_SFT,
1579     },
1580     [MT8192_IRQ_17] = {
1581         .id = MT8192_IRQ_17,
1582         .irq_cnt_reg = AFE_IRQ_MCU_CNT17,
1583         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1584         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1585         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1586         .irq_fs_shift = IRQ17_MCU_MODE_SFT,
1587         .irq_fs_maskbit = IRQ17_MCU_MODE_MASK,
1588         .irq_en_reg = AFE_IRQ_MCU_CON0,
1589         .irq_en_shift = IRQ17_MCU_ON_SFT,
1590         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1591         .irq_clr_shift = IRQ17_MCU_CLR_SFT,
1592     },
1593     [MT8192_IRQ_18] = {
1594         .id = MT8192_IRQ_18,
1595         .irq_cnt_reg = AFE_IRQ_MCU_CNT18,
1596         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1597         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1598         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1599         .irq_fs_shift = IRQ18_MCU_MODE_SFT,
1600         .irq_fs_maskbit = IRQ18_MCU_MODE_MASK,
1601         .irq_en_reg = AFE_IRQ_MCU_CON0,
1602         .irq_en_shift = IRQ18_MCU_ON_SFT,
1603         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1604         .irq_clr_shift = IRQ18_MCU_CLR_SFT,
1605     },
1606     [MT8192_IRQ_19] = {
1607         .id = MT8192_IRQ_19,
1608         .irq_cnt_reg = AFE_IRQ_MCU_CNT19,
1609         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1610         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1611         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1612         .irq_fs_shift = IRQ19_MCU_MODE_SFT,
1613         .irq_fs_maskbit = IRQ19_MCU_MODE_MASK,
1614         .irq_en_reg = AFE_IRQ_MCU_CON0,
1615         .irq_en_shift = IRQ19_MCU_ON_SFT,
1616         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1617         .irq_clr_shift = IRQ19_MCU_CLR_SFT,
1618     },
1619     [MT8192_IRQ_20] = {
1620         .id = MT8192_IRQ_20,
1621         .irq_cnt_reg = AFE_IRQ_MCU_CNT20,
1622         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1623         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1624         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1625         .irq_fs_shift = IRQ20_MCU_MODE_SFT,
1626         .irq_fs_maskbit = IRQ20_MCU_MODE_MASK,
1627         .irq_en_reg = AFE_IRQ_MCU_CON0,
1628         .irq_en_shift = IRQ20_MCU_ON_SFT,
1629         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1630         .irq_clr_shift = IRQ20_MCU_CLR_SFT,
1631     },
1632     [MT8192_IRQ_21] = {
1633         .id = MT8192_IRQ_21,
1634         .irq_cnt_reg = AFE_IRQ_MCU_CNT21,
1635         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1636         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1637         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1638         .irq_fs_shift = IRQ21_MCU_MODE_SFT,
1639         .irq_fs_maskbit = IRQ21_MCU_MODE_MASK,
1640         .irq_en_reg = AFE_IRQ_MCU_CON0,
1641         .irq_en_shift = IRQ21_MCU_ON_SFT,
1642         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1643         .irq_clr_shift = IRQ21_MCU_CLR_SFT,
1644     },
1645     [MT8192_IRQ_22] = {
1646         .id = MT8192_IRQ_22,
1647         .irq_cnt_reg = AFE_IRQ_MCU_CNT22,
1648         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1649         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1650         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1651         .irq_fs_shift = IRQ22_MCU_MODE_SFT,
1652         .irq_fs_maskbit = IRQ22_MCU_MODE_MASK,
1653         .irq_en_reg = AFE_IRQ_MCU_CON0,
1654         .irq_en_shift = IRQ22_MCU_ON_SFT,
1655         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1656         .irq_clr_shift = IRQ22_MCU_CLR_SFT,
1657     },
1658     [MT8192_IRQ_23] = {
1659         .id = MT8192_IRQ_23,
1660         .irq_cnt_reg = AFE_IRQ_MCU_CNT23,
1661         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1662         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1663         .irq_fs_reg = AFE_IRQ_MCU_CON3,
1664         .irq_fs_shift = IRQ23_MCU_MODE_SFT,
1665         .irq_fs_maskbit = IRQ23_MCU_MODE_MASK,
1666         .irq_en_reg = AFE_IRQ_MCU_CON0,
1667         .irq_en_shift = IRQ23_MCU_ON_SFT,
1668         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1669         .irq_clr_shift = IRQ23_MCU_CLR_SFT,
1670     },
1671     [MT8192_IRQ_24] = {
1672         .id = MT8192_IRQ_24,
1673         .irq_cnt_reg = AFE_IRQ_MCU_CNT24,
1674         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1675         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1676         .irq_fs_reg = AFE_IRQ_MCU_CON4,
1677         .irq_fs_shift = IRQ24_MCU_MODE_SFT,
1678         .irq_fs_maskbit = IRQ24_MCU_MODE_MASK,
1679         .irq_en_reg = AFE_IRQ_MCU_CON0,
1680         .irq_en_shift = IRQ24_MCU_ON_SFT,
1681         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1682         .irq_clr_shift = IRQ24_MCU_CLR_SFT,
1683     },
1684     [MT8192_IRQ_25] = {
1685         .id = MT8192_IRQ_25,
1686         .irq_cnt_reg = AFE_IRQ_MCU_CNT25,
1687         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1688         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1689         .irq_fs_reg = AFE_IRQ_MCU_CON4,
1690         .irq_fs_shift = IRQ25_MCU_MODE_SFT,
1691         .irq_fs_maskbit = IRQ25_MCU_MODE_MASK,
1692         .irq_en_reg = AFE_IRQ_MCU_CON0,
1693         .irq_en_shift = IRQ25_MCU_ON_SFT,
1694         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1695         .irq_clr_shift = IRQ25_MCU_CLR_SFT,
1696     },
1697     [MT8192_IRQ_26] = {
1698         .id = MT8192_IRQ_26,
1699         .irq_cnt_reg = AFE_IRQ_MCU_CNT26,
1700         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1701         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1702         .irq_fs_reg = AFE_IRQ_MCU_CON4,
1703         .irq_fs_shift = IRQ26_MCU_MODE_SFT,
1704         .irq_fs_maskbit = IRQ26_MCU_MODE_MASK,
1705         .irq_en_reg = AFE_IRQ_MCU_CON0,
1706         .irq_en_shift = IRQ26_MCU_ON_SFT,
1707         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1708         .irq_clr_shift = IRQ26_MCU_CLR_SFT,
1709     },
1710     [MT8192_IRQ_31] = {
1711         .id = MT8192_IRQ_31,
1712         .irq_cnt_reg = AFE_IRQ_MCU_CNT31,
1713         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
1714         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
1715         .irq_fs_reg = -1,
1716         .irq_fs_shift = -1,
1717         .irq_fs_maskbit = -1,
1718         .irq_en_reg = AFE_IRQ_MCU_CON0,
1719         .irq_en_shift = IRQ31_MCU_ON_SFT,
1720         .irq_clr_reg = AFE_IRQ_MCU_CLR,
1721         .irq_clr_shift = IRQ31_MCU_CLR_SFT,
1722     },
1723 };
1724 
1725 static const int memif_irq_usage[MT8192_MEMIF_NUM] = {
1726     [MT8192_MEMIF_DL1] = MT8192_IRQ_0,
1727     [MT8192_MEMIF_DL2] = MT8192_IRQ_1,
1728     [MT8192_MEMIF_DL3] = MT8192_IRQ_2,
1729     [MT8192_MEMIF_DL4] = MT8192_IRQ_3,
1730     [MT8192_MEMIF_DL5] = MT8192_IRQ_4,
1731     [MT8192_MEMIF_DL6] = MT8192_IRQ_5,
1732     [MT8192_MEMIF_DL7] = MT8192_IRQ_6,
1733     [MT8192_MEMIF_DL8] = MT8192_IRQ_7,
1734     [MT8192_MEMIF_DL9] = MT8192_IRQ_8,
1735     [MT8192_MEMIF_DL12] = MT8192_IRQ_9,
1736     [MT8192_MEMIF_DAI] = MT8192_IRQ_10,
1737     [MT8192_MEMIF_MOD_DAI] = MT8192_IRQ_11,
1738     [MT8192_MEMIF_DAI2] = MT8192_IRQ_12,
1739     [MT8192_MEMIF_VUL12] = MT8192_IRQ_13,
1740     [MT8192_MEMIF_VUL2] = MT8192_IRQ_14,
1741     [MT8192_MEMIF_AWB] = MT8192_IRQ_15,
1742     [MT8192_MEMIF_AWB2] = MT8192_IRQ_16,
1743     [MT8192_MEMIF_VUL3] = MT8192_IRQ_17,
1744     [MT8192_MEMIF_VUL4] = MT8192_IRQ_18,
1745     [MT8192_MEMIF_VUL5] = MT8192_IRQ_19,
1746     [MT8192_MEMIF_VUL6] = MT8192_IRQ_20,
1747     [MT8192_MEMIF_HDMI] = MT8192_IRQ_31,
1748 };
1749 
1750 static bool mt8192_is_volatile_reg(struct device *dev, unsigned int reg)
1751 {
1752     /* these auto-gen reg has read-only bit, so put it as volatile */
1753     /* volatile reg cannot be cached, so cannot be set when power off */
1754     switch (reg) {
1755     case AUDIO_TOP_CON0:    /* reg bit controlled by CCF */
1756     case AUDIO_TOP_CON1:    /* reg bit controlled by CCF */
1757     case AUDIO_TOP_CON2:
1758     case AUDIO_TOP_CON3:
1759     case AFE_DL1_CUR_MSB:
1760     case AFE_DL1_CUR:
1761     case AFE_DL1_END:
1762     case AFE_DL2_CUR_MSB:
1763     case AFE_DL2_CUR:
1764     case AFE_DL2_END:
1765     case AFE_DL3_CUR_MSB:
1766     case AFE_DL3_CUR:
1767     case AFE_DL3_END:
1768     case AFE_DL4_CUR_MSB:
1769     case AFE_DL4_CUR:
1770     case AFE_DL4_END:
1771     case AFE_DL12_CUR_MSB:
1772     case AFE_DL12_CUR:
1773     case AFE_DL12_END:
1774     case AFE_ADDA_SRC_DEBUG_MON0:
1775     case AFE_ADDA_SRC_DEBUG_MON1:
1776     case AFE_ADDA_UL_SRC_MON0:
1777     case AFE_ADDA_UL_SRC_MON1:
1778     case AFE_SECURE_CON0:
1779     case AFE_SRAM_BOUND:
1780     case AFE_SECURE_CON1:
1781     case AFE_VUL_CUR_MSB:
1782     case AFE_VUL_CUR:
1783     case AFE_VUL_END:
1784     case AFE_ADDA_3RD_DAC_DL_SDM_FIFO_MON:
1785     case AFE_ADDA_3RD_DAC_DL_SRC_LCH_MON:
1786     case AFE_ADDA_3RD_DAC_DL_SRC_RCH_MON:
1787     case AFE_ADDA_3RD_DAC_DL_SDM_OUT_MON:
1788     case AFE_SIDETONE_MON:
1789     case AFE_SIDETONE_CON0:
1790     case AFE_SIDETONE_COEFF:
1791     case AFE_VUL2_CUR_MSB:
1792     case AFE_VUL2_CUR:
1793     case AFE_VUL2_END:
1794     case AFE_VUL3_CUR_MSB:
1795     case AFE_VUL3_CUR:
1796     case AFE_VUL3_END:
1797     case AFE_I2S_MON:
1798     case AFE_DAC_MON:
1799     case AFE_IRQ0_MCU_CNT_MON:
1800     case AFE_IRQ6_MCU_CNT_MON:
1801     case AFE_VUL4_CUR_MSB:
1802     case AFE_VUL4_CUR:
1803     case AFE_VUL4_END:
1804     case AFE_VUL12_CUR_MSB:
1805     case AFE_VUL12_CUR:
1806     case AFE_VUL12_END:
1807     case AFE_IRQ3_MCU_CNT_MON:
1808     case AFE_IRQ4_MCU_CNT_MON:
1809     case AFE_IRQ_MCU_STATUS:
1810     case AFE_IRQ_MCU_CLR:
1811     case AFE_IRQ_MCU_MON2:
1812     case AFE_IRQ1_MCU_CNT_MON:
1813     case AFE_IRQ2_MCU_CNT_MON:
1814     case AFE_IRQ5_MCU_CNT_MON:
1815     case AFE_IRQ7_MCU_CNT_MON:
1816     case AFE_IRQ_MCU_MISS_CLR:
1817     case AFE_GAIN1_CUR:
1818     case AFE_GAIN2_CUR:
1819     case AFE_SRAM_DELSEL_CON1:
1820     case PCM_INTF_CON2:
1821     case FPGA_CFG0:
1822     case FPGA_CFG1:
1823     case FPGA_CFG2:
1824     case FPGA_CFG3:
1825     case AUDIO_TOP_DBG_MON0:
1826     case AUDIO_TOP_DBG_MON1:
1827     case AFE_IRQ8_MCU_CNT_MON:
1828     case AFE_IRQ11_MCU_CNT_MON:
1829     case AFE_IRQ12_MCU_CNT_MON:
1830     case AFE_IRQ9_MCU_CNT_MON:
1831     case AFE_IRQ10_MCU_CNT_MON:
1832     case AFE_IRQ13_MCU_CNT_MON:
1833     case AFE_IRQ14_MCU_CNT_MON:
1834     case AFE_IRQ15_MCU_CNT_MON:
1835     case AFE_IRQ16_MCU_CNT_MON:
1836     case AFE_IRQ17_MCU_CNT_MON:
1837     case AFE_IRQ18_MCU_CNT_MON:
1838     case AFE_IRQ19_MCU_CNT_MON:
1839     case AFE_IRQ20_MCU_CNT_MON:
1840     case AFE_IRQ21_MCU_CNT_MON:
1841     case AFE_IRQ22_MCU_CNT_MON:
1842     case AFE_IRQ23_MCU_CNT_MON:
1843     case AFE_IRQ24_MCU_CNT_MON:
1844     case AFE_IRQ25_MCU_CNT_MON:
1845     case AFE_IRQ26_MCU_CNT_MON:
1846     case AFE_IRQ31_MCU_CNT_MON:
1847     case AFE_CBIP_MON0:
1848     case AFE_CBIP_SLV_MUX_MON0:
1849     case AFE_CBIP_SLV_DECODER_MON0:
1850     case AFE_ADDA6_MTKAIF_MON0:
1851     case AFE_ADDA6_MTKAIF_MON1:
1852     case AFE_AWB_CUR_MSB:
1853     case AFE_AWB_CUR:
1854     case AFE_AWB_END:
1855     case AFE_AWB2_CUR_MSB:
1856     case AFE_AWB2_CUR:
1857     case AFE_AWB2_END:
1858     case AFE_DAI_CUR_MSB:
1859     case AFE_DAI_CUR:
1860     case AFE_DAI_END:
1861     case AFE_DAI2_CUR_MSB:
1862     case AFE_DAI2_CUR:
1863     case AFE_DAI2_END:
1864     case AFE_ADDA6_SRC_DEBUG_MON0:
1865     case AFE_ADD6A_UL_SRC_MON0:
1866     case AFE_ADDA6_UL_SRC_MON1:
1867     case AFE_MOD_DAI_CUR_MSB:
1868     case AFE_MOD_DAI_CUR:
1869     case AFE_MOD_DAI_END:
1870     case AFE_HDMI_OUT_CUR_MSB:
1871     case AFE_HDMI_OUT_CUR:
1872     case AFE_HDMI_OUT_END:
1873     case AFE_AWB_RCH_MON:
1874     case AFE_AWB_LCH_MON:
1875     case AFE_VUL_RCH_MON:
1876     case AFE_VUL_LCH_MON:
1877     case AFE_VUL12_RCH_MON:
1878     case AFE_VUL12_LCH_MON:
1879     case AFE_VUL2_RCH_MON:
1880     case AFE_VUL2_LCH_MON:
1881     case AFE_DAI_DATA_MON:
1882     case AFE_MOD_DAI_DATA_MON:
1883     case AFE_DAI2_DATA_MON:
1884     case AFE_AWB2_RCH_MON:
1885     case AFE_AWB2_LCH_MON:
1886     case AFE_VUL3_RCH_MON:
1887     case AFE_VUL3_LCH_MON:
1888     case AFE_VUL4_RCH_MON:
1889     case AFE_VUL4_LCH_MON:
1890     case AFE_VUL5_RCH_MON:
1891     case AFE_VUL5_LCH_MON:
1892     case AFE_VUL6_RCH_MON:
1893     case AFE_VUL6_LCH_MON:
1894     case AFE_DL1_RCH_MON:
1895     case AFE_DL1_LCH_MON:
1896     case AFE_DL2_RCH_MON:
1897     case AFE_DL2_LCH_MON:
1898     case AFE_DL12_RCH1_MON:
1899     case AFE_DL12_LCH1_MON:
1900     case AFE_DL12_RCH2_MON:
1901     case AFE_DL12_LCH2_MON:
1902     case AFE_DL3_RCH_MON:
1903     case AFE_DL3_LCH_MON:
1904     case AFE_DL4_RCH_MON:
1905     case AFE_DL4_LCH_MON:
1906     case AFE_DL5_RCH_MON:
1907     case AFE_DL5_LCH_MON:
1908     case AFE_DL6_RCH_MON:
1909     case AFE_DL6_LCH_MON:
1910     case AFE_DL7_RCH_MON:
1911     case AFE_DL7_LCH_MON:
1912     case AFE_DL8_RCH_MON:
1913     case AFE_DL8_LCH_MON:
1914     case AFE_VUL5_CUR_MSB:
1915     case AFE_VUL5_CUR:
1916     case AFE_VUL5_END:
1917     case AFE_VUL6_CUR_MSB:
1918     case AFE_VUL6_CUR:
1919     case AFE_VUL6_END:
1920     case AFE_ADDA_DL_SDM_FIFO_MON:
1921     case AFE_ADDA_DL_SRC_LCH_MON:
1922     case AFE_ADDA_DL_SRC_RCH_MON:
1923     case AFE_ADDA_DL_SDM_OUT_MON:
1924     case AFE_CONNSYS_I2S_MON:
1925     case AFE_ASRC_2CH_CON0:
1926     case AFE_ASRC_2CH_CON2:
1927     case AFE_ASRC_2CH_CON3:
1928     case AFE_ASRC_2CH_CON4:
1929     case AFE_ASRC_2CH_CON5:
1930     case AFE_ASRC_2CH_CON7:
1931     case AFE_ASRC_2CH_CON8:
1932     case AFE_ASRC_2CH_CON12:
1933     case AFE_ASRC_2CH_CON13:
1934     case AFE_DL9_CUR_MSB:
1935     case AFE_DL9_CUR:
1936     case AFE_DL9_END:
1937     case AFE_ADDA_MTKAIF_MON0:
1938     case AFE_ADDA_MTKAIF_MON1:
1939     case AFE_DL_NLE_R_MON0:
1940     case AFE_DL_NLE_R_MON1:
1941     case AFE_DL_NLE_R_MON2:
1942     case AFE_DL_NLE_L_MON0:
1943     case AFE_DL_NLE_L_MON1:
1944     case AFE_DL_NLE_L_MON2:
1945     case AFE_GENERAL1_ASRC_2CH_CON0:
1946     case AFE_GENERAL1_ASRC_2CH_CON2:
1947     case AFE_GENERAL1_ASRC_2CH_CON3:
1948     case AFE_GENERAL1_ASRC_2CH_CON4:
1949     case AFE_GENERAL1_ASRC_2CH_CON5:
1950     case AFE_GENERAL1_ASRC_2CH_CON7:
1951     case AFE_GENERAL1_ASRC_2CH_CON8:
1952     case AFE_GENERAL1_ASRC_2CH_CON12:
1953     case AFE_GENERAL1_ASRC_2CH_CON13:
1954     case AFE_GENERAL2_ASRC_2CH_CON0:
1955     case AFE_GENERAL2_ASRC_2CH_CON2:
1956     case AFE_GENERAL2_ASRC_2CH_CON3:
1957     case AFE_GENERAL2_ASRC_2CH_CON4:
1958     case AFE_GENERAL2_ASRC_2CH_CON5:
1959     case AFE_GENERAL2_ASRC_2CH_CON7:
1960     case AFE_GENERAL2_ASRC_2CH_CON8:
1961     case AFE_GENERAL2_ASRC_2CH_CON12:
1962     case AFE_GENERAL2_ASRC_2CH_CON13:
1963     case AFE_DL9_RCH_MON:
1964     case AFE_DL9_LCH_MON:
1965     case AFE_DL5_CUR_MSB:
1966     case AFE_DL5_CUR:
1967     case AFE_DL5_END:
1968     case AFE_DL6_CUR_MSB:
1969     case AFE_DL6_CUR:
1970     case AFE_DL6_END:
1971     case AFE_DL7_CUR_MSB:
1972     case AFE_DL7_CUR:
1973     case AFE_DL7_END:
1974     case AFE_DL8_CUR_MSB:
1975     case AFE_DL8_CUR:
1976     case AFE_DL8_END:
1977     case AFE_PROT_SIDEBAND_MON:
1978     case AFE_DOMAIN_SIDEBAND0_MON:
1979     case AFE_DOMAIN_SIDEBAND1_MON:
1980     case AFE_DOMAIN_SIDEBAND2_MON:
1981     case AFE_DOMAIN_SIDEBAND3_MON:
1982     case AFE_APLL1_TUNER_CFG:   /* [20:31] is monitor */
1983     case AFE_APLL2_TUNER_CFG:   /* [20:31] is monitor */
1984     case AFE_DAC_CON0:
1985     case AFE_IRQ_MCU_CON0:
1986     case AFE_IRQ_MCU_EN:
1987         return true;
1988     default:
1989         return false;
1990     };
1991 }
1992 
1993 static const struct regmap_config mt8192_afe_regmap_config = {
1994     .reg_bits = 32,
1995     .reg_stride = 4,
1996     .val_bits = 32,
1997     .volatile_reg = mt8192_is_volatile_reg,
1998     .max_register = AFE_MAX_REGISTER,
1999     .num_reg_defaults_raw = AFE_MAX_REGISTER,
2000     .cache_type = REGCACHE_FLAT,
2001 };
2002 
2003 static irqreturn_t mt8192_afe_irq_handler(int irq_id, void *dev)
2004 {
2005     struct mtk_base_afe *afe = dev;
2006     struct mtk_base_afe_irq *irq;
2007     unsigned int status;
2008     unsigned int status_mcu;
2009     unsigned int mcu_en;
2010     int ret;
2011     int i;
2012 
2013     /* get irq that is sent to MCU */
2014     regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
2015 
2016     ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
2017     /* only care IRQ which is sent to MCU */
2018     status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
2019 
2020     if (ret || status_mcu == 0) {
2021         dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
2022             __func__, ret, status, mcu_en);
2023 
2024         goto err_irq;
2025     }
2026 
2027     for (i = 0; i < MT8192_MEMIF_NUM; i++) {
2028         struct mtk_base_afe_memif *memif = &afe->memif[i];
2029 
2030         if (!memif->substream)
2031             continue;
2032 
2033         if (memif->irq_usage < 0)
2034             continue;
2035 
2036         irq = &afe->irqs[memif->irq_usage];
2037 
2038         if (status_mcu & (1 << irq->irq_data->irq_en_shift))
2039             snd_pcm_period_elapsed(memif->substream);
2040     }
2041 
2042 err_irq:
2043     /* clear irq */
2044     regmap_write(afe->regmap,
2045              AFE_IRQ_MCU_CLR,
2046              status_mcu);
2047 
2048     return IRQ_HANDLED;
2049 }
2050 
2051 static int mt8192_afe_runtime_suspend(struct device *dev)
2052 {
2053     struct mtk_base_afe *afe = dev_get_drvdata(dev);
2054     struct mt8192_afe_private *afe_priv = afe->platform_priv;
2055     unsigned int value;
2056     int ret;
2057 
2058     dev_info(afe->dev, "%s()\n", __func__);
2059 
2060     if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
2061         goto skip_regmap;
2062 
2063     /* disable AFE */
2064     regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
2065 
2066     ret = regmap_read_poll_timeout(afe->regmap,
2067                        AFE_DAC_MON,
2068                        value,
2069                        (value & AFE_ON_RETM_MASK_SFT) == 0,
2070                        20,
2071                        1 * 1000 * 1000);
2072     if (ret)
2073         dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
2074 
2075     /* make sure all irq status are cleared */
2076     regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
2077     regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
2078 
2079     /* reset sgen */
2080     regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0);
2081     regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
2082                INNER_LOOP_BACK_MODE_MASK_SFT,
2083                0x3f << INNER_LOOP_BACK_MODE_SFT);
2084 
2085     /* cache only */
2086     regcache_cache_only(afe->regmap, true);
2087     regcache_mark_dirty(afe->regmap);
2088 
2089 skip_regmap:
2090     mt8192_afe_disable_clock(afe);
2091     return 0;
2092 }
2093 
2094 static int mt8192_afe_runtime_resume(struct device *dev)
2095 {
2096     struct mtk_base_afe *afe = dev_get_drvdata(dev);
2097     struct mt8192_afe_private *afe_priv = afe->platform_priv;
2098     int ret;
2099 
2100     dev_info(afe->dev, "%s()\n", __func__);
2101 
2102     ret = mt8192_afe_enable_clock(afe);
2103     if (ret)
2104         return ret;
2105 
2106     if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
2107         goto skip_regmap;
2108 
2109     regcache_cache_only(afe->regmap, false);
2110     regcache_sync(afe->regmap);
2111 
2112     /* enable audio sys DCM for power saving */
2113     regmap_update_bits(afe_priv->infracfg,
2114                PERI_BUS_DCM_CTRL, 0x1 << 29, 0x1 << 29);
2115     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
2116 
2117     /* force cpu use 8_24 format when writing 32bit data */
2118     regmap_update_bits(afe->regmap, AFE_MEMIF_CON0,
2119                CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
2120 
2121     /* set all output port to 24bit */
2122     regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
2123     regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
2124 
2125     /* enable AFE */
2126     regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x1);
2127 
2128 skip_regmap:
2129     return 0;
2130 }
2131 
2132 static int mt8192_afe_component_probe(struct snd_soc_component *component)
2133 {
2134     return mtk_afe_add_sub_dai_control(component);
2135 }
2136 
2137 static const struct snd_soc_component_driver mt8192_afe_component = {
2138     .name = AFE_PCM_NAME,
2139     .probe = mt8192_afe_component_probe,
2140     .pointer = mtk_afe_pcm_pointer,
2141     .pcm_construct = mtk_afe_pcm_new,
2142 };
2143 
2144 static const struct snd_soc_component_driver mt8192_afe_pcm_component = {
2145     .name = "mt8192-afe-pcm-dai",
2146 };
2147 
2148 static int mt8192_dai_memif_register(struct mtk_base_afe *afe)
2149 {
2150     struct mtk_base_afe_dai *dai;
2151 
2152     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2153     if (!dai)
2154         return -ENOMEM;
2155 
2156     list_add(&dai->list, &afe->sub_dais);
2157 
2158     dai->dai_drivers = mt8192_memif_dai_driver;
2159     dai->num_dai_drivers = ARRAY_SIZE(mt8192_memif_dai_driver);
2160 
2161     dai->dapm_widgets = mt8192_memif_widgets;
2162     dai->num_dapm_widgets = ARRAY_SIZE(mt8192_memif_widgets);
2163     dai->dapm_routes = mt8192_memif_routes;
2164     dai->num_dapm_routes = ARRAY_SIZE(mt8192_memif_routes);
2165     return 0;
2166 }
2167 
2168 typedef int (*dai_register_cb)(struct mtk_base_afe *);
2169 static const dai_register_cb dai_register_cbs[] = {
2170     mt8192_dai_adda_register,
2171     mt8192_dai_i2s_register,
2172     mt8192_dai_pcm_register,
2173     mt8192_dai_tdm_register,
2174     mt8192_dai_memif_register,
2175 };
2176 
2177 static int mt8192_afe_pcm_dev_probe(struct platform_device *pdev)
2178 {
2179     struct mtk_base_afe *afe;
2180     struct mt8192_afe_private *afe_priv;
2181     struct device *dev;
2182     struct reset_control *rstc;
2183     int i, ret, irq_id;
2184 
2185     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
2186     if (ret)
2187         return ret;
2188 
2189     afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
2190     if (!afe)
2191         return -ENOMEM;
2192     platform_set_drvdata(pdev, afe);
2193 
2194     afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
2195                       GFP_KERNEL);
2196     if (!afe->platform_priv)
2197         return -ENOMEM;
2198     afe_priv = afe->platform_priv;
2199 
2200     afe->dev = &pdev->dev;
2201     dev = afe->dev;
2202 
2203     /* init audio related clock */
2204     ret = mt8192_init_clock(afe);
2205     if (ret) {
2206         dev_err(dev, "init clock error\n");
2207         return ret;
2208     }
2209 
2210     /* reset controller to reset audio regs before regmap cache */
2211     rstc = devm_reset_control_get_exclusive(dev, "audiosys");
2212     if (IS_ERR(rstc)) {
2213         ret = PTR_ERR(rstc);
2214         dev_err(dev, "could not get audiosys reset:%d\n", ret);
2215         return ret;
2216     }
2217 
2218     ret = reset_control_reset(rstc);
2219     if (ret) {
2220         dev_err(dev, "failed to trigger audio reset:%d\n", ret);
2221         return ret;
2222     }
2223 
2224     pm_runtime_enable(&pdev->dev);
2225     if (!pm_runtime_enabled(&pdev->dev))
2226         goto err_pm_disable;
2227 
2228     /* regmap init */
2229     afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
2230     if (IS_ERR(afe->regmap)) {
2231         dev_err(dev, "could not get regmap from parent\n");
2232         ret = PTR_ERR(afe->regmap);
2233         goto err_pm_disable;
2234     }
2235     ret = regmap_attach_dev(dev, afe->regmap, &mt8192_afe_regmap_config);
2236     if (ret) {
2237         dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
2238         goto err_pm_disable;
2239     }
2240 
2241     /* enable clock for regcache get default value from hw */
2242     afe_priv->pm_runtime_bypass_reg_ctl = true;
2243     pm_runtime_get_sync(&pdev->dev);
2244 
2245     ret = regmap_reinit_cache(afe->regmap, &mt8192_afe_regmap_config);
2246     if (ret) {
2247         dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
2248         goto err_pm_disable;
2249     }
2250 
2251     pm_runtime_put_sync(&pdev->dev);
2252     afe_priv->pm_runtime_bypass_reg_ctl = false;
2253 
2254     regcache_cache_only(afe->regmap, true);
2255     regcache_mark_dirty(afe->regmap);
2256 
2257     /* init memif */
2258     afe->memif_size = MT8192_MEMIF_NUM;
2259     afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
2260                   GFP_KERNEL);
2261     if (!afe->memif) {
2262         ret = -ENOMEM;
2263         goto err_pm_disable;
2264     }
2265 
2266     for (i = 0; i < afe->memif_size; i++) {
2267         afe->memif[i].data = &memif_data[i];
2268         afe->memif[i].irq_usage = memif_irq_usage[i];
2269         afe->memif[i].const_irq = 1;
2270     }
2271 
2272     mutex_init(&afe->irq_alloc_lock);   /* needed when dynamic irq */
2273 
2274     /* init irq */
2275     afe->irqs_size = MT8192_IRQ_NUM;
2276     afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
2277                  GFP_KERNEL);
2278     if (!afe->irqs) {
2279         ret = -ENOMEM;
2280         goto err_pm_disable;
2281     }
2282 
2283     for (i = 0; i < afe->irqs_size; i++)
2284         afe->irqs[i].irq_data = &irq_data[i];
2285 
2286     /* request irq */
2287     irq_id = platform_get_irq(pdev, 0);
2288     if (irq_id < 0) {
2289         ret = irq_id;
2290         goto err_pm_disable;
2291     }
2292 
2293     ret = devm_request_irq(dev, irq_id, mt8192_afe_irq_handler,
2294                    IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
2295     if (ret) {
2296         dev_err(dev, "could not request_irq for Afe_ISR_Handle\n");
2297         goto err_pm_disable;
2298     }
2299 
2300     /* init sub_dais */
2301     INIT_LIST_HEAD(&afe->sub_dais);
2302 
2303     for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
2304         ret = dai_register_cbs[i](afe);
2305         if (ret) {
2306             dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
2307                  i, ret);
2308             goto err_pm_disable;
2309         }
2310     }
2311 
2312     /* init dai_driver and component_driver */
2313     ret = mtk_afe_combine_sub_dai(afe);
2314     if (ret) {
2315         dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
2316              ret);
2317         goto err_pm_disable;
2318     }
2319 
2320     /* others */
2321     afe->mtk_afe_hardware = &mt8192_afe_hardware;
2322     afe->memif_fs = mt8192_memif_fs;
2323     afe->irq_fs = mt8192_irq_fs;
2324     afe->get_dai_fs = mt8192_get_dai_fs;
2325     afe->get_memif_pbuf_size = mt8192_get_memif_pbuf_size;
2326     afe->memif_32bit_supported = 1;
2327 
2328     afe->runtime_resume = mt8192_afe_runtime_resume;
2329     afe->runtime_suspend = mt8192_afe_runtime_suspend;
2330 
2331     /* register platform */
2332     ret = devm_snd_soc_register_component(&pdev->dev,
2333                           &mt8192_afe_component, NULL, 0);
2334     if (ret) {
2335         dev_warn(dev, "err_platform\n");
2336         goto err_pm_disable;
2337     }
2338 
2339     ret = devm_snd_soc_register_component(&pdev->dev,
2340                           &mt8192_afe_pcm_component,
2341                           afe->dai_drivers,
2342                           afe->num_dai_drivers);
2343     if (ret) {
2344         dev_warn(dev, "err_dai_component\n");
2345         goto err_pm_disable;
2346     }
2347 
2348     return 0;
2349 
2350 err_pm_disable:
2351     pm_runtime_disable(&pdev->dev);
2352 
2353     return ret;
2354 }
2355 
2356 static int mt8192_afe_pcm_dev_remove(struct platform_device *pdev)
2357 {
2358     struct mtk_base_afe *afe = platform_get_drvdata(pdev);
2359 
2360     pm_runtime_disable(&pdev->dev);
2361     if (!pm_runtime_status_suspended(&pdev->dev))
2362         mt8192_afe_runtime_suspend(&pdev->dev);
2363 
2364     /* disable afe clock */
2365     mt8192_afe_disable_clock(afe);
2366     return 0;
2367 }
2368 
2369 static const struct of_device_id mt8192_afe_pcm_dt_match[] = {
2370     { .compatible = "mediatek,mt8192-audio", },
2371     {},
2372 };
2373 MODULE_DEVICE_TABLE(of, mt8192_afe_pcm_dt_match);
2374 
2375 static const struct dev_pm_ops mt8192_afe_pm_ops = {
2376     SET_RUNTIME_PM_OPS(mt8192_afe_runtime_suspend,
2377                mt8192_afe_runtime_resume, NULL)
2378 };
2379 
2380 static struct platform_driver mt8192_afe_pcm_driver = {
2381     .driver = {
2382            .name = "mt8192-audio",
2383            .of_match_table = mt8192_afe_pcm_dt_match,
2384            .pm = &mt8192_afe_pm_ops,
2385     },
2386     .probe = mt8192_afe_pcm_dev_probe,
2387     .remove = mt8192_afe_pcm_dev_remove,
2388 };
2389 
2390 module_platform_driver(mt8192_afe_pcm_driver);
2391 
2392 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8192");
2393 MODULE_AUTHOR("Shane Chien <shane.chien@mediatek.com>");
2394 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!