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0009 #include <linux/arm-smccc.h>
0010 #include <linux/clk.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/regmap.h>
0013
0014 #include "mt8192-afe-clk.h"
0015 #include "mt8192-afe-common.h"
0016
0017 static const char *aud_clks[CLK_NUM] = {
0018 [CLK_AFE] = "aud_afe_clk",
0019 [CLK_TML] = "aud_tml_clk",
0020 [CLK_APLL22M] = "aud_apll22m_clk",
0021 [CLK_APLL24M] = "aud_apll24m_clk",
0022 [CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
0023 [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
0024 [CLK_NLE] = "aud_nle",
0025 [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
0026 [CLK_INFRA_AUDIO_26M] = "aud_infra_26m_clk",
0027 [CLK_MUX_AUDIO] = "top_mux_audio",
0028 [CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
0029 [CLK_TOP_MAINPLL_D4_D4] = "top_mainpll_d4_d4",
0030 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
0031 [CLK_TOP_APLL1_CK] = "top_apll1_ck",
0032 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
0033 [CLK_TOP_APLL2_CK] = "top_apll2_ck",
0034 [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
0035 [CLK_TOP_APLL1_D4] = "top_apll1_d4",
0036 [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
0037 [CLK_TOP_APLL2_D4] = "top_apll2_d4",
0038 [CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
0039 [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
0040 [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
0041 [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
0042 [CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
0043 [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
0044 [CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
0045 [CLK_TOP_I2S6_M_SEL] = "top_i2s6_m_sel",
0046 [CLK_TOP_I2S7_M_SEL] = "top_i2s7_m_sel",
0047 [CLK_TOP_I2S8_M_SEL] = "top_i2s8_m_sel",
0048 [CLK_TOP_I2S9_M_SEL] = "top_i2s9_m_sel",
0049 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
0050 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
0051 [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
0052 [CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
0053 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
0054 [CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
0055 [CLK_TOP_APLL12_DIV5] = "top_apll12_div5",
0056 [CLK_TOP_APLL12_DIV6] = "top_apll12_div6",
0057 [CLK_TOP_APLL12_DIV7] = "top_apll12_div7",
0058 [CLK_TOP_APLL12_DIV8] = "top_apll12_div8",
0059 [CLK_TOP_APLL12_DIV9] = "top_apll12_div9",
0060 [CLK_CLK26M] = "top_clk26m_clk",
0061 };
0062
0063 int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe,
0064 int clk_id)
0065 {
0066 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0067 int ret;
0068
0069 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
0070 afe_priv->clk[clk_id]);
0071 if (ret) {
0072 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0073 __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
0074 aud_clks[clk_id], ret);
0075 }
0076
0077 return ret;
0078 }
0079
0080 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
0081 {
0082 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0083 int ret;
0084
0085 if (enable) {
0086 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0087 if (ret) {
0088 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0089 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
0090 goto EXIT;
0091 }
0092 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0093 afe_priv->clk[CLK_TOP_APLL1_CK]);
0094 if (ret) {
0095 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0096 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
0097 aud_clks[CLK_TOP_APLL1_CK], ret);
0098 goto EXIT;
0099 }
0100
0101
0102 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0103 if (ret) {
0104 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0105 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
0106 goto EXIT;
0107 }
0108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0109 afe_priv->clk[CLK_TOP_APLL1_D4]);
0110 if (ret) {
0111 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0112 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
0113 aud_clks[CLK_TOP_APLL1_D4], ret);
0114 goto EXIT;
0115 }
0116 } else {
0117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0118 afe_priv->clk[CLK_CLK26M]);
0119 if (ret) {
0120 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0121 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
0122 aud_clks[CLK_CLK26M], ret);
0123 goto EXIT;
0124 }
0125 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0126
0127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0128 afe_priv->clk[CLK_CLK26M]);
0129 if (ret) {
0130 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0131 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
0132 aud_clks[CLK_CLK26M], ret);
0133 goto EXIT;
0134 }
0135 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0136 }
0137
0138 EXIT:
0139 return ret;
0140 }
0141
0142 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
0143 {
0144 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0145 int ret;
0146
0147 if (enable) {
0148 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0149 if (ret) {
0150 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0151 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
0152 goto EXIT;
0153 }
0154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0155 afe_priv->clk[CLK_TOP_APLL2_CK]);
0156 if (ret) {
0157 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0158 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
0159 aud_clks[CLK_TOP_APLL2_CK], ret);
0160 goto EXIT;
0161 }
0162
0163
0164 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0165 if (ret) {
0166 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0167 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
0168 goto EXIT;
0169 }
0170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0171 afe_priv->clk[CLK_TOP_APLL2_D4]);
0172 if (ret) {
0173 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0174 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
0175 aud_clks[CLK_TOP_APLL2_D4], ret);
0176 goto EXIT;
0177 }
0178 } else {
0179 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0180 afe_priv->clk[CLK_CLK26M]);
0181 if (ret) {
0182 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0183 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
0184 aud_clks[CLK_CLK26M], ret);
0185 goto EXIT;
0186 }
0187 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0188
0189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0190 afe_priv->clk[CLK_CLK26M]);
0191 if (ret) {
0192 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0193 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
0194 aud_clks[CLK_CLK26M], ret);
0195 goto EXIT;
0196 }
0197 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0198 }
0199
0200 EXIT:
0201 return ret;
0202 }
0203
0204 int mt8192_afe_enable_clock(struct mtk_base_afe *afe)
0205 {
0206 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0207 int ret;
0208
0209 dev_info(afe->dev, "%s()\n", __func__);
0210
0211 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0212 if (ret) {
0213 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0214 __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
0215 goto EXIT;
0216 }
0217
0218 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
0219 if (ret) {
0220 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0221 __func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
0222 goto EXIT;
0223 }
0224
0225 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
0226 if (ret) {
0227 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0228 __func__, aud_clks[CLK_MUX_AUDIO], ret);
0229 goto EXIT;
0230 }
0231 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
0232 afe_priv->clk[CLK_CLK26M]);
0233 if (ret) {
0234 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0235 __func__, aud_clks[CLK_MUX_AUDIO],
0236 aud_clks[CLK_CLK26M], ret);
0237 goto EXIT;
0238 }
0239
0240 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0241 if (ret) {
0242 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0243 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
0244 goto EXIT;
0245 }
0246
0247 ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
0248 if (ret) {
0249 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0250 __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
0251 aud_clks[CLK_CLK26M], ret);
0252 goto EXIT;
0253 }
0254
0255 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
0256 afe_priv->clk[CLK_TOP_APLL2_CK]);
0257 if (ret) {
0258 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0259 __func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
0260 aud_clks[CLK_TOP_APLL2_CK], ret);
0261 goto EXIT;
0262 }
0263
0264 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
0265 if (ret) {
0266 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0267 __func__, aud_clks[CLK_AFE], ret);
0268 goto EXIT;
0269 }
0270
0271 EXIT:
0272 return ret;
0273 }
0274
0275 void mt8192_afe_disable_clock(struct mtk_base_afe *afe)
0276 {
0277 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0278
0279 dev_info(afe->dev, "%s()\n", __func__);
0280
0281 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
0282 mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
0283 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0284 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
0285 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
0286 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0287 }
0288
0289 int mt8192_apll1_enable(struct mtk_base_afe *afe)
0290 {
0291 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0292 int ret;
0293
0294
0295 apll1_mux_setting(afe, true);
0296
0297 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
0298 if (ret) {
0299 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0300 __func__, aud_clks[CLK_APLL22M], ret);
0301 goto EXIT;
0302 }
0303
0304 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
0305 if (ret) {
0306 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0307 __func__, aud_clks[CLK_APLL1_TUNER], ret);
0308 goto EXIT;
0309 }
0310
0311 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
0312 0x0000FFF7, 0x00000832);
0313 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
0314
0315 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0316 AFE_22M_ON_MASK_SFT,
0317 0x1 << AFE_22M_ON_SFT);
0318
0319 EXIT:
0320 return ret;
0321 }
0322
0323 void mt8192_apll1_disable(struct mtk_base_afe *afe)
0324 {
0325 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0326
0327 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0328 AFE_22M_ON_MASK_SFT,
0329 0x0 << AFE_22M_ON_SFT);
0330
0331 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
0332
0333 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
0334 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
0335
0336 apll1_mux_setting(afe, false);
0337 }
0338
0339 int mt8192_apll2_enable(struct mtk_base_afe *afe)
0340 {
0341 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0342 int ret;
0343
0344
0345 apll2_mux_setting(afe, true);
0346
0347 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
0348 if (ret) {
0349 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0350 __func__, aud_clks[CLK_APLL24M], ret);
0351 goto EXIT;
0352 }
0353
0354 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
0355 if (ret) {
0356 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0357 __func__, aud_clks[CLK_APLL2_TUNER], ret);
0358 goto EXIT;
0359 }
0360
0361 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
0362 0x0000FFF7, 0x00000634);
0363 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
0364
0365 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0366 AFE_24M_ON_MASK_SFT,
0367 0x1 << AFE_24M_ON_SFT);
0368
0369 EXIT:
0370 return ret;
0371 }
0372
0373 void mt8192_apll2_disable(struct mtk_base_afe *afe)
0374 {
0375 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0376
0377 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0378 AFE_24M_ON_MASK_SFT,
0379 0x0 << AFE_24M_ON_SFT);
0380
0381 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
0382
0383 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
0384 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
0385
0386 apll2_mux_setting(afe, false);
0387 }
0388
0389 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll)
0390 {
0391 return (apll == MT8192_APLL1) ? 180633600 : 196608000;
0392 }
0393
0394 int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
0395 {
0396 return ((rate % 8000) == 0) ? MT8192_APLL2 : MT8192_APLL1;
0397 }
0398
0399 int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
0400 {
0401 if (strcmp(name, APLL1_W_NAME) == 0)
0402 return MT8192_APLL1;
0403 else
0404 return MT8192_APLL2;
0405 }
0406
0407
0408 struct mt8192_mck_div {
0409 int m_sel_id;
0410 int div_clk_id;
0411
0412 int div_pdn_reg;
0413 int div_pdn_mask_sft;
0414 int div_reg;
0415 int div_mask_sft;
0416 int div_mask;
0417 int div_sft;
0418 int div_apll_sel_reg;
0419 int div_apll_sel_mask_sft;
0420 int div_apll_sel_sft;
0421 };
0422
0423 static const struct mt8192_mck_div mck_div[MT8192_MCK_NUM] = {
0424 [MT8192_I2S0_MCK] = {
0425 .m_sel_id = CLK_TOP_I2S0_M_SEL,
0426 .div_clk_id = CLK_TOP_APLL12_DIV0,
0427 .div_pdn_reg = CLK_AUDDIV_0,
0428 .div_pdn_mask_sft = APLL12_DIV0_PDN_MASK_SFT,
0429 .div_reg = CLK_AUDDIV_2,
0430 .div_mask_sft = APLL12_CK_DIV0_MASK_SFT,
0431 .div_mask = APLL12_CK_DIV0_MASK,
0432 .div_sft = APLL12_CK_DIV0_SFT,
0433 .div_apll_sel_reg = CLK_AUDDIV_0,
0434 .div_apll_sel_mask_sft = APLL_I2S0_MCK_SEL_MASK_SFT,
0435 .div_apll_sel_sft = APLL_I2S0_MCK_SEL_SFT,
0436 },
0437 [MT8192_I2S1_MCK] = {
0438 .m_sel_id = CLK_TOP_I2S1_M_SEL,
0439 .div_clk_id = CLK_TOP_APLL12_DIV1,
0440 .div_pdn_reg = CLK_AUDDIV_0,
0441 .div_pdn_mask_sft = APLL12_DIV1_PDN_MASK_SFT,
0442 .div_reg = CLK_AUDDIV_2,
0443 .div_mask_sft = APLL12_CK_DIV1_MASK_SFT,
0444 .div_mask = APLL12_CK_DIV1_MASK,
0445 .div_sft = APLL12_CK_DIV1_SFT,
0446 .div_apll_sel_reg = CLK_AUDDIV_0,
0447 .div_apll_sel_mask_sft = APLL_I2S1_MCK_SEL_MASK_SFT,
0448 .div_apll_sel_sft = APLL_I2S1_MCK_SEL_SFT,
0449 },
0450 [MT8192_I2S2_MCK] = {
0451 .m_sel_id = CLK_TOP_I2S2_M_SEL,
0452 .div_clk_id = CLK_TOP_APLL12_DIV2,
0453 .div_pdn_reg = CLK_AUDDIV_0,
0454 .div_pdn_mask_sft = APLL12_DIV2_PDN_MASK_SFT,
0455 .div_reg = CLK_AUDDIV_2,
0456 .div_mask_sft = APLL12_CK_DIV2_MASK_SFT,
0457 .div_mask = APLL12_CK_DIV2_MASK,
0458 .div_sft = APLL12_CK_DIV2_SFT,
0459 .div_apll_sel_reg = CLK_AUDDIV_0,
0460 .div_apll_sel_mask_sft = APLL_I2S2_MCK_SEL_MASK_SFT,
0461 .div_apll_sel_sft = APLL_I2S2_MCK_SEL_SFT,
0462 },
0463 [MT8192_I2S3_MCK] = {
0464 .m_sel_id = CLK_TOP_I2S3_M_SEL,
0465 .div_clk_id = CLK_TOP_APLL12_DIV3,
0466 .div_pdn_reg = CLK_AUDDIV_0,
0467 .div_pdn_mask_sft = APLL12_DIV3_PDN_MASK_SFT,
0468 .div_reg = CLK_AUDDIV_2,
0469 .div_mask_sft = APLL12_CK_DIV3_MASK_SFT,
0470 .div_mask = APLL12_CK_DIV3_MASK,
0471 .div_sft = APLL12_CK_DIV3_SFT,
0472 .div_apll_sel_reg = CLK_AUDDIV_0,
0473 .div_apll_sel_mask_sft = APLL_I2S3_MCK_SEL_MASK_SFT,
0474 .div_apll_sel_sft = APLL_I2S3_MCK_SEL_SFT,
0475 },
0476 [MT8192_I2S4_MCK] = {
0477 .m_sel_id = CLK_TOP_I2S4_M_SEL,
0478 .div_clk_id = CLK_TOP_APLL12_DIV4,
0479 .div_pdn_reg = CLK_AUDDIV_0,
0480 .div_pdn_mask_sft = APLL12_DIV4_PDN_MASK_SFT,
0481 .div_reg = CLK_AUDDIV_3,
0482 .div_mask_sft = APLL12_CK_DIV4_MASK_SFT,
0483 .div_mask = APLL12_CK_DIV4_MASK,
0484 .div_sft = APLL12_CK_DIV4_SFT,
0485 .div_apll_sel_reg = CLK_AUDDIV_0,
0486 .div_apll_sel_mask_sft = APLL_I2S4_MCK_SEL_MASK_SFT,
0487 .div_apll_sel_sft = APLL_I2S4_MCK_SEL_SFT,
0488 },
0489 [MT8192_I2S4_BCK] = {
0490 .m_sel_id = -1,
0491 .div_clk_id = CLK_TOP_APLL12_DIVB,
0492 .div_pdn_reg = CLK_AUDDIV_0,
0493 .div_pdn_mask_sft = APLL12_DIVB_PDN_MASK_SFT,
0494 .div_reg = CLK_AUDDIV_2,
0495 .div_mask_sft = APLL12_CK_DIVB_MASK_SFT,
0496 .div_mask = APLL12_CK_DIVB_MASK,
0497 .div_sft = APLL12_CK_DIVB_SFT,
0498 },
0499 [MT8192_I2S5_MCK] = {
0500 .m_sel_id = CLK_TOP_I2S5_M_SEL,
0501 .div_clk_id = CLK_TOP_APLL12_DIV5,
0502 .div_pdn_reg = CLK_AUDDIV_0,
0503 .div_pdn_mask_sft = APLL12_DIV5_PDN_MASK_SFT,
0504 .div_reg = CLK_AUDDIV_3,
0505 .div_mask_sft = APLL12_CK_DIV5_MASK_SFT,
0506 .div_mask = APLL12_CK_DIV5_MASK,
0507 .div_sft = APLL12_CK_DIV5_SFT,
0508 .div_apll_sel_reg = CLK_AUDDIV_0,
0509 .div_apll_sel_mask_sft = APLL_I2S5_MCK_SEL_MASK_SFT,
0510 .div_apll_sel_sft = APLL_I2S5_MCK_SEL_SFT,
0511 },
0512 [MT8192_I2S6_MCK] = {
0513 .m_sel_id = CLK_TOP_I2S6_M_SEL,
0514 .div_clk_id = CLK_TOP_APLL12_DIV6,
0515 .div_pdn_reg = CLK_AUDDIV_0,
0516 .div_pdn_mask_sft = APLL12_DIV6_PDN_MASK_SFT,
0517 .div_reg = CLK_AUDDIV_3,
0518 .div_mask_sft = APLL12_CK_DIV6_MASK_SFT,
0519 .div_mask = APLL12_CK_DIV6_MASK,
0520 .div_sft = APLL12_CK_DIV6_SFT,
0521 .div_apll_sel_reg = CLK_AUDDIV_0,
0522 .div_apll_sel_mask_sft = APLL_I2S6_MCK_SEL_MASK_SFT,
0523 .div_apll_sel_sft = APLL_I2S6_MCK_SEL_SFT,
0524 },
0525 [MT8192_I2S7_MCK] = {
0526 .m_sel_id = CLK_TOP_I2S7_M_SEL,
0527 .div_clk_id = CLK_TOP_APLL12_DIV7,
0528 .div_pdn_reg = CLK_AUDDIV_0,
0529 .div_pdn_mask_sft = APLL12_DIV7_PDN_MASK_SFT,
0530 .div_reg = CLK_AUDDIV_4,
0531 .div_mask_sft = APLL12_CK_DIV7_MASK_SFT,
0532 .div_mask = APLL12_CK_DIV7_MASK,
0533 .div_sft = APLL12_CK_DIV7_SFT,
0534 .div_apll_sel_reg = CLK_AUDDIV_0,
0535 .div_apll_sel_mask_sft = APLL_I2S7_MCK_SEL_MASK_SFT,
0536 .div_apll_sel_sft = APLL_I2S7_MCK_SEL_SFT,
0537 },
0538 [MT8192_I2S8_MCK] = {
0539 .m_sel_id = CLK_TOP_I2S8_M_SEL,
0540 .div_clk_id = CLK_TOP_APLL12_DIV8,
0541 .div_pdn_reg = CLK_AUDDIV_0,
0542 .div_pdn_mask_sft = APLL12_DIV8_PDN_MASK_SFT,
0543 .div_reg = CLK_AUDDIV_4,
0544 .div_mask_sft = APLL12_CK_DIV8_MASK_SFT,
0545 .div_mask = APLL12_CK_DIV8_MASK,
0546 .div_sft = APLL12_CK_DIV8_SFT,
0547 .div_apll_sel_reg = CLK_AUDDIV_0,
0548 .div_apll_sel_mask_sft = APLL_I2S8_MCK_SEL_MASK_SFT,
0549 .div_apll_sel_sft = APLL_I2S8_MCK_SEL_SFT,
0550 },
0551 [MT8192_I2S9_MCK] = {
0552 .m_sel_id = CLK_TOP_I2S9_M_SEL,
0553 .div_clk_id = CLK_TOP_APLL12_DIV9,
0554 .div_pdn_reg = CLK_AUDDIV_0,
0555 .div_pdn_mask_sft = APLL12_DIV9_PDN_MASK_SFT,
0556 .div_reg = CLK_AUDDIV_4,
0557 .div_mask_sft = APLL12_CK_DIV9_MASK_SFT,
0558 .div_mask = APLL12_CK_DIV9_MASK,
0559 .div_sft = APLL12_CK_DIV9_SFT,
0560 .div_apll_sel_reg = CLK_AUDDIV_0,
0561 .div_apll_sel_mask_sft = APLL_I2S9_MCK_SEL_MASK_SFT,
0562 .div_apll_sel_sft = APLL_I2S9_MCK_SEL_SFT,
0563 },
0564 };
0565
0566 int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
0567 {
0568 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0569 int apll = mt8192_get_apll_by_rate(afe, rate);
0570 int apll_clk_id = apll == MT8192_APLL1 ?
0571 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
0572 int m_sel_id = mck_div[mck_id].m_sel_id;
0573 int div_clk_id = mck_div[mck_id].div_clk_id;
0574 int ret;
0575
0576
0577 if (m_sel_id >= 0) {
0578 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
0579 if (ret) {
0580 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0581 __func__, aud_clks[m_sel_id], ret);
0582 return ret;
0583 }
0584 ret = clk_set_parent(afe_priv->clk[m_sel_id],
0585 afe_priv->clk[apll_clk_id]);
0586 if (ret) {
0587 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
0588 __func__, aud_clks[m_sel_id],
0589 aud_clks[apll_clk_id], ret);
0590 return ret;
0591 }
0592 }
0593
0594
0595 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
0596 if (ret) {
0597 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0598 __func__, aud_clks[div_clk_id], ret);
0599 return ret;
0600 }
0601 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
0602 if (ret) {
0603 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
0604 __func__, aud_clks[div_clk_id],
0605 rate, ret);
0606 return ret;
0607 }
0608
0609 return 0;
0610 }
0611
0612 void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id)
0613 {
0614 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0615 int m_sel_id = mck_div[mck_id].m_sel_id;
0616 int div_clk_id = mck_div[mck_id].div_clk_id;
0617
0618 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
0619 if (m_sel_id >= 0)
0620 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
0621 }
0622
0623 int mt8192_init_clock(struct mtk_base_afe *afe)
0624 {
0625 struct mt8192_afe_private *afe_priv = afe->platform_priv;
0626 struct device_node *of_node = afe->dev->of_node;
0627 int i = 0;
0628
0629 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
0630 GFP_KERNEL);
0631 if (!afe_priv->clk)
0632 return -ENOMEM;
0633
0634 for (i = 0; i < CLK_NUM; i++) {
0635 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
0636 if (IS_ERR(afe_priv->clk[i])) {
0637 dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
0638 __func__,
0639 aud_clks[i], PTR_ERR(afe_priv->clk[i]));
0640 afe_priv->clk[i] = NULL;
0641 }
0642 }
0643
0644 afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
0645 "mediatek,apmixedsys");
0646 if (IS_ERR(afe_priv->apmixedsys)) {
0647 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
0648 __func__, PTR_ERR(afe_priv->apmixedsys));
0649 return PTR_ERR(afe_priv->apmixedsys);
0650 }
0651
0652 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
0653 "mediatek,topckgen");
0654 if (IS_ERR(afe_priv->topckgen)) {
0655 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
0656 __func__, PTR_ERR(afe_priv->topckgen));
0657 return PTR_ERR(afe_priv->topckgen);
0658 }
0659
0660 afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
0661 "mediatek,infracfg");
0662 if (IS_ERR(afe_priv->infracfg)) {
0663 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
0664 __func__, PTR_ERR(afe_priv->infracfg));
0665 return PTR_ERR(afe_priv->infracfg);
0666 }
0667
0668 return 0;
0669 }
