mediatek/mt8186/mt8186-misc-control.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // MediaTek ALSA SoC Audio Misc Control
0004 //
0005 // Copyright (c) 2022 MediaTek Inc.
0006 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007
0008 #include <linux/delay.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/io.h>
0011 #include <linux/regmap.h>
0012 #include <sound/soc.h>
0013
0014 #include "../common/mtk-afe-fe-dai.h"
0015 #include "../common/mtk-afe-platform-driver.h"
0016 #include "mt8186-afe-common.h"
0017
0018 static const char * const mt8186_sgen_mode_str[] = {
0019     "I0I1",   "I2",     "I3I4",   "I5I6",
0020     "I7I8",   "I9I22",  "I10I11", "I12I13",
0021     "I14I21", "I15I16", "I17I18", "I19I20",
0022     "I23I24", "I25I26", "I27I28", "I33",
0023     "I34I35", "I36I37", "I38I39", "I40I41",
0024     "I42I43", "I44I45", "I46I47", "I48I49",
0025     "I56I57", "I58I59", "I60I61", "I62I63",
0026     "O0O1",   "O2",     "O3O4",   "O5O6",
0027     "O7O8",   "O9O10",  "O11",    "O12",
0028     "O13O14", "O15O16", "O17O18", "O19O20",
0029     "O21O22", "O23O24", "O25",    "O28O29",
0030     "O34",    "O35",    "O32O33", "O36O37",
0031     "O38O39", "O30O31", "O40O41", "O42O43",
0032     "O44O45", "O46O47", "O48O49", "O50O51",
0033     "O58O59", "O60O61", "O62O63", "O64O65",
0034     "O66O67", "O68O69", "O26O27", "OFF",
0035 };
0036
0037 static const int mt8186_sgen_mode_idx[] = {
0038     0, 2, 4, 6,
0039     8, 22, 10, 12,
0040     14, -1, 18, 20,
0041     24, 26, 28, 33,
0042     34, 36, 38, 40,
0043     42, 44, 46, 48,
0044     56, 58, 60, 62,
0045     128, 130, 132, 134,
0046     135, 138, 139, 140,
0047     142, 144, 166, 148,
0048     150, 152, 153, 156,
0049     162, 163, 160, 164,
0050     166, -1, 168, 170,
0051     172, 174, 176, 178,
0052     186, 188, 190, 192,
0053     194, 196, -1, -1,
0054 };
0055
0056 static const char * const mt8186_sgen_rate_str[] = {
0057     "8K", "11K", "12K", "16K",
0058     "22K", "24K", "32K", "44K",
0059     "48K", "88k", "96k", "176k",
0060     "192k"
0061 };
0062
0063 static const int mt8186_sgen_rate_idx[] = {
0064     0, 1, 2, 4,
0065     5, 6, 8, 9,
0066     10, 11, 12, 13,
0067     14
0068 };
0069
0070 /* this order must match reg bit amp_div_ch1/2 */
0071 static const char * const mt8186_sgen_amp_str[] = {
0072     "1/128", "1/64", "1/32", "1/16", "1/8", "1/4", "1/2", "1" };
0073
0074 static int mt8186_sgen_get(struct snd_kcontrol *kcontrol,
0075                struct snd_ctl_elem_value *ucontrol)
0076 {
0077     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0078     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0079     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0080
0081     ucontrol->value.integer.value[0] = afe_priv->sgen_mode;
0082
0083     return 0;
0084 }
0085
0086 static int mt8186_sgen_set(struct snd_kcontrol *kcontrol,
0087                struct snd_ctl_elem_value *ucontrol)
0088 {
0089     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0090     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0091     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0092     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0093     int mode;
0094     int mode_idx;
0095
0096     if (ucontrol->value.enumerated.item[0] >= e->items)
0097         return -EINVAL;
0098
0099     mode = ucontrol->value.integer.value[0];
0100     mode_idx = mt8186_sgen_mode_idx[mode];
0101
0102     dev_dbg(afe->dev, "%s(), mode %d, mode_idx %d\n",
0103         __func__, mode, mode_idx);
0104
0105     if (mode == afe_priv->sgen_mode)
0106         return 0;
0107
0108     if (mode_idx >= 0) {
0109         regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
0110                    INNER_LOOP_BACK_MODE_MASK_SFT,
0111                    mode_idx << INNER_LOOP_BACK_MODE_SFT);
0112         regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
0113                    DAC_EN_MASK_SFT, BIT(DAC_EN_SFT));
0114     } else {
0115         /* disable sgen */
0116         regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
0117                    DAC_EN_MASK_SFT, 0);
0118         regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
0119                    INNER_LOOP_BACK_MODE_MASK_SFT,
0120                    0x3f << INNER_LOOP_BACK_MODE_SFT);
0121     }
0122
0123     afe_priv->sgen_mode = mode;
0124
0125     return 1;
0126 }
0127
0128 static int mt8186_sgen_rate_get(struct snd_kcontrol *kcontrol,
0129                 struct snd_ctl_elem_value *ucontrol)
0130 {
0131     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0132     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0133     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0134
0135     ucontrol->value.integer.value[0] = afe_priv->sgen_rate;
0136
0137     return 0;
0138 }
0139
0140 static int mt8186_sgen_rate_set(struct snd_kcontrol *kcontrol,
0141                 struct snd_ctl_elem_value *ucontrol)
0142 {
0143     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0144     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0145     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0146     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0147     int rate;
0148
0149     if (ucontrol->value.enumerated.item[0] >= e->items)
0150         return -EINVAL;
0151
0152     rate = ucontrol->value.integer.value[0];
0153
0154     dev_dbg(afe->dev, "%s(), rate %d\n", __func__, rate);
0155
0156     if (rate == afe_priv->sgen_rate)
0157         return 0;
0158
0159     regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
0160                SINE_MODE_CH1_MASK_SFT,
0161                mt8186_sgen_rate_idx[rate] << SINE_MODE_CH1_SFT);
0162
0163     regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
0164                SINE_MODE_CH2_MASK_SFT,
0165                mt8186_sgen_rate_idx[rate] << SINE_MODE_CH2_SFT);
0166
0167     afe_priv->sgen_rate = rate;
0168
0169     return 1;
0170 }
0171
0172 static int mt8186_sgen_amplitude_get(struct snd_kcontrol *kcontrol,
0173                      struct snd_ctl_elem_value *ucontrol)
0174 {
0175     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0176     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0177     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0178
0179     ucontrol->value.integer.value[0] = afe_priv->sgen_amplitude;
0180     return 0;
0181 }
0182
0183 static int mt8186_sgen_amplitude_set(struct snd_kcontrol *kcontrol,
0184                      struct snd_ctl_elem_value *ucontrol)
0185 {
0186     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0187     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0188     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0189     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0190     int amplitude;
0191
0192     if (ucontrol->value.enumerated.item[0] >= e->items)
0193         return -EINVAL;
0194
0195     amplitude = ucontrol->value.integer.value[0];
0196     if (amplitude > AMP_DIV_CH1_MASK) {
0197         dev_err(afe->dev, "%s(), amplitude %d invalid\n",
0198             __func__, amplitude);
0199         return -EINVAL;
0200     }
0201
0202     dev_dbg(afe->dev, "%s(), amplitude %d\n", __func__, amplitude);
0203
0204     if (amplitude == afe_priv->sgen_amplitude)
0205         return 0;
0206
0207     regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
0208                AMP_DIV_CH1_MASK_SFT,
0209                amplitude << AMP_DIV_CH1_SFT);
0210     regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
0211                AMP_DIV_CH2_MASK_SFT,
0212                amplitude << AMP_DIV_CH2_SFT);
0213
0214     afe_priv->sgen_amplitude = amplitude;
0215
0216     return 1;
0217 }
0218
0219 static const struct soc_enum mt8186_afe_sgen_enum[] = {
0220     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_sgen_mode_str),
0221                 mt8186_sgen_mode_str),
0222     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_sgen_rate_str),
0223                 mt8186_sgen_rate_str),
0224     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_sgen_amp_str),
0225                 mt8186_sgen_amp_str),
0226 };
0227
0228 static const struct snd_kcontrol_new mt8186_afe_sgen_controls[] = {
0229     SOC_ENUM_EXT("Audio_SineGen_Switch", mt8186_afe_sgen_enum[0],
0230              mt8186_sgen_get, mt8186_sgen_set),
0231     SOC_ENUM_EXT("Audio_SineGen_SampleRate", mt8186_afe_sgen_enum[1],
0232              mt8186_sgen_rate_get, mt8186_sgen_rate_set),
0233     SOC_ENUM_EXT("Audio_SineGen_Amplitude", mt8186_afe_sgen_enum[2],
0234              mt8186_sgen_amplitude_get, mt8186_sgen_amplitude_set),
0235     SOC_SINGLE("Audio_SineGen_Mute_Ch1", AFE_SINEGEN_CON0,
0236            MUTE_SW_CH1_MASK_SFT, MUTE_SW_CH1_MASK, 0),
0237     SOC_SINGLE("Audio_SineGen_Mute_Ch2", AFE_SINEGEN_CON0,
0238            MUTE_SW_CH2_MASK_SFT, MUTE_SW_CH2_MASK, 0),
0239     SOC_SINGLE("Audio_SineGen_Freq_Div_Ch1", AFE_SINEGEN_CON0,
0240            FREQ_DIV_CH1_SFT, FREQ_DIV_CH1_MASK, 0),
0241     SOC_SINGLE("Audio_SineGen_Freq_Div_Ch2", AFE_SINEGEN_CON0,
0242            FREQ_DIV_CH2_SFT, FREQ_DIV_CH2_MASK, 0),
0243 };
0244
0245 int mt8186_add_misc_control(struct snd_soc_component *component)
0246 {
0247     snd_soc_add_component_controls(component,
0248                        mt8186_afe_sgen_controls,
0249                        ARRAY_SIZE(mt8186_afe_sgen_controls));
0250
0251     return 0;
0252 }