mediatek/mt8186/mt8186-dai-i2s.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // MediaTek ALSA SoC Audio DAI I2S Control
0004 //
0005 // Copyright (c) 2022 MediaTek Inc.
0006 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007
0008 #include <linux/bitops.h>
0009 #include <linux/regmap.h>
0010 #include <sound/pcm_params.h>
0011 #include "mt8186-afe-clk.h"
0012 #include "mt8186-afe-common.h"
0013 #include "mt8186-afe-gpio.h"
0014 #include "mt8186-interconnection.h"
0015
0016 enum {
0017     I2S_FMT_EIAJ = 0,
0018     I2S_FMT_I2S = 1,
0019 };
0020
0021 enum {
0022     I2S_WLEN_16_BIT = 0,
0023     I2S_WLEN_32_BIT = 1,
0024 };
0025
0026 enum {
0027     I2S_HD_NORMAL = 0,
0028     I2S_HD_LOW_JITTER = 1,
0029 };
0030
0031 enum {
0032     I2S1_SEL_O28_O29 = 0,
0033     I2S1_SEL_O03_O04 = 1,
0034 };
0035
0036 enum {
0037     I2S_IN_PAD_CONNSYS = 0,
0038     I2S_IN_PAD_IO_MUX = 1,
0039 };
0040
0041 struct mtk_afe_i2s_priv {
0042     int id;
0043     int rate; /* for determine which apll to use */
0044     int low_jitter_en;
0045     int master; /* only i2s0 has slave mode*/
0046
0047     const char *share_property_name;
0048     int share_i2s_id;
0049
0050     int mclk_id;
0051     int mclk_rate;
0052     int mclk_apll;
0053 };
0054
0055 static unsigned int get_i2s_wlen(snd_pcm_format_t format)
0056 {
0057     return snd_pcm_format_physical_width(format) <= 16 ?
0058            I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
0059 }
0060
0061 #define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux"
0062 #define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux"
0063 #define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux"
0064 #define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux"
0065 #define MTK_AFE_I2S0_SRC_KCONTROL_NAME "I2S0_SRC_Mux"
0066
0067 #define I2S0_HD_EN_W_NAME "I2S0_HD_EN"
0068 #define I2S1_HD_EN_W_NAME "I2S1_HD_EN"
0069 #define I2S2_HD_EN_W_NAME "I2S2_HD_EN"
0070 #define I2S3_HD_EN_W_NAME "I2S3_HD_EN"
0071
0072 #define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN"
0073 #define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN"
0074 #define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN"
0075 #define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN"
0076
0077 static int get_i2s_id_by_name(struct mtk_base_afe *afe,
0078                   const char *name)
0079 {
0080     if (strncmp(name, "I2S0", 4) == 0)
0081         return MT8186_DAI_I2S_0;
0082     else if (strncmp(name, "I2S1", 4) == 0)
0083         return MT8186_DAI_I2S_1;
0084     else if (strncmp(name, "I2S2", 4) == 0)
0085         return MT8186_DAI_I2S_2;
0086     else if (strncmp(name, "I2S3", 4) == 0)
0087         return MT8186_DAI_I2S_3;
0088
0089     return -EINVAL;
0090 }
0091
0092 static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
0093                              const char *name)
0094 {
0095     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0096     int dai_id = get_i2s_id_by_name(afe, name);
0097
0098     if (dai_id < 0)
0099         return NULL;
0100
0101     return afe_priv->dai_priv[dai_id];
0102 }
0103
0104 /* low jitter control */
0105 static const char * const mt8186_i2s_hd_str[] = {
0106     "Normal", "Low_Jitter"
0107 };
0108
0109 static const struct soc_enum mt8186_i2s_enum[] = {
0110     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_i2s_hd_str),
0111                 mt8186_i2s_hd_str),
0112 };
0113
0114 static int mt8186_i2s_hd_get(struct snd_kcontrol *kcontrol,
0115                  struct snd_ctl_elem_value *ucontrol)
0116 {
0117     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0118     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0119     struct mtk_afe_i2s_priv *i2s_priv;
0120
0121     i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
0122     ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
0123
0124     return 0;
0125 }
0126
0127 static int mt8186_i2s_hd_set(struct snd_kcontrol *kcontrol,
0128                  struct snd_ctl_elem_value *ucontrol)
0129 {
0130     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0131     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0132     struct mtk_afe_i2s_priv *i2s_priv;
0133     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0134     int hd_en;
0135
0136     if (ucontrol->value.enumerated.item[0] >= e->items)
0137         return -EINVAL;
0138
0139     hd_en = ucontrol->value.integer.value[0];
0140
0141     dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n",
0142         __func__, kcontrol->id.name, hd_en);
0143
0144     i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
0145     if (i2s_priv->low_jitter_en == hd_en)
0146         return 0;
0147
0148     i2s_priv->low_jitter_en = hd_en;
0149
0150     return 1;
0151 }
0152
0153 static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
0154     SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8186_i2s_enum[0],
0155              mt8186_i2s_hd_get, mt8186_i2s_hd_set),
0156     SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8186_i2s_enum[0],
0157              mt8186_i2s_hd_get, mt8186_i2s_hd_set),
0158     SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8186_i2s_enum[0],
0159              mt8186_i2s_hd_get, mt8186_i2s_hd_set),
0160     SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8186_i2s_enum[0],
0161              mt8186_i2s_hd_get, mt8186_i2s_hd_set),
0162 };
0163
0164 /* dai component */
0165 /* i2s virtual mux to output widget */
0166 static const char * const i2s_mux_map[] = {
0167     "Normal", "Dummy_Widget",
0168 };
0169
0170 static int i2s_mux_map_value[] = {
0171     0, 1,
0172 };
0173
0174 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum,
0175                           SND_SOC_NOPM,
0176                           0,
0177                           1,
0178                           i2s_mux_map,
0179                           i2s_mux_map_value);
0180
0181 static const struct snd_kcontrol_new i2s0_in_mux_control =
0182     SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum);
0183
0184 static const struct snd_kcontrol_new i2s1_out_mux_control =
0185     SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum);
0186
0187 static const struct snd_kcontrol_new i2s2_in_mux_control =
0188     SOC_DAPM_ENUM("I2S2 In Select", i2s_mux_map_enum);
0189
0190 static const struct snd_kcontrol_new i2s3_out_mux_control =
0191     SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum);
0192
0193 /* i2s in lpbk */
0194 static const char * const i2s_lpbk_mux_map[] = {
0195     "Normal", "Lpbk",
0196 };
0197
0198 static int i2s_lpbk_mux_map_value[] = {
0199     0, 1,
0200 };
0201
0202 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum,
0203                           AFE_I2S_CON,
0204                           I2S_LOOPBACK_SFT,
0205                           1,
0206                           i2s_lpbk_mux_map,
0207                           i2s_lpbk_mux_map_value);
0208
0209 static const struct snd_kcontrol_new i2s0_lpbk_mux_control =
0210     SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum);
0211
0212 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum,
0213                           AFE_I2S_CON2,
0214                           I2S3_LOOPBACK_SFT,
0215                           1,
0216                           i2s_lpbk_mux_map,
0217                           i2s_lpbk_mux_map_value);
0218
0219 static const struct snd_kcontrol_new i2s2_lpbk_mux_control =
0220     SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum);
0221
0222 /* interconnection */
0223 static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = {
0224     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN0,
0225                     I_DL1_CH1, 1, 0),
0226     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN0,
0227                     I_DL2_CH1, 1, 0),
0228     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN0,
0229                     I_DL3_CH1, 1, 0),
0230     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN0,
0231                     I_DL12_CH1, 1, 0),
0232     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN0,
0233                     I_DL12_CH3, 1, 0),
0234     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN0_1,
0235                     I_DL6_CH1, 1, 0),
0236     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN0_1,
0237                     I_DL4_CH1, 1, 0),
0238     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN0_1,
0239                     I_DL5_CH1, 1, 0),
0240     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN0_1,
0241                     I_DL8_CH1, 1, 0),
0242     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN0,
0243                     I_GAIN1_OUT_CH1, 1, 0),
0244     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN0,
0245                     I_ADDA_UL_CH1, 1, 0),
0246     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN0,
0247                     I_ADDA_UL_CH2, 1, 0),
0248     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN0,
0249                     I_ADDA_UL_CH3, 1, 0),
0250     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN0,
0251                     I_PCM_1_CAP_CH1, 1, 0),
0252     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN0_1,
0253                     I_SRC_1_OUT_CH1, 1, 0),
0254 };
0255
0256 static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = {
0257     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN1,
0258                     I_DL1_CH2, 1, 0),
0259     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN1,
0260                     I_DL2_CH2, 1, 0),
0261     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN1,
0262                     I_DL3_CH2, 1, 0),
0263     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN1,
0264                     I_DL12_CH2, 1, 0),
0265     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN1,
0266                     I_DL12_CH4, 1, 0),
0267     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN1_1,
0268                     I_DL6_CH2, 1, 0),
0269     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN1_1,
0270                     I_DL4_CH2, 1, 0),
0271     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN1_1,
0272                     I_DL5_CH2, 1, 0),
0273     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN1_1,
0274                     I_DL8_CH2, 1, 0),
0275     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN1,
0276                     I_GAIN1_OUT_CH2, 1, 0),
0277     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN1,
0278                     I_ADDA_UL_CH1, 1, 0),
0279     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN1,
0280                     I_ADDA_UL_CH2, 1, 0),
0281     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN1,
0282                     I_ADDA_UL_CH3, 1, 0),
0283     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN1,
0284                     I_PCM_1_CAP_CH2, 1, 0),
0285     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN1,
0286                     I_PCM_2_CAP_CH2, 1, 0),
0287     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN1_1,
0288                     I_SRC_1_OUT_CH2, 1, 0),
0289 };
0290
0291 static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = {
0292     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN28,
0293                     I_DL1_CH1, 1, 0),
0294     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN28,
0295                     I_DL2_CH1, 1, 0),
0296     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN28,
0297                     I_DL3_CH1, 1, 0),
0298     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN28,
0299                     I_DL12_CH1, 1, 0),
0300     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN28,
0301                     I_DL12_CH3, 1, 0),
0302     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN28_1,
0303                     I_DL6_CH1, 1, 0),
0304     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN28_1,
0305                     I_DL4_CH1, 1, 0),
0306     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN28_1,
0307                     I_DL5_CH1, 1, 0),
0308     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN28_1,
0309                     I_DL8_CH1, 1, 0),
0310     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN28,
0311                     I_GAIN1_OUT_CH1, 1, 0),
0312     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN28,
0313                     I_ADDA_UL_CH1, 1, 0),
0314     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN28,
0315                     I_PCM_1_CAP_CH1, 1, 0),
0316     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN28_1,
0317                     I_SRC_1_OUT_CH1, 1, 0),
0318 };
0319
0320 static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = {
0321     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN29,
0322                     I_DL1_CH2, 1, 0),
0323     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN29,
0324                     I_DL2_CH2, 1, 0),
0325     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN29,
0326                     I_DL3_CH2, 1, 0),
0327     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN29,
0328                     I_DL12_CH2, 1, 0),
0329     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN29,
0330                     I_DL12_CH4, 1, 0),
0331     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN29_1,
0332                     I_DL6_CH2, 1, 0),
0333     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN29_1,
0334                     I_DL4_CH2, 1, 0),
0335     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN29_1,
0336                     I_DL5_CH2, 1, 0),
0337     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN29_1,
0338                     I_DL8_CH2, 1, 0),
0339     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN29,
0340                     I_GAIN1_OUT_CH2, 1, 0),
0341     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN29,
0342                     I_ADDA_UL_CH2, 1, 0),
0343     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN29,
0344                     I_PCM_1_CAP_CH2, 1, 0),
0345     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN29,
0346                     I_PCM_2_CAP_CH2, 1, 0),
0347     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN29_1,
0348                     I_SRC_1_OUT_CH2, 1, 0),
0349 };
0350
0351 enum {
0352     SUPPLY_SEQ_APLL,
0353     SUPPLY_SEQ_I2S_MCLK_EN,
0354     SUPPLY_SEQ_I2S_HD_EN,
0355     SUPPLY_SEQ_I2S_EN,
0356 };
0357
0358 static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w,
0359                 struct snd_kcontrol *kcontrol,
0360                 int event)
0361 {
0362     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0363     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0364     struct mtk_afe_i2s_priv *i2s_priv;
0365
0366     i2s_priv = get_i2s_priv_by_name(afe, w->name);
0367
0368     dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
0369         __func__, w->name, event);
0370
0371     switch (event) {
0372     case SND_SOC_DAPM_PRE_PMU:
0373         mt8186_afe_gpio_request(afe->dev, true, i2s_priv->id, 0);
0374         break;
0375     case SND_SOC_DAPM_POST_PMD:
0376         mt8186_afe_gpio_request(afe->dev, false, i2s_priv->id, 0);
0377         break;
0378     default:
0379         break;
0380     }
0381
0382     return 0;
0383 }
0384
0385 static int mtk_apll_event(struct snd_soc_dapm_widget *w,
0386               struct snd_kcontrol *kcontrol,
0387               int event)
0388 {
0389     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0390     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0391
0392     dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
0393         __func__, w->name, event);
0394
0395     switch (event) {
0396     case SND_SOC_DAPM_PRE_PMU:
0397         if (strcmp(w->name, APLL1_W_NAME) == 0)
0398             mt8186_apll1_enable(afe);
0399         else
0400             mt8186_apll2_enable(afe);
0401         break;
0402     case SND_SOC_DAPM_POST_PMD:
0403         if (strcmp(w->name, APLL1_W_NAME) == 0)
0404             mt8186_apll1_disable(afe);
0405         else
0406             mt8186_apll2_disable(afe);
0407         break;
0408     default:
0409         break;
0410     }
0411
0412     return 0;
0413 }
0414
0415 static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
0416                  struct snd_kcontrol *kcontrol,
0417                  int event)
0418 {
0419     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0420     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0421     struct mtk_afe_i2s_priv *i2s_priv;
0422
0423     dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
0424         __func__, w->name, event);
0425
0426     i2s_priv = get_i2s_priv_by_name(afe, w->name);
0427
0428     switch (event) {
0429     case SND_SOC_DAPM_PRE_PMU:
0430         mt8186_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
0431         break;
0432     case SND_SOC_DAPM_POST_PMD:
0433         i2s_priv->mclk_rate = 0;
0434         mt8186_mck_disable(afe, i2s_priv->mclk_id);
0435         break;
0436     default:
0437         break;
0438     }
0439
0440     return 0;
0441 }
0442
0443 static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
0444     SND_SOC_DAPM_INPUT("CONNSYS"),
0445
0446     SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0,
0447                mtk_i2s1_ch1_mix,
0448                ARRAY_SIZE(mtk_i2s1_ch1_mix)),
0449     SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0,
0450                mtk_i2s1_ch2_mix,
0451                ARRAY_SIZE(mtk_i2s1_ch2_mix)),
0452
0453     SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0,
0454                mtk_i2s3_ch1_mix,
0455                ARRAY_SIZE(mtk_i2s3_ch1_mix)),
0456     SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0,
0457                mtk_i2s3_ch2_mix,
0458                ARRAY_SIZE(mtk_i2s3_ch2_mix)),
0459
0460     /* i2s en*/
0461     SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN,
0462                   AFE_I2S_CON, I2S_EN_SFT, 0,
0463                   mtk_i2s_en_event,
0464                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0465     SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN,
0466                   AFE_I2S_CON1, I2S_EN_SFT, 0,
0467                   mtk_i2s_en_event,
0468                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0469     SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN,
0470                   AFE_I2S_CON2, I2S_EN_SFT, 0,
0471                   mtk_i2s_en_event,
0472                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0473     SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN,
0474                   AFE_I2S_CON3, I2S_EN_SFT, 0,
0475                   mtk_i2s_en_event,
0476                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0477     /* i2s hd en */
0478     SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
0479                   AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL,
0480                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0481     SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
0482                   AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL,
0483                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0484     SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
0485                   AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL,
0486                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0487     SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
0488                   AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL,
0489                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0490
0491     /* i2s mclk en */
0492     SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
0493                   SND_SOC_NOPM, 0, 0,
0494                   mtk_mclk_en_event,
0495                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0496     SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
0497                   SND_SOC_NOPM, 0, 0,
0498                   mtk_mclk_en_event,
0499                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0500     SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
0501                   SND_SOC_NOPM, 0, 0,
0502                   mtk_mclk_en_event,
0503                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0504     SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
0505                   SND_SOC_NOPM, 0, 0,
0506                   mtk_mclk_en_event,
0507                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0508
0509     /* apll */
0510     SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
0511                   SND_SOC_NOPM, 0, 0,
0512                   mtk_apll_event,
0513                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0514     SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
0515                   SND_SOC_NOPM, 0, 0,
0516                   mtk_apll_event,
0517                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0518
0519     /* allow i2s on without codec on */
0520     SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"),
0521     SND_SOC_DAPM_MUX("I2S1_Out_Mux",
0522              SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control),
0523     SND_SOC_DAPM_MUX("I2S3_Out_Mux",
0524              SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control),
0525     SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"),
0526     SND_SOC_DAPM_MUX("I2S0_In_Mux",
0527              SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control),
0528     SND_SOC_DAPM_MUX("I2S2_In_Mux",
0529              SND_SOC_NOPM, 0, 0, &i2s2_in_mux_control),
0530
0531     /* i2s in lpbk */
0532     SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux",
0533              SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control),
0534     SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux",
0535              SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control),
0536 };
0537
0538 static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
0539                      struct snd_soc_dapm_widget *sink)
0540 {
0541     struct snd_soc_dapm_widget *w = sink;
0542     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0543     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0544     struct mtk_afe_i2s_priv *i2s_priv;
0545
0546     i2s_priv = get_i2s_priv_by_name(afe, sink->name);
0547     if (i2s_priv->share_i2s_id < 0)
0548         return 0;
0549
0550     return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
0551 }
0552
0553 static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
0554                   struct snd_soc_dapm_widget *sink)
0555 {
0556     struct snd_soc_dapm_widget *w = sink;
0557     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0558     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0559     struct mtk_afe_i2s_priv *i2s_priv;
0560
0561     i2s_priv = get_i2s_priv_by_name(afe, sink->name);
0562     if (get_i2s_id_by_name(afe, sink->name) ==
0563         get_i2s_id_by_name(afe, source->name))
0564         return i2s_priv->low_jitter_en;
0565
0566     /* check if share i2s need hd en */
0567     if (i2s_priv->share_i2s_id < 0)
0568         return 0;
0569
0570     if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
0571         return i2s_priv->low_jitter_en;
0572
0573     return 0;
0574 }
0575
0576 static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
0577                     struct snd_soc_dapm_widget *sink)
0578 {
0579     struct snd_soc_dapm_widget *w = sink;
0580     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0581     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0582     struct mtk_afe_i2s_priv *i2s_priv;
0583     int cur_apll;
0584     int i2s_need_apll;
0585
0586     i2s_priv = get_i2s_priv_by_name(afe, w->name);
0587     /* which apll */
0588     cur_apll = mt8186_get_apll_by_name(afe, source->name);
0589     /* choose APLL from i2s rate */
0590     i2s_need_apll = mt8186_get_apll_by_rate(afe, i2s_priv->rate);
0591
0592     return (i2s_need_apll == cur_apll) ? 1 : 0;
0593 }
0594
0595 static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
0596                     struct snd_soc_dapm_widget *sink)
0597 {
0598     struct snd_soc_dapm_widget *w = sink;
0599     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0600     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0601     struct mtk_afe_i2s_priv *i2s_priv;
0602
0603     i2s_priv = get_i2s_priv_by_name(afe, sink->name);
0604     if (get_i2s_id_by_name(afe, sink->name) ==
0605         get_i2s_id_by_name(afe, source->name))
0606         return (i2s_priv->mclk_rate > 0) ? 1 : 0;
0607
0608     /* check if share i2s need mclk */
0609     if (i2s_priv->share_i2s_id < 0)
0610         return 0;
0611
0612     if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
0613         return (i2s_priv->mclk_rate > 0) ? 1 : 0;
0614
0615     return 0;
0616 }
0617
0618 static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
0619                      struct snd_soc_dapm_widget *sink)
0620 {
0621     struct snd_soc_dapm_widget *w = sink;
0622     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0623     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0624     struct mtk_afe_i2s_priv *i2s_priv;
0625     int cur_apll;
0626
0627     i2s_priv = get_i2s_priv_by_name(afe, w->name);
0628     /* which apll */
0629     cur_apll = mt8186_get_apll_by_name(afe, source->name);
0630
0631     return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0;
0632 }
0633
0634 static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
0635     {"Connsys I2S", NULL, "CONNSYS"},
0636
0637     /* i2s0 */
0638     {"I2S0", NULL, "I2S0_EN"},
0639     {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
0640     {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
0641     {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
0642
0643     {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0644     {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0645     {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0646     {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0647     {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
0648     {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
0649
0650     {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0651     {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0652     {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0653     {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0654     {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
0655     {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
0656
0657     /* i2s1 */
0658     {"I2S1_CH1", "DL1_CH1 Switch", "DL1"},
0659     {"I2S1_CH2", "DL1_CH2 Switch", "DL1"},
0660
0661     {"I2S1_CH1", "DL2_CH1 Switch", "DL2"},
0662     {"I2S1_CH2", "DL2_CH2 Switch", "DL2"},
0663
0664     {"I2S1_CH1", "DL3_CH1 Switch", "DL3"},
0665     {"I2S1_CH2", "DL3_CH2 Switch", "DL3"},
0666
0667     {"I2S1_CH1", "DL12_CH1 Switch", "DL12"},
0668     {"I2S1_CH2", "DL12_CH2 Switch", "DL12"},
0669
0670     {"I2S1_CH1", "DL12_CH3 Switch", "DL12"},
0671     {"I2S1_CH2", "DL12_CH4 Switch", "DL12"},
0672
0673     {"I2S1_CH1", "DL6_CH1 Switch", "DL6"},
0674     {"I2S1_CH2", "DL6_CH2 Switch", "DL6"},
0675
0676     {"I2S1_CH1", "DL4_CH1 Switch", "DL4"},
0677     {"I2S1_CH2", "DL4_CH2 Switch", "DL4"},
0678
0679     {"I2S1_CH1", "DL5_CH1 Switch", "DL5"},
0680     {"I2S1_CH2", "DL5_CH2 Switch", "DL5"},
0681
0682     {"I2S1_CH1", "DL8_CH1 Switch", "DL8"},
0683     {"I2S1_CH2", "DL8_CH2 Switch", "DL8"},
0684
0685     {"I2S1", NULL, "I2S1_CH1"},
0686     {"I2S1", NULL, "I2S1_CH2"},
0687
0688     {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
0689     {"I2S1", NULL, "I2S1_EN"},
0690     {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
0691     {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
0692
0693     {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0694     {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0695     {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0696     {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0697     {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
0698     {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
0699
0700     {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0701     {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0702     {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0703     {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0704     {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
0705     {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
0706
0707     /* i2s2 */
0708     {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
0709     {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
0710     {"I2S2", NULL, "I2S2_EN"},
0711     {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
0712
0713     {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0714     {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0715     {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0716     {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0717     {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
0718     {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
0719
0720     {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0721     {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0722     {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0723     {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0724     {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
0725     {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
0726
0727     /* i2s3 */
0728     {"I2S3_CH1", "DL1_CH1 Switch", "DL1"},
0729     {"I2S3_CH2", "DL1_CH2 Switch", "DL1"},
0730
0731     {"I2S3_CH1", "DL2_CH1 Switch", "DL2"},
0732     {"I2S3_CH2", "DL2_CH2 Switch", "DL2"},
0733
0734     {"I2S3_CH1", "DL3_CH1 Switch", "DL3"},
0735     {"I2S3_CH2", "DL3_CH2 Switch", "DL3"},
0736
0737     {"I2S3_CH1", "DL12_CH1 Switch", "DL12"},
0738     {"I2S3_CH2", "DL12_CH2 Switch", "DL12"},
0739
0740     {"I2S3_CH1", "DL12_CH3 Switch", "DL12"},
0741     {"I2S3_CH2", "DL12_CH4 Switch", "DL12"},
0742
0743     {"I2S3_CH1", "DL6_CH1 Switch", "DL6"},
0744     {"I2S3_CH2", "DL6_CH2 Switch", "DL6"},
0745
0746     {"I2S3_CH1", "DL4_CH1 Switch", "DL4"},
0747     {"I2S3_CH2", "DL4_CH2 Switch", "DL4"},
0748
0749     {"I2S3_CH1", "DL5_CH1 Switch", "DL5"},
0750     {"I2S3_CH2", "DL5_CH2 Switch", "DL5"},
0751
0752     {"I2S3_CH1", "DL8_CH1 Switch", "DL8"},
0753     {"I2S3_CH2", "DL8_CH2 Switch", "DL8"},
0754
0755     {"I2S3", NULL, "I2S3_CH1"},
0756     {"I2S3", NULL, "I2S3_CH2"},
0757
0758     {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
0759     {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
0760     {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
0761     {"I2S3", NULL, "I2S3_EN"},
0762
0763     {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0764     {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0765     {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0766     {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
0767     {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
0768     {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
0769
0770     {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0771     {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0772     {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0773     {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
0774     {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
0775     {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
0776
0777     /* allow i2s on without codec on */
0778     {"I2S0", NULL, "I2S0_In_Mux"},
0779     {"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
0780
0781     {"I2S1_Out_Mux", "Dummy_Widget", "I2S1"},
0782     {"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"},
0783
0784     {"I2S2", NULL, "I2S2_In_Mux"},
0785     {"I2S2_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
0786
0787     {"I2S3_Out_Mux", "Dummy_Widget", "I2S3"},
0788     {"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"},
0789
0790     /* i2s in lpbk */
0791     {"I2S0_Lpbk_Mux", "Lpbk", "I2S3"},
0792     {"I2S2_Lpbk_Mux", "Lpbk", "I2S1"},
0793     {"I2S0", NULL, "I2S0_Lpbk_Mux"},
0794     {"I2S2", NULL, "I2S2_Lpbk_Mux"},
0795 };
0796
0797 /* dai ops */
0798 static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream,
0799                      struct snd_pcm_hw_params *params,
0800                      struct snd_soc_dai *dai)
0801 {
0802     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0803     unsigned int rate = params_rate(params);
0804     unsigned int rate_reg = mt8186_rate_transform(afe->dev,
0805                               rate, dai->id);
0806     unsigned int i2s_con = 0;
0807
0808     dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
0809         __func__, dai->id, substream->stream, rate);
0810
0811     /* non-inverse, i2s mode, slave, 16bits, from connsys */
0812     i2s_con |= 0 << INV_PAD_CTRL_SFT;
0813     i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
0814     i2s_con |= 1 << I2S_SRC_SFT;
0815     i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT;
0816     i2s_con |= 0 << I2SIN_PAD_SEL_SFT;
0817     regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con);
0818
0819     /* use asrc */
0820     regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
0821                I2S_BYPSRC_MASK_SFT, 0);
0822
0823     /* slave mode, set i2s for asrc */
0824     regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
0825                I2S_MODE_MASK_SFT, rate_reg << I2S_MODE_SFT);
0826
0827     if (rate == 44100)
0828         regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1b9000);
0829     else if (rate == 32000)
0830         regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000);
0831     else
0832         regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1e0000);
0833
0834     /* Calibration setting */
0835     regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x140000);
0836     regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x36000);
0837     regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x2fc00);
0838     regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x7ef4);
0839     regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0xff5986);
0840
0841     /* 0:Stereo 1:Mono */
0842     regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
0843                CHSET_IS_MONO_MASK_SFT, 0);
0844
0845     return 0;
0846 }
0847
0848 static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream,
0849                        int cmd, struct snd_soc_dai *dai)
0850 {
0851     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0852     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0853
0854     dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n",
0855         __func__, cmd, substream->stream);
0856
0857     switch (cmd) {
0858     case SNDRV_PCM_TRIGGER_START:
0859     case SNDRV_PCM_TRIGGER_RESUME:
0860         /* i2s enable */
0861         regmap_update_bits(afe->regmap,
0862                    AFE_CONNSYS_I2S_CON,
0863                    I2S_EN_MASK_SFT,
0864                    BIT(I2S_EN_SFT));
0865
0866         /* calibrator enable */
0867         regmap_update_bits(afe->regmap,
0868                    AFE_ASRC_2CH_CON5,
0869                    CALI_EN_MASK_SFT,
0870                    BIT(CALI_EN_SFT));
0871
0872         /* asrc enable */
0873         regmap_update_bits(afe->regmap,
0874                    AFE_ASRC_2CH_CON0,
0875                    CON0_CHSET_STR_CLR_MASK_SFT,
0876                    BIT(CON0_CHSET_STR_CLR_SFT));
0877         regmap_update_bits(afe->regmap,
0878                    AFE_ASRC_2CH_CON0,
0879                    CON0_ASM_ON_MASK_SFT,
0880                    BIT(CON0_ASM_ON_SFT));
0881
0882         afe_priv->dai_on[dai->id] = true;
0883         return 0;
0884     case SNDRV_PCM_TRIGGER_STOP:
0885     case SNDRV_PCM_TRIGGER_SUSPEND:
0886         regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
0887                    CON0_ASM_ON_MASK_SFT, 0);
0888         regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5,
0889                    CALI_EN_MASK_SFT, 0);
0890
0891         /* i2s disable */
0892         regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
0893                    I2S_EN_MASK_SFT, 0);
0894
0895         /* bypass asrc */
0896         regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
0897                    I2S_BYPSRC_MASK_SFT, BIT(I2S_BYPSRC_SFT));
0898
0899         afe_priv->dai_on[dai->id] = false;
0900         return 0;
0901     default:
0902         return -EINVAL;
0903     }
0904     return 0;
0905 }
0906
0907 static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = {
0908     .hw_params = mtk_dai_connsys_i2s_hw_params,
0909     .trigger = mtk_dai_connsys_i2s_trigger,
0910 };
0911
0912 /* i2s */
0913 static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
0914                   struct snd_pcm_hw_params *params,
0915                   int i2s_id)
0916 {
0917     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0918     struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id];
0919
0920     unsigned int rate = params_rate(params);
0921     unsigned int rate_reg = mt8186_rate_transform(afe->dev,
0922                               rate, i2s_id);
0923     snd_pcm_format_t format = params_format(params);
0924     unsigned int i2s_con = 0;
0925     int ret;
0926
0927     dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n",
0928         __func__, i2s_id, rate, format);
0929
0930     i2s_priv->rate = rate;
0931
0932     switch (i2s_id) {
0933     case MT8186_DAI_I2S_0:
0934         i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
0935         i2s_con |= rate_reg << I2S_OUT_MODE_SFT;
0936         i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
0937         i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
0938         regmap_update_bits(afe->regmap, AFE_I2S_CON,
0939                    0xffffeffa, i2s_con);
0940         break;
0941     case MT8186_DAI_I2S_1:
0942         i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT;
0943         i2s_con |= rate_reg << I2S2_OUT_MODE_SFT;
0944         i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT;
0945         i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT;
0946         regmap_update_bits(afe->regmap, AFE_I2S_CON1,
0947                    0xffffeffa, i2s_con);
0948         break;
0949     case MT8186_DAI_I2S_2:
0950         i2s_con = 8 << I2S3_UPDATE_WORD_SFT;
0951         i2s_con |= rate_reg << I2S3_OUT_MODE_SFT;
0952         i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT;
0953         i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT;
0954         regmap_update_bits(afe->regmap, AFE_I2S_CON2,
0955                    0xffffeffa, i2s_con);
0956         break;
0957     case MT8186_DAI_I2S_3:
0958         i2s_con = rate_reg << I2S4_OUT_MODE_SFT;
0959         i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT;
0960         i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT;
0961         regmap_update_bits(afe->regmap, AFE_I2S_CON3,
0962                    0xffffeffa, i2s_con);
0963         break;
0964     default:
0965         dev_err(afe->dev, "%s(), id %d not support\n",
0966             __func__, i2s_id);
0967         return -EINVAL;
0968     }
0969
0970     /* set share i2s */
0971     if (i2s_priv && i2s_priv->share_i2s_id >= 0) {
0972         ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
0973         if (ret)
0974             return ret;
0975     }
0976
0977     return 0;
0978 }
0979
0980 static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
0981                  struct snd_pcm_hw_params *params,
0982                  struct snd_soc_dai *dai)
0983 {
0984     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0985
0986     return mtk_dai_i2s_config(afe, params, dai->id);
0987 }
0988
0989 static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
0990                   int clk_id, unsigned int freq, int dir)
0991 {
0992     struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
0993     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0994     struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id];
0995     int apll;
0996     int apll_rate;
0997
0998     if (dir != SND_SOC_CLOCK_OUT) {
0999         dev_err(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
1000         return -EINVAL;
1001     }
1002
1003     dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
1004
1005     apll = mt8186_get_apll_by_rate(afe, freq);
1006     apll_rate = mt8186_get_apll_rate(afe, apll);
1007
1008     if (freq > apll_rate) {
1009         dev_err(afe->dev, "%s(), freq > apll rate", __func__);
1010         return -EINVAL;
1011     }
1012
1013     if (apll_rate % freq != 0) {
1014         dev_err(afe->dev, "%s(), APLL cannot generate freq Hz", __func__);
1015         return -EINVAL;
1016     }
1017
1018     i2s_priv->mclk_rate = freq;
1019     i2s_priv->mclk_apll = apll;
1020
1021     if (i2s_priv->share_i2s_id > 0) {
1022         struct mtk_afe_i2s_priv *share_i2s_priv;
1023
1024         share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
1025         if (!share_i2s_priv) {
1026             dev_err(afe->dev, "%s(), share_i2s_priv == NULL", __func__);
1027             return -EINVAL;
1028         }
1029
1030         share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
1031         share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
1032     }
1033
1034     return 0;
1035 }
1036
1037 static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
1038     .hw_params = mtk_dai_i2s_hw_params,
1039     .set_sysclk = mtk_dai_i2s_set_sysclk,
1040 };
1041
1042 /* dai driver */
1043 #define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1044
1045 #define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\
1046                SNDRV_PCM_RATE_88200 |\
1047                SNDRV_PCM_RATE_96000 |\
1048                SNDRV_PCM_RATE_176400 |\
1049                SNDRV_PCM_RATE_192000)
1050
1051 #define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1052              SNDRV_PCM_FMTBIT_S24_LE |\
1053              SNDRV_PCM_FMTBIT_S32_LE)
1054
1055 static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
1056     {
1057         .name = "CONNSYS_I2S",
1058         .id = MT8186_DAI_CONNSYS_I2S,
1059         .capture = {
1060             .stream_name = "Connsys I2S",
1061             .channels_min = 1,
1062             .channels_max = 2,
1063             .rates = MTK_CONNSYS_I2S_RATES,
1064             .formats = MTK_I2S_FORMATS,
1065         },
1066         .ops = &mtk_dai_connsys_i2s_ops,
1067     },
1068     {
1069         .name = "I2S0",
1070         .id = MT8186_DAI_I2S_0,
1071         .capture = {
1072             .stream_name = "I2S0",
1073             .channels_min = 1,
1074             .channels_max = 2,
1075             .rates = MTK_I2S_RATES,
1076             .formats = MTK_I2S_FORMATS,
1077         },
1078         .ops = &mtk_dai_i2s_ops,
1079     },
1080     {
1081         .name = "I2S1",
1082         .id = MT8186_DAI_I2S_1,
1083         .playback = {
1084             .stream_name = "I2S1",
1085             .channels_min = 1,
1086             .channels_max = 2,
1087             .rates = MTK_I2S_RATES,
1088             .formats = MTK_I2S_FORMATS,
1089         },
1090         .ops = &mtk_dai_i2s_ops,
1091     },
1092     {
1093         .name = "I2S2",
1094         .id = MT8186_DAI_I2S_2,
1095         .capture = {
1096             .stream_name = "I2S2",
1097             .channels_min = 1,
1098             .channels_max = 2,
1099             .rates = MTK_I2S_RATES,
1100             .formats = MTK_I2S_FORMATS,
1101         },
1102         .ops = &mtk_dai_i2s_ops,
1103     },
1104     {
1105         .name = "I2S3",
1106         .id = MT8186_DAI_I2S_3,
1107         .playback = {
1108             .stream_name = "I2S3",
1109             .channels_min = 1,
1110             .channels_max = 2,
1111             .rates = MTK_I2S_RATES,
1112             .formats = MTK_I2S_FORMATS,
1113         },
1114         .ops = &mtk_dai_i2s_ops,
1115     }
1116 };
1117
1118 /* this enum is merely for mtk_afe_i2s_priv declare */
1119 enum {
1120     DAI_I2S0 = 0,
1121     DAI_I2S1,
1122     DAI_I2S2,
1123     DAI_I2S3,
1124     DAI_I2S_NUM,
1125 };
1126
1127 static const struct mtk_afe_i2s_priv mt8186_i2s_priv[DAI_I2S_NUM] = {
1128     [DAI_I2S0] = {
1129         .id = MT8186_DAI_I2S_0,
1130         .mclk_id = MT8186_I2S0_MCK,
1131         .share_property_name = "i2s0-share",
1132         .share_i2s_id = -1,
1133     },
1134     [DAI_I2S1] = {
1135         .id = MT8186_DAI_I2S_1,
1136         .mclk_id = MT8186_I2S1_MCK,
1137         .share_property_name = "i2s1-share",
1138         .share_i2s_id = -1,
1139     },
1140     [DAI_I2S2] = {
1141         .id = MT8186_DAI_I2S_2,
1142         .mclk_id = MT8186_I2S2_MCK,
1143         .share_property_name = "i2s2-share",
1144         .share_i2s_id = -1,
1145     },
1146     [DAI_I2S3] = {
1147         .id = MT8186_DAI_I2S_3,
1148         /*  clock gate naming is hf_faud_i2s4_m_ck*/
1149         .mclk_id = MT8186_I2S4_MCK,
1150         .share_property_name = "i2s3-share",
1151         .share_i2s_id = -1,
1152     }
1153 };
1154
1155 static int mt8186_dai_i2s_get_share(struct mtk_base_afe *afe)
1156 {
1157     struct mt8186_afe_private *afe_priv = afe->platform_priv;
1158     const struct device_node *of_node = afe->dev->of_node;
1159     const char *of_str;
1160     const char *property_name;
1161     struct mtk_afe_i2s_priv *i2s_priv;
1162     int i;
1163
1164     for (i = 0; i < DAI_I2S_NUM; i++) {
1165         i2s_priv = afe_priv->dai_priv[mt8186_i2s_priv[i].id];
1166         property_name = mt8186_i2s_priv[i].share_property_name;
1167         if (of_property_read_string(of_node, property_name, &of_str))
1168             continue;
1169         i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str);
1170     }
1171
1172     return 0;
1173 }
1174
1175 static int mt8186_dai_i2s_set_priv(struct mtk_base_afe *afe)
1176 {
1177     int i;
1178     int ret;
1179
1180     for (i = 0; i < DAI_I2S_NUM; i++) {
1181         ret = mt8186_dai_set_priv(afe, mt8186_i2s_priv[i].id,
1182                       sizeof(struct mtk_afe_i2s_priv),
1183                       &mt8186_i2s_priv[i]);
1184         if (ret)
1185             return ret;
1186     }
1187
1188     return 0;
1189 }
1190
1191 int mt8186_dai_i2s_register(struct mtk_base_afe *afe)
1192 {
1193     struct mtk_base_afe_dai *dai;
1194     int ret;
1195
1196     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1197     if (!dai)
1198         return -ENOMEM;
1199
1200     list_add(&dai->list, &afe->sub_dais);
1201
1202     dai->dai_drivers = mtk_dai_i2s_driver;
1203     dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
1204
1205     dai->controls = mtk_dai_i2s_controls;
1206     dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
1207     dai->dapm_widgets = mtk_dai_i2s_widgets;
1208     dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
1209     dai->dapm_routes = mtk_dai_i2s_routes;
1210     dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
1211
1212     /* set all dai i2s private data */
1213     ret = mt8186_dai_i2s_set_priv(afe);
1214     if (ret)
1215         return ret;
1216
1217     /* parse share i2s */
1218     ret = mt8186_dai_i2s_get_share(afe);
1219     if (ret)
1220         return ret;
1221
1222     return 0;
1223 }