mediatek/mt8186/mt8186-dai-adda.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // MediaTek ALSA SoC Audio DAI ADDA Control
0004 //
0005 // Copyright (c) 2022 MediaTek Inc.
0006 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007
0008 #include <linux/regmap.h>
0009 #include <linux/delay.h>
0010 #include "mt8186-afe-clk.h"
0011 #include "mt8186-afe-common.h"
0012 #include "mt8186-afe-gpio.h"
0013 #include "mt8186-interconnection.h"
0014
0015 enum {
0016     UL_IIR_SW = 0,
0017     UL_IIR_5HZ,
0018     UL_IIR_10HZ,
0019     UL_IIR_25HZ,
0020     UL_IIR_50HZ,
0021     UL_IIR_75HZ,
0022 };
0023
0024 enum {
0025     AUDIO_SDM_LEVEL_MUTE = 0,
0026     AUDIO_SDM_LEVEL_NORMAL = 0x1d,
0027     /* if you change level normal */
0028     /* you need to change formula of hp impedance and dc trim too */
0029 };
0030
0031 enum {
0032     AUDIO_SDM_2ND = 0,
0033     AUDIO_SDM_3RD,
0034 };
0035
0036 enum {
0037     DELAY_DATA_MISO1 = 0,
0038     DELAY_DATA_MISO2,
0039 };
0040
0041 enum {
0042     MTK_AFE_ADDA_DL_RATE_8K = 0,
0043     MTK_AFE_ADDA_DL_RATE_11K = 1,
0044     MTK_AFE_ADDA_DL_RATE_12K = 2,
0045     MTK_AFE_ADDA_DL_RATE_16K = 3,
0046     MTK_AFE_ADDA_DL_RATE_22K = 4,
0047     MTK_AFE_ADDA_DL_RATE_24K = 5,
0048     MTK_AFE_ADDA_DL_RATE_32K = 6,
0049     MTK_AFE_ADDA_DL_RATE_44K = 7,
0050     MTK_AFE_ADDA_DL_RATE_48K = 8,
0051     MTK_AFE_ADDA_DL_RATE_96K = 9,
0052     MTK_AFE_ADDA_DL_RATE_192K = 10,
0053 };
0054
0055 enum {
0056     MTK_AFE_ADDA_UL_RATE_8K = 0,
0057     MTK_AFE_ADDA_UL_RATE_16K = 1,
0058     MTK_AFE_ADDA_UL_RATE_32K = 2,
0059     MTK_AFE_ADDA_UL_RATE_48K = 3,
0060     MTK_AFE_ADDA_UL_RATE_96K = 4,
0061     MTK_AFE_ADDA_UL_RATE_192K = 5,
0062     MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
0063 };
0064
0065 #define SDM_AUTO_RESET_THRESHOLD 0x190000
0066
0067 struct mtk_afe_adda_priv {
0068     int dl_rate;
0069     int ul_rate;
0070 };
0071
0072 static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
0073                                const char *name)
0074 {
0075     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0076     int dai_id;
0077
0078     if (strncmp(name, "aud_dac", 7) == 0 || strncmp(name, "aud_adc", 7) == 0)
0079         dai_id = MT8186_DAI_ADDA;
0080     else
0081         return NULL;
0082
0083     return afe_priv->dai_priv[dai_id];
0084 }
0085
0086 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
0087                        unsigned int rate)
0088 {
0089     switch (rate) {
0090     case 8000:
0091         return MTK_AFE_ADDA_DL_RATE_8K;
0092     case 11025:
0093         return MTK_AFE_ADDA_DL_RATE_11K;
0094     case 12000:
0095         return MTK_AFE_ADDA_DL_RATE_12K;
0096     case 16000:
0097         return MTK_AFE_ADDA_DL_RATE_16K;
0098     case 22050:
0099         return MTK_AFE_ADDA_DL_RATE_22K;
0100     case 24000:
0101         return MTK_AFE_ADDA_DL_RATE_24K;
0102     case 32000:
0103         return MTK_AFE_ADDA_DL_RATE_32K;
0104     case 44100:
0105         return MTK_AFE_ADDA_DL_RATE_44K;
0106     case 48000:
0107         return MTK_AFE_ADDA_DL_RATE_48K;
0108     case 96000:
0109         return MTK_AFE_ADDA_DL_RATE_96K;
0110     case 192000:
0111         return MTK_AFE_ADDA_DL_RATE_192K;
0112     default:
0113         dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0114              __func__, rate);
0115     }
0116
0117     return MTK_AFE_ADDA_DL_RATE_48K;
0118 }
0119
0120 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
0121                        unsigned int rate)
0122 {
0123     switch (rate) {
0124     case 8000:
0125         return MTK_AFE_ADDA_UL_RATE_8K;
0126     case 16000:
0127         return MTK_AFE_ADDA_UL_RATE_16K;
0128     case 32000:
0129         return MTK_AFE_ADDA_UL_RATE_32K;
0130     case 48000:
0131         return MTK_AFE_ADDA_UL_RATE_48K;
0132     case 96000:
0133         return MTK_AFE_ADDA_UL_RATE_96K;
0134     case 192000:
0135         return MTK_AFE_ADDA_UL_RATE_192K;
0136     default:
0137         dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0138              __func__, rate);
0139     }
0140
0141     return MTK_AFE_ADDA_UL_RATE_48K;
0142 }
0143
0144 /* dai component */
0145 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
0146     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0),
0147     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0),
0148     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0),
0149     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0),
0150     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0),
0151     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0),
0152     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0),
0153     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0),
0154     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3,
0155                     I_ADDA_UL_CH2, 1, 0),
0156     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3,
0157                     I_ADDA_UL_CH1, 1, 0),
0158     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3,
0159                     I_GAIN1_OUT_CH1, 1, 0),
0160     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3,
0161                     I_PCM_1_CAP_CH1, 1, 0),
0162     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3,
0163                     I_PCM_2_CAP_CH1, 1, 0),
0164     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1,
0165                     I_SRC_1_OUT_CH1, 1, 0),
0166     SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1,
0167                     I_SRC_2_OUT_CH1, 1, 0),
0168 };
0169
0170 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
0171     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0),
0172     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0),
0173     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0),
0174     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0),
0175     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0),
0176     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0),
0177     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0),
0178     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0),
0179     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0),
0180     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0),
0181     SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0),
0182     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4,
0183                     I_ADDA_UL_CH2, 1, 0),
0184     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4,
0185                     I_ADDA_UL_CH1, 1, 0),
0186     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4,
0187                     I_GAIN1_OUT_CH2, 1, 0),
0188     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4,
0189                     I_PCM_1_CAP_CH2, 1, 0),
0190     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4,
0191                     I_PCM_2_CAP_CH2, 1, 0),
0192     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1,
0193                     I_SRC_1_OUT_CH2, 1, 0),
0194     SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1,
0195                     I_SRC_2_OUT_CH2, 1, 0),
0196 };
0197
0198 enum {
0199     SUPPLY_SEQ_ADDA_AFE_ON,
0200     SUPPLY_SEQ_ADDA_DL_ON,
0201     SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
0202     SUPPLY_SEQ_ADDA_MTKAIF_CFG,
0203     SUPPLY_SEQ_ADDA_FIFO,
0204     SUPPLY_SEQ_ADDA_AP_DMIC,
0205     SUPPLY_SEQ_ADDA_UL_ON,
0206 };
0207
0208 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
0209 {
0210     unsigned int reg;
0211
0212     switch (id) {
0213     case MT8186_DAI_ADDA:
0214     case MT8186_DAI_AP_DMIC:
0215         reg = AFE_ADDA_UL_SRC_CON0;
0216         break;
0217     default:
0218         return -EINVAL;
0219     }
0220
0221     /* dmic mode, 3.25M*/
0222     regmap_update_bits(afe->regmap, reg,
0223                DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0);
0224     regmap_update_bits(afe->regmap, reg,
0225                DMIC_LOW_POWER_CTL_MASK_SFT, 0);
0226
0227     /* turn on dmic, ch1, ch2 */
0228     regmap_update_bits(afe->regmap, reg,
0229                UL_SDM_3_LEVEL_MASK_SFT,
0230                BIT(UL_SDM_3_LEVEL_SFT));
0231     regmap_update_bits(afe->regmap, reg,
0232                UL_MODE_3P25M_CH1_CTL_MASK_SFT,
0233                BIT(UL_MODE_3P25M_CH1_CTL_SFT));
0234     regmap_update_bits(afe->regmap, reg,
0235                UL_MODE_3P25M_CH2_CTL_MASK_SFT,
0236                BIT(UL_MODE_3P25M_CH2_CTL_SFT));
0237
0238     return 0;
0239 }
0240
0241 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
0242                  struct snd_kcontrol *kcontrol,
0243                  int event)
0244 {
0245     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0246     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0247     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0248     int mtkaif_dmic = afe_priv->mtkaif_dmic;
0249
0250     dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
0251         __func__, w->name, event, mtkaif_dmic);
0252
0253     switch (event) {
0254     case SND_SOC_DAPM_PRE_PMU:
0255         mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1);
0256
0257         /* update setting to dmic */
0258         if (mtkaif_dmic) {
0259             /* mtkaif_rxif_data_mode = 1, dmic */
0260             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0261                        0x1, 0x1);
0262
0263             /* dmic mode, 3.25M*/
0264             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0265                        MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
0266                        0x0);
0267             mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA);
0268         }
0269         break;
0270     case SND_SOC_DAPM_POST_PMD:
0271         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0272         usleep_range(125, 135);
0273         mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1);
0274         break;
0275     default:
0276         break;
0277     }
0278
0279     return 0;
0280 }
0281
0282 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
0283                   struct snd_kcontrol *kcontrol,
0284                   int event)
0285 {
0286     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0287     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0288     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0289
0290     switch (event) {
0291     case SND_SOC_DAPM_PRE_PMU:
0292         if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
0293             regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
0294         else
0295             regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
0296         break;
0297     default:
0298         break;
0299     }
0300
0301     return 0;
0302 }
0303
0304 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
0305                      struct snd_kcontrol *kcontrol,
0306                      int event)
0307 {
0308     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0309     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0310     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0311     int delay_data;
0312     int delay_cycle;
0313
0314     switch (event) {
0315     case SND_SOC_DAPM_PRE_PMU:
0316         if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
0317             /* set protocol 2 */
0318             regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);
0319             /* mtkaif_rxif_clkinv_adc inverse */
0320             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0321                        MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
0322                        BIT(MTKAIF_RXIF_CLKINV_ADC_SFT));
0323
0324             if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0) {
0325                 if (afe_priv->mtkaif_chosen_phase[0] < 0 &&
0326                     afe_priv->mtkaif_chosen_phase[1] < 0) {
0327                     dev_err(afe->dev,
0328                         "%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n",
0329                         __func__,
0330                         afe_priv->mtkaif_chosen_phase[0],
0331                         afe_priv->mtkaif_chosen_phase[1]);
0332                     break;
0333                 }
0334
0335                 if (afe_priv->mtkaif_chosen_phase[0] < 0 ||
0336                     afe_priv->mtkaif_chosen_phase[1] < 0) {
0337                     dev_err(afe->dev,
0338                         "%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n",
0339                         __func__,
0340                         afe_priv->mtkaif_chosen_phase[0],
0341                         afe_priv->mtkaif_chosen_phase[1]);
0342                     break;
0343                 }
0344             }
0345
0346             /* set delay for ch12 */
0347             if (afe_priv->mtkaif_phase_cycle[0] >=
0348                 afe_priv->mtkaif_phase_cycle[1]) {
0349                 delay_data = DELAY_DATA_MISO1;
0350                 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
0351                           afe_priv->mtkaif_phase_cycle[1];
0352             } else {
0353                 delay_data = DELAY_DATA_MISO2;
0354                 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
0355                           afe_priv->mtkaif_phase_cycle[0];
0356             }
0357
0358             regmap_update_bits(afe->regmap,
0359                        AFE_ADDA_MTKAIF_RX_CFG2,
0360                        MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
0361                        delay_data <<
0362                        MTKAIF_RXIF_DELAY_DATA_SFT);
0363
0364             regmap_update_bits(afe->regmap,
0365                        AFE_ADDA_MTKAIF_RX_CFG2,
0366                        MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
0367                        delay_cycle <<
0368                        MTKAIF_RXIF_DELAY_CYCLE_SFT);
0369
0370         } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
0371             regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);
0372         } else {
0373             regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0);
0374         }
0375
0376         break;
0377     default:
0378         break;
0379     }
0380
0381     return 0;
0382 }
0383
0384 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
0385                  struct snd_kcontrol *kcontrol,
0386                  int event)
0387 {
0388     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0389     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0390
0391     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0392         __func__, w->name, event);
0393
0394     switch (event) {
0395     case SND_SOC_DAPM_PRE_PMU:
0396         mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0);
0397         break;
0398     case SND_SOC_DAPM_POST_PMD:
0399         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0400         usleep_range(125, 135);
0401         mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0);
0402         break;
0403     default:
0404         break;
0405     }
0406
0407     return 0;
0408 }
0409
0410 static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol,
0411                 struct snd_ctl_elem_value *ucontrol)
0412 {
0413     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0414     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0415     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0416
0417     ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
0418
0419     return 0;
0420 }
0421
0422 static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol,
0423                 struct snd_ctl_elem_value *ucontrol)
0424 {
0425     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0426     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0427     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0428     int dmic_on;
0429
0430     dmic_on = ucontrol->value.integer.value[0];
0431
0432     dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
0433         __func__, kcontrol->id.name, dmic_on);
0434
0435     if (afe_priv->mtkaif_dmic == dmic_on)
0436         return 0;
0437
0438     afe_priv->mtkaif_dmic = dmic_on;
0439
0440     return 1;
0441 }
0442
0443 static const struct snd_kcontrol_new mtk_adda_controls[] = {
0444     SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
0445            DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
0446     SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
0447                 mt8186_adda_dmic_get, mt8186_adda_dmic_set),
0448 };
0449
0450 /* ADDA UL MUX */
0451 enum {
0452     ADDA_UL_MUX_MTKAIF = 0,
0453     ADDA_UL_MUX_AP_DMIC,
0454     ADDA_UL_MUX_MASK = 0x1,
0455 };
0456
0457 static const char * const adda_ul_mux_map[] = {
0458     "MTKAIF", "AP_DMIC"
0459 };
0460
0461 static int adda_ul_map_value[] = {
0462     ADDA_UL_MUX_MTKAIF,
0463     ADDA_UL_MUX_AP_DMIC,
0464 };
0465
0466 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
0467                   SND_SOC_NOPM,
0468                   0,
0469                   ADDA_UL_MUX_MASK,
0470                   adda_ul_mux_map,
0471                   adda_ul_map_value);
0472
0473 static const struct snd_kcontrol_new adda_ul_mux_control =
0474     SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
0475
0476 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
0477     /* inter-connections */
0478     SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
0479                mtk_adda_dl_ch1_mix,
0480                ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
0481     SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
0482                mtk_adda_dl_ch2_mix,
0483                ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
0484
0485     SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
0486                   AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
0487                   NULL, 0),
0488
0489     SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
0490                   AFE_ADDA_DL_SRC2_CON0,
0491                   DL_2_SRC_ON_CTL_PRE_SFT, 0,
0492                   mtk_adda_dl_event,
0493                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0494
0495     SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
0496                   AFE_ADDA_UL_SRC_CON0,
0497                   UL_SRC_ON_CTL_SFT, 0,
0498                   mtk_adda_ul_event,
0499                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0500
0501     SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
0502                   0, 0, 0,
0503                   mtk_adda_pad_top_event,
0504                   SND_SOC_DAPM_PRE_PMU),
0505     SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
0506                   SND_SOC_NOPM, 0, 0,
0507                   mtk_adda_mtkaif_cfg_event,
0508                   SND_SOC_DAPM_PRE_PMU),
0509
0510     SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
0511                   AFE_ADDA_UL_SRC_CON0,
0512                   UL_AP_DMIC_ON_SFT, 0,
0513                   NULL, 0),
0514
0515     SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
0516                   AFE_ADDA_UL_DL_CON0,
0517                   AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
0518                   NULL, 0),
0519
0520     SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
0521              &adda_ul_mux_control),
0522
0523     SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
0524
0525     /* clock */
0526     SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
0527
0528     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
0529     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"),
0530     SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
0531
0532     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
0533     SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"),
0534 };
0535
0536 #define HIRES_THRESHOLD 48000
0537 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source,
0538                      struct snd_soc_dapm_widget *sink)
0539 {
0540     struct snd_soc_dapm_widget *w = source;
0541     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0542     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0543     struct mtk_afe_adda_priv *adda_priv;
0544
0545     adda_priv = get_adda_priv_by_name(afe, w->name);
0546
0547     if (!adda_priv) {
0548         dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);
0549         return 0;
0550     }
0551
0552     return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0;
0553 }
0554
0555 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source,
0556                      struct snd_soc_dapm_widget *sink)
0557 {
0558     struct snd_soc_dapm_widget *w = source;
0559     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0560     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0561     struct mtk_afe_adda_priv *adda_priv;
0562
0563     adda_priv = get_adda_priv_by_name(afe, w->name);
0564
0565     if (!adda_priv) {
0566         dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);
0567         return 0;
0568     }
0569
0570     return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0;
0571 }
0572
0573 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
0574     /* playback */
0575     {"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"},
0576     {"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"},
0577     {"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"},
0578
0579     {"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"},
0580     {"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"},
0581
0582     {"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"},
0583     {"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"},
0584
0585     {"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"},
0586     {"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"},
0587
0588     {"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"},
0589     {"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"},
0590     {"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"},
0591
0592     {"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"},
0593     {"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"},
0594     {"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"},
0595
0596     {"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"},
0597     {"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"},
0598
0599     {"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"},
0600     {"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"},
0601
0602     {"ADDA Playback", NULL, "ADDA_DL_CH1"},
0603     {"ADDA Playback", NULL, "ADDA_DL_CH2"},
0604
0605     {"ADDA Playback", NULL, "ADDA Enable"},
0606     {"ADDA Playback", NULL, "ADDA Playback Enable"},
0607
0608     /* capture */
0609     {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
0610     {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
0611
0612     {"ADDA Capture", NULL, "ADDA Enable"},
0613     {"ADDA Capture", NULL, "ADDA Capture Enable"},
0614     {"ADDA Capture", NULL, "AUD_PAD_TOP"},
0615     {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
0616
0617     {"AP DMIC Capture", NULL, "ADDA Enable"},
0618     {"AP DMIC Capture", NULL, "ADDA Capture Enable"},
0619     {"AP DMIC Capture", NULL, "ADDA_FIFO"},
0620     {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
0621
0622     {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
0623
0624     /* clk */
0625     {"ADDA Playback", NULL, "aud_dac_clk"},
0626     {"ADDA Playback", NULL, "aud_dac_predis_clk"},
0627     {"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect},
0628
0629     {"ADDA Capture Enable", NULL, "aud_adc_clk"},
0630     {"ADDA Capture Enable", NULL, "aud_adc_hires_clk",
0631      mtk_afe_adc_hires_connect},
0632
0633     /* hires source from apll1 */
0634     {"top_mux_audio_h", NULL, APLL2_W_NAME},
0635
0636     {"aud_dac_hires_clk", NULL, "top_mux_audio_h"},
0637     {"aud_adc_hires_clk", NULL, "top_mux_audio_h"},
0638 };
0639
0640 /* dai ops */
0641 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
0642                   struct snd_pcm_hw_params *params,
0643                   struct snd_soc_dai *dai)
0644 {
0645     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0646     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0647     unsigned int rate = params_rate(params);
0648     int id = dai->id;
0649     struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id];
0650
0651     dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
0652         __func__, id, substream->stream, rate);
0653
0654     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0655         unsigned int dl_src2_con0;
0656         unsigned int dl_src2_con1;
0657
0658         adda_priv->dl_rate = rate;
0659
0660         /* set sampling rate */
0661         dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
0662                    DL_2_INPUT_MODE_CTL_SFT;
0663
0664         /* set output mode, UP_SAMPLING_RATE_X8 */
0665         dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
0666
0667         /* turn off mute function */
0668         dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
0669         dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
0670
0671         /* set voice input data if input sample rate is 8k or 16k */
0672         if (rate == 8000 || rate == 16000)
0673             dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT);
0674
0675         /* SA suggest apply -0.3db to audio/speech path */
0676         dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
0677                    DL_2_GAIN_CTL_PRE_SFT;
0678
0679         /* turn on down-link gain */
0680         dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT);
0681
0682         if (id == MT8186_DAI_ADDA) {
0683             /* clean predistortion */
0684             regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
0685             regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
0686
0687             regmap_write(afe->regmap,
0688                      AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
0689             regmap_write(afe->regmap,
0690                      AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
0691
0692             /* set sdm gain */
0693             regmap_update_bits(afe->regmap,
0694                        AFE_ADDA_DL_SDM_DCCOMP_CON,
0695                        ATTGAIN_CTL_MASK_SFT,
0696                        AUDIO_SDM_LEVEL_NORMAL <<
0697                        ATTGAIN_CTL_SFT);
0698
0699             /* Use new 2nd sdm */
0700             regmap_update_bits(afe->regmap,
0701                        AFE_ADDA_DL_SDM_DITHER_CON,
0702                        AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT,
0703                        BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT));
0704             regmap_update_bits(afe->regmap,
0705                        AFE_ADDA_DL_SDM_AUTO_RESET_CON,
0706                        AFE_DL_USE_NEW_2ND_SDM_MASK_SFT,
0707                        BIT(AFE_DL_USE_NEW_2ND_SDM_SFT));
0708             regmap_update_bits(afe->regmap,
0709                        AFE_ADDA_DL_SDM_DCCOMP_CON,
0710                        USE_3RD_SDM_MASK_SFT,
0711                        AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
0712
0713             /* sdm auto reset */
0714             regmap_write(afe->regmap,
0715                      AFE_ADDA_DL_SDM_AUTO_RESET_CON,
0716                      SDM_AUTO_RESET_THRESHOLD);
0717             regmap_update_bits(afe->regmap,
0718                        AFE_ADDA_DL_SDM_AUTO_RESET_CON,
0719                        SDM_AUTO_RESET_TEST_ON_MASK_SFT,
0720                        BIT(SDM_AUTO_RESET_TEST_ON_SFT));
0721         }
0722     } else {
0723         unsigned int ul_src_con0 = 0;
0724         unsigned int voice_mode = adda_ul_rate_transform(afe, rate);
0725
0726         adda_priv->ul_rate = rate;
0727         ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
0728
0729         /* enable iir */
0730         ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
0731                    UL_IIR_ON_TMP_CTL_MASK_SFT;
0732         ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
0733                    UL_IIRMODE_CTL_MASK_SFT;
0734         switch (id) {
0735         case MT8186_DAI_ADDA:
0736         case MT8186_DAI_AP_DMIC:
0737             /* 35Hz @ 48k */
0738             regmap_write(afe->regmap,
0739                      AFE_ADDA_IIR_COEF_02_01, 0);
0740             regmap_write(afe->regmap,
0741                      AFE_ADDA_IIR_COEF_04_03, 0x3fb8);
0742             regmap_write(afe->regmap,
0743                      AFE_ADDA_IIR_COEF_06_05, 0x3fb80000);
0744             regmap_write(afe->regmap,
0745                      AFE_ADDA_IIR_COEF_08_07, 0x3fb80000);
0746             regmap_write(afe->regmap,
0747                      AFE_ADDA_IIR_COEF_10_09, 0xc048);
0748
0749             regmap_write(afe->regmap,
0750                      AFE_ADDA_UL_SRC_CON0, ul_src_con0);
0751
0752             /* Using Internal ADC */
0753             regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0);
0754
0755             /* mtkaif_rxif_data_mode = 0, amic */
0756             regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0);
0757             break;
0758         default:
0759             break;
0760         }
0761
0762         /* ap dmic */
0763         switch (id) {
0764         case MT8186_DAI_AP_DMIC:
0765             mtk_adda_ul_src_dmic(afe, id);
0766             break;
0767         default:
0768             break;
0769         }
0770     }
0771
0772     return 0;
0773 }
0774
0775 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
0776     .hw_params = mtk_dai_adda_hw_params,
0777 };
0778
0779 /* dai driver */
0780 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
0781                  SNDRV_PCM_RATE_96000 |\
0782                  SNDRV_PCM_RATE_192000)
0783
0784 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
0785                 SNDRV_PCM_RATE_16000 |\
0786                 SNDRV_PCM_RATE_32000 |\
0787                 SNDRV_PCM_RATE_48000 |\
0788                 SNDRV_PCM_RATE_96000 |\
0789                 SNDRV_PCM_RATE_192000)
0790
0791 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0792               SNDRV_PCM_FMTBIT_S24_LE |\
0793               SNDRV_PCM_FMTBIT_S32_LE)
0794
0795 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
0796     {
0797         .name = "ADDA",
0798         .id = MT8186_DAI_ADDA,
0799         .playback = {
0800             .stream_name = "ADDA Playback",
0801             .channels_min = 1,
0802             .channels_max = 2,
0803             .rates = MTK_ADDA_PLAYBACK_RATES,
0804             .formats = MTK_ADDA_FORMATS,
0805         },
0806         .capture = {
0807             .stream_name = "ADDA Capture",
0808             .channels_min = 1,
0809             .channels_max = 2,
0810             .rates = MTK_ADDA_CAPTURE_RATES,
0811             .formats = MTK_ADDA_FORMATS,
0812         },
0813         .ops = &mtk_dai_adda_ops,
0814     },
0815     {
0816         .name = "AP_DMIC",
0817         .id = MT8186_DAI_AP_DMIC,
0818         .capture = {
0819             .stream_name = "AP DMIC Capture",
0820             .channels_min = 1,
0821             .channels_max = 2,
0822             .rates = MTK_ADDA_CAPTURE_RATES,
0823             .formats = MTK_ADDA_FORMATS,
0824         },
0825         .ops = &mtk_dai_adda_ops,
0826     },
0827 };
0828
0829 int mt8186_dai_adda_register(struct mtk_base_afe *afe)
0830 {
0831     struct mtk_base_afe_dai *dai;
0832     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0833     int ret;
0834
0835     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
0836     if (!dai)
0837         return -ENOMEM;
0838
0839     list_add(&dai->list, &afe->sub_dais);
0840
0841     dai->dai_drivers = mtk_dai_adda_driver;
0842     dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
0843
0844     dai->controls = mtk_adda_controls;
0845     dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
0846     dai->dapm_widgets = mtk_dai_adda_widgets;
0847     dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
0848     dai->dapm_routes = mtk_dai_adda_routes;
0849     dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
0850
0851     /* set dai priv */
0852     ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA,
0853                   sizeof(struct mtk_afe_adda_priv), NULL);
0854     if (ret)
0855         return ret;
0856
0857     /* ap dmic priv share with adda */
0858     afe_priv->dai_priv[MT8186_DAI_AP_DMIC] =
0859         afe_priv->dai_priv[MT8186_DAI_ADDA];
0860
0861     return 0;
0862 }