mediatek/mt8186/mt8186-audsys-clk.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt8186-audsys-clk.h  --  Mediatek 8186 audsys clock control
0004 //
0005 // Copyright (c) 2022 MediaTek Inc.
0006 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007
0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/clkdev.h>
0011 #include "mt8186-afe-common.h"
0012 #include "mt8186-audsys-clk.h"
0013 #include "mt8186-audsys-clkid.h"
0014 #include "mt8186-reg.h"
0015
0016 struct afe_gate {
0017     int id;
0018     const char *name;
0019     const char *parent_name;
0020     int reg;
0021     u8 bit;
0022     const struct clk_ops *ops;
0023     unsigned long flags;
0024     u8 cg_flags;
0025 };
0026
0027 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
0028         .id = _id,                  \
0029         .name = _name,                  \
0030         .parent_name = _parent,             \
0031         .reg = _reg,                    \
0032         .bit = _bit,                    \
0033         .flags = _flags,                \
0034         .cg_flags = _cgflags,               \
0035     }
0036
0037 #define GATE_AFE(_id, _name, _parent, _reg, _bit)       \
0038     GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit,     \
0039                CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
0040
0041 #define GATE_AUD0(_id, _name, _parent, _bit)            \
0042     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
0043
0044 #define GATE_AUD1(_id, _name, _parent, _bit)            \
0045     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
0046
0047 #define GATE_AUD2(_id, _name, _parent, _bit)            \
0048     GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
0049
0050 static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
0051     /* AUD0 */
0052     GATE_AUD0(CLK_AUD_AFE, "aud_afe_clk", "top_audio", 2),
0053     GATE_AUD0(CLK_AUD_22M, "aud_apll22m_clk", "top_aud_engen1", 8),
0054     GATE_AUD0(CLK_AUD_24M, "aud_apll24m_clk", "top_aud_engen2", 9),
0055     GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner_clk", "top_aud_engen2", 18),
0056     GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner_clk", "top_aud_engen1", 19),
0057     GATE_AUD0(CLK_AUD_TDM, "aud_tdm_clk", "top_aud_1", 20),
0058     GATE_AUD0(CLK_AUD_ADC, "aud_adc_clk", "top_audio", 24),
0059     GATE_AUD0(CLK_AUD_DAC, "aud_dac_clk", "top_audio", 25),
0060     GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis_clk", "top_audio", 26),
0061     GATE_AUD0(CLK_AUD_TML, "aud_tml_clk", "top_audio", 27),
0062     GATE_AUD0(CLK_AUD_NLE, "aud_nle_clk", "top_audio", 28),
0063
0064     /* AUD1 */
0065     GATE_AUD1(CLK_AUD_I2S1_BCLK, "aud_i2s1_bclk", "top_audio", 4),
0066     GATE_AUD1(CLK_AUD_I2S2_BCLK, "aud_i2s2_bclk", "top_audio", 5),
0067     GATE_AUD1(CLK_AUD_I2S3_BCLK, "aud_i2s3_bclk", "top_audio", 6),
0068     GATE_AUD1(CLK_AUD_I2S4_BCLK, "aud_i2s4_bclk", "top_audio", 7),
0069     GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "top_audio", 12),
0070     GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "top_audio", 13),
0071     GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "top_audio", 14),
0072     GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires_clk", "top_audio_h", 15),
0073     GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires_clk", "top_audio_h", 16),
0074     GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "top_audio_h", 17),
0075     GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_audio", 20),
0076     GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 21),
0077     GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "top_audio", 28),
0078     GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "top_audio", 29),
0079     GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "top_audio", 30),
0080     GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "top_audio_h", 31),
0081
0082     /* AUD2 */
0083     GATE_AUD2(CLK_AUD_ETDM_IN1_BCLK, "aud_etdm_in1_bclk", "top_audio", 23),
0084     GATE_AUD2(CLK_AUD_ETDM_OUT1_BCLK, "aud_etdm_out1_bclk", "top_audio", 24),
0085 };
0086
0087 int mt8186_audsys_clk_register(struct mtk_base_afe *afe)
0088 {
0089     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0090     struct clk *clk;
0091     struct clk_lookup *cl;
0092     int i;
0093
0094     afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
0095                     sizeof(*afe_priv->lookup),
0096                     GFP_KERNEL);
0097
0098     if (!afe_priv->lookup)
0099         return -ENOMEM;
0100
0101     for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
0102         const struct afe_gate *gate = &aud_clks[i];
0103
0104         clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
0105                     gate->flags, afe->base_addr + gate->reg,
0106                     gate->bit, gate->cg_flags, NULL);
0107
0108         if (IS_ERR(clk)) {
0109             dev_err(afe->dev, "Failed to register clk %s: %ld\n",
0110                 gate->name, PTR_ERR(clk));
0111             continue;
0112         }
0113
0114         /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
0115         cl = kzalloc(sizeof(*cl), GFP_KERNEL);
0116         if (!cl)
0117             return -ENOMEM;
0118
0119         cl->clk = clk;
0120         cl->con_id = gate->name;
0121         cl->dev_id = dev_name(afe->dev);
0122         clkdev_add(cl);
0123
0124         afe_priv->lookup[i] = cl;
0125     }
0126
0127     return 0;
0128 }
0129
0130 void mt8186_audsys_clk_unregister(struct mtk_base_afe *afe)
0131 {
0132     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0133     struct clk *clk;
0134     struct clk_lookup *cl;
0135     int i;
0136
0137     if (!afe_priv)
0138         return;
0139
0140     for (i = 0; i < CLK_AUD_NR_CLK; i++) {
0141         cl = afe_priv->lookup[i];
0142         if (!cl)
0143             continue;
0144
0145         clk = cl->clk;
0146         clk_unregister_gate(clk);
0147
0148         clkdev_drop(cl);
0149     }
0150 }