mediatek/mt8186/mt8186-afe-pcm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Mediatek ALSA SoC AFE platform driver for 8186
0004 //
0005 // Copyright (c) 2022 MediaTek Inc.
0006 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007
0008 #include <linux/delay.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/reset.h>
0015 #include <sound/soc.h>
0016
0017 #include "../common/mtk-afe-platform-driver.h"
0018 #include "../common/mtk-afe-fe-dai.h"
0019
0020 #include "mt8186-afe-common.h"
0021 #include "mt8186-afe-clk.h"
0022 #include "mt8186-afe-gpio.h"
0023 #include "mt8186-interconnection.h"
0024
0025 static const struct snd_pcm_hardware mt8186_afe_hardware = {
0026     .info = (SNDRV_PCM_INFO_MMAP |
0027          SNDRV_PCM_INFO_INTERLEAVED |
0028          SNDRV_PCM_INFO_MMAP_VALID),
0029     .formats = (SNDRV_PCM_FMTBIT_S16_LE |
0030             SNDRV_PCM_FMTBIT_S24_LE |
0031             SNDRV_PCM_FMTBIT_S32_LE),
0032     .period_bytes_min = 96,
0033     .period_bytes_max = 4 * 48 * 1024,
0034     .periods_min = 2,
0035     .periods_max = 256,
0036     .buffer_bytes_max = 4 * 48 * 1024,
0037     .fifo_size = 0,
0038 };
0039
0040 static int mt8186_fe_startup(struct snd_pcm_substream *substream,
0041                  struct snd_soc_dai *dai)
0042 {
0043     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0044     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0045     struct snd_pcm_runtime *runtime = substream->runtime;
0046     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0047     struct mtk_base_afe_memif *memif = &afe->memif[id];
0048     const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
0049     int ret;
0050
0051     memif->substream = substream;
0052
0053     snd_pcm_hw_constraint_step(substream->runtime, 0,
0054                    SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
0055
0056     snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
0057
0058     ret = snd_pcm_hw_constraint_integer(runtime,
0059                         SNDRV_PCM_HW_PARAM_PERIODS);
0060     if (ret < 0) {
0061         dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
0062         return ret;
0063     }
0064
0065     /* dynamic allocate irq to memif */
0066     if (memif->irq_usage < 0) {
0067         int irq_id = mtk_dynamic_irq_acquire(afe);
0068
0069         if (irq_id != afe->irqs_size) {
0070             /* link */
0071             memif->irq_usage = irq_id;
0072         } else {
0073             dev_err(afe->dev, "%s() error: no more asys irq\n",
0074                 __func__);
0075             return -EBUSY;
0076         }
0077     }
0078
0079     return 0;
0080 }
0081
0082 static void mt8186_fe_shutdown(struct snd_pcm_substream *substream,
0083                    struct snd_soc_dai *dai)
0084 {
0085     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0086     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0087     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0088     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0089     struct mtk_base_afe_memif *memif = &afe->memif[id];
0090     int irq_id = memif->irq_usage;
0091
0092     memif->substream = NULL;
0093     afe_priv->irq_cnt[id] = 0;
0094     afe_priv->xrun_assert[id] = 0;
0095
0096     if (!memif->const_irq) {
0097         mtk_dynamic_irq_release(afe, irq_id);
0098         memif->irq_usage = -1;
0099         memif->substream = NULL;
0100     }
0101 }
0102
0103 static int mt8186_fe_hw_params(struct snd_pcm_substream *substream,
0104                    struct snd_pcm_hw_params *params,
0105                    struct snd_soc_dai *dai)
0106 {
0107     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0108     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0109     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0110     unsigned int channels = params_channels(params);
0111     unsigned int rate = params_rate(params);
0112     int ret;
0113
0114     ret = mtk_afe_fe_hw_params(substream, params, dai);
0115     if (ret)
0116         return ret;
0117
0118     /* channel merge configuration, enable control is in UL5_IN_MUX */
0119     if (id == MT8186_MEMIF_VUL3) {
0120         int update_cnt = 8;
0121         unsigned int val = 0;
0122         unsigned int mask = 0;
0123         int fs_mode = mt8186_rate_transform(afe->dev, rate, id);
0124
0125         /* set rate, channel, update cnt, disable sgen */
0126         val = fs_mode << CM1_FS_SELECT_SFT |
0127             (channels - 1) << CHANNEL_MERGE0_CHNUM_SFT |
0128             update_cnt << CHANNEL_MERGE0_UPDATE_CNT_SFT;
0129         mask = CM1_FS_SELECT_MASK_SFT |
0130             CHANNEL_MERGE0_CHNUM_MASK_SFT |
0131             CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT;
0132         regmap_update_bits(afe->regmap, AFE_CM1_CON, mask, val);
0133     }
0134
0135     return 0;
0136 }
0137
0138 static int mt8186_fe_hw_free(struct snd_pcm_substream *substream,
0139                  struct snd_soc_dai *dai)
0140 {
0141     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0142     int ret;
0143
0144     ret = mtk_afe_fe_hw_free(substream, dai);
0145     if (ret) {
0146         dev_err(afe->dev, "%s failed\n", __func__);
0147         return ret;
0148     }
0149
0150     return 0;
0151 }
0152
0153 static int mt8186_fe_trigger(struct snd_pcm_substream *substream, int cmd,
0154                  struct snd_soc_dai *dai)
0155 {
0156     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0157     struct snd_pcm_runtime * const runtime = substream->runtime;
0158     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0159     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0160     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0161     struct mtk_base_afe_memif *memif = &afe->memif[id];
0162     int irq_id = memif->irq_usage;
0163     struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
0164     const struct mtk_base_irq_data *irq_data = irqs->irq_data;
0165     unsigned int rate = runtime->rate;
0166     unsigned int counter;
0167     int fs;
0168     int ret;
0169
0170     dev_dbg(afe->dev, "%s(), %s cmd %d, irq_id %d\n",
0171         __func__, memif->data->name, cmd, irq_id);
0172
0173     switch (cmd) {
0174     case SNDRV_PCM_TRIGGER_START:
0175     case SNDRV_PCM_TRIGGER_RESUME:
0176         ret = mtk_memif_set_enable(afe, id);
0177         if (ret) {
0178             dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
0179                 __func__, id, ret);
0180             return ret;
0181         }
0182
0183         /*
0184          * for small latency record
0185          * ul memif need read some data before irq enable
0186          */
0187         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
0188             ((runtime->period_size * 1000) / rate <= 10))
0189             udelay(300);
0190
0191         /* set irq counter */
0192         if (afe_priv->irq_cnt[id] > 0)
0193             counter = afe_priv->irq_cnt[id];
0194         else
0195             counter = runtime->period_size;
0196
0197         regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
0198                    irq_data->irq_cnt_maskbit
0199                    << irq_data->irq_cnt_shift,
0200                    counter << irq_data->irq_cnt_shift);
0201
0202         /* set irq fs */
0203         fs = afe->irq_fs(substream, runtime->rate);
0204         if (fs < 0)
0205             return -EINVAL;
0206
0207         regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
0208                    irq_data->irq_fs_maskbit
0209                    << irq_data->irq_fs_shift,
0210                    fs << irq_data->irq_fs_shift);
0211
0212         /* enable interrupt */
0213         if (runtime->stop_threshold != ~(0U))
0214             regmap_update_bits(afe->regmap,
0215                        irq_data->irq_en_reg,
0216                        1 << irq_data->irq_en_shift,
0217                        1 << irq_data->irq_en_shift);
0218         return 0;
0219     case SNDRV_PCM_TRIGGER_STOP:
0220     case SNDRV_PCM_TRIGGER_SUSPEND:
0221         if (afe_priv->xrun_assert[id] > 0) {
0222             if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
0223                 int avail = snd_pcm_capture_avail(runtime);
0224                 /* alsa can trigger stop/start when occur xrun */
0225                 if (avail >= runtime->buffer_size)
0226                     dev_dbg(afe->dev, "%s(), id %d, xrun assert\n",
0227                         __func__, id);
0228             }
0229         }
0230
0231         ret = mtk_memif_set_disable(afe, id);
0232         if (ret)
0233             dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
0234                 __func__, id, ret);
0235
0236         /* disable interrupt */
0237         if (runtime->stop_threshold != ~(0U))
0238             regmap_update_bits(afe->regmap,
0239                        irq_data->irq_en_reg,
0240                        1 << irq_data->irq_en_shift,
0241                        0 << irq_data->irq_en_shift);
0242
0243         /* clear pending IRQ */
0244         regmap_write(afe->regmap, irq_data->irq_clr_reg,
0245                  1 << irq_data->irq_clr_shift);
0246         return ret;
0247     default:
0248         return -EINVAL;
0249     }
0250 }
0251
0252 static int mt8186_memif_fs(struct snd_pcm_substream *substream,
0253                unsigned int rate)
0254 {
0255     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0256     struct snd_soc_component *component =
0257         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0258     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0259     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0260
0261     return mt8186_rate_transform(afe->dev, rate, id);
0262 }
0263
0264 static int mt8186_get_dai_fs(struct mtk_base_afe *afe,
0265                  int dai_id, unsigned int rate)
0266 {
0267     return mt8186_rate_transform(afe->dev, rate, dai_id);
0268 }
0269
0270 static int mt8186_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
0271 {
0272     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0273     struct snd_soc_component *component =
0274         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0275     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0276
0277     return mt8186_general_rate_transform(afe->dev, rate);
0278 }
0279
0280 static int mt8186_get_memif_pbuf_size(struct snd_pcm_substream *substream)
0281 {
0282     struct snd_pcm_runtime *runtime = substream->runtime;
0283
0284     if ((runtime->period_size * 1000) / runtime->rate > 10)
0285         return MT8186_MEMIF_PBUF_SIZE_256_BYTES;
0286
0287     return MT8186_MEMIF_PBUF_SIZE_32_BYTES;
0288 }
0289
0290 static int mt8186_fe_prepare(struct snd_pcm_substream *substream,
0291                  struct snd_soc_dai *dai)
0292 {
0293     struct snd_soc_pcm_runtime *rtd = substream->private_data;
0294     struct snd_pcm_runtime * const runtime = substream->runtime;
0295     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0296     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0297     struct mtk_base_afe_memif *memif = &afe->memif[id];
0298     int irq_id = memif->irq_usage;
0299     struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
0300     const struct mtk_base_irq_data *irq_data = irqs->irq_data;
0301     unsigned int counter = runtime->period_size;
0302     int fs;
0303     int ret;
0304
0305     ret = mtk_afe_fe_prepare(substream, dai);
0306     if (ret)
0307         return ret;
0308
0309     /* set irq counter */
0310     regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
0311                irq_data->irq_cnt_maskbit
0312                << irq_data->irq_cnt_shift,
0313                counter << irq_data->irq_cnt_shift);
0314
0315     /* set irq fs */
0316     fs = afe->irq_fs(substream, runtime->rate);
0317
0318     if (fs < 0)
0319         return -EINVAL;
0320
0321     regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
0322                irq_data->irq_fs_maskbit
0323                << irq_data->irq_fs_shift,
0324                fs << irq_data->irq_fs_shift);
0325
0326     return 0;
0327 }
0328
0329 /* FE DAIs */
0330 static const struct snd_soc_dai_ops mt8186_memif_dai_ops = {
0331     .startup    = mt8186_fe_startup,
0332     .shutdown   = mt8186_fe_shutdown,
0333     .hw_params  = mt8186_fe_hw_params,
0334     .hw_free    = mt8186_fe_hw_free,
0335     .prepare    = mt8186_fe_prepare,
0336     .trigger    = mt8186_fe_trigger,
0337 };
0338
0339 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
0340                SNDRV_PCM_RATE_88200 |\
0341                SNDRV_PCM_RATE_96000 |\
0342                SNDRV_PCM_RATE_176400 |\
0343                SNDRV_PCM_RATE_192000)
0344
0345 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
0346                SNDRV_PCM_RATE_16000 |\
0347                SNDRV_PCM_RATE_32000 |\
0348                SNDRV_PCM_RATE_48000)
0349
0350 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0351              SNDRV_PCM_FMTBIT_S24_LE |\
0352              SNDRV_PCM_FMTBIT_S32_LE)
0353
0354 static struct snd_soc_dai_driver mt8186_memif_dai_driver[] = {
0355     /* FE DAIs: memory intefaces to CPU */
0356     {
0357         .name = "DL1",
0358         .id = MT8186_MEMIF_DL1,
0359         .playback = {
0360             .stream_name = "DL1",
0361             .channels_min = 1,
0362             .channels_max = 2,
0363             .rates = MTK_PCM_RATES,
0364             .formats = MTK_PCM_FORMATS,
0365         },
0366         .ops = &mt8186_memif_dai_ops,
0367     },
0368     {
0369         .name = "DL12",
0370         .id = MT8186_MEMIF_DL12,
0371         .playback = {
0372             .stream_name = "DL12",
0373             .channels_min = 1,
0374             .channels_max = 4,
0375             .rates = MTK_PCM_RATES,
0376             .formats = MTK_PCM_FORMATS,
0377         },
0378         .ops = &mt8186_memif_dai_ops,
0379     },
0380     {
0381         .name = "DL2",
0382         .id = MT8186_MEMIF_DL2,
0383         .playback = {
0384             .stream_name = "DL2",
0385             .channels_min = 1,
0386             .channels_max = 2,
0387             .rates = MTK_PCM_RATES,
0388             .formats = MTK_PCM_FORMATS,
0389         },
0390         .ops = &mt8186_memif_dai_ops,
0391     },
0392     {
0393         .name = "DL3",
0394         .id = MT8186_MEMIF_DL3,
0395         .playback = {
0396             .stream_name = "DL3",
0397             .channels_min = 1,
0398             .channels_max = 2,
0399             .rates = MTK_PCM_RATES,
0400             .formats = MTK_PCM_FORMATS,
0401         },
0402         .ops = &mt8186_memif_dai_ops,
0403     },
0404     {
0405         .name = "DL4",
0406         .id = MT8186_MEMIF_DL4,
0407         .playback = {
0408             .stream_name = "DL4",
0409             .channels_min = 1,
0410             .channels_max = 2,
0411             .rates = MTK_PCM_RATES,
0412             .formats = MTK_PCM_FORMATS,
0413         },
0414         .ops = &mt8186_memif_dai_ops,
0415     },
0416     {
0417         .name = "DL5",
0418         .id = MT8186_MEMIF_DL5,
0419         .playback = {
0420             .stream_name = "DL5",
0421             .channels_min = 1,
0422             .channels_max = 2,
0423             .rates = MTK_PCM_RATES,
0424             .formats = MTK_PCM_FORMATS,
0425         },
0426         .ops = &mt8186_memif_dai_ops,
0427     },
0428     {
0429         .name = "DL6",
0430         .id = MT8186_MEMIF_DL6,
0431         .playback = {
0432             .stream_name = "DL6",
0433             .channels_min = 1,
0434             .channels_max = 2,
0435             .rates = MTK_PCM_RATES,
0436             .formats = MTK_PCM_FORMATS,
0437         },
0438         .ops = &mt8186_memif_dai_ops,
0439     },
0440     {
0441         .name = "DL7",
0442         .id = MT8186_MEMIF_DL7,
0443         .playback = {
0444             .stream_name = "DL7",
0445             .channels_min = 1,
0446             .channels_max = 2,
0447             .rates = MTK_PCM_RATES,
0448             .formats = MTK_PCM_FORMATS,
0449         },
0450         .ops = &mt8186_memif_dai_ops,
0451     },
0452     {
0453         .name = "DL8",
0454         .id = MT8186_MEMIF_DL8,
0455         .playback = {
0456             .stream_name = "DL8",
0457             .channels_min = 1,
0458             .channels_max = 2,
0459             .rates = MTK_PCM_RATES,
0460             .formats = MTK_PCM_FORMATS,
0461         },
0462         .ops = &mt8186_memif_dai_ops,
0463     },
0464     {
0465         .name = "UL1",
0466         .id = MT8186_MEMIF_VUL12,
0467         .capture = {
0468             .stream_name = "UL1",
0469             .channels_min = 1,
0470             .channels_max = 4,
0471             .rates = MTK_PCM_RATES,
0472             .formats = MTK_PCM_FORMATS,
0473         },
0474         .ops = &mt8186_memif_dai_ops,
0475     },
0476     {
0477         .name = "UL2",
0478         .id = MT8186_MEMIF_AWB,
0479         .capture = {
0480             .stream_name = "UL2",
0481             .channels_min = 1,
0482             .channels_max = 2,
0483             .rates = MTK_PCM_RATES,
0484             .formats = MTK_PCM_FORMATS,
0485         },
0486         .ops = &mt8186_memif_dai_ops,
0487     },
0488     {
0489         .name = "UL3",
0490         .id = MT8186_MEMIF_VUL2,
0491         .capture = {
0492             .stream_name = "UL3",
0493             .channels_min = 1,
0494             .channels_max = 2,
0495             .rates = MTK_PCM_RATES,
0496             .formats = MTK_PCM_FORMATS,
0497         },
0498         .ops = &mt8186_memif_dai_ops,
0499     },
0500     {
0501         .name = "UL4",
0502         .id = MT8186_MEMIF_AWB2,
0503         .capture = {
0504             .stream_name = "UL4",
0505             .channels_min = 1,
0506             .channels_max = 2,
0507             .rates = MTK_PCM_RATES,
0508             .formats = MTK_PCM_FORMATS,
0509         },
0510         .ops = &mt8186_memif_dai_ops,
0511     },
0512     {
0513         .name = "UL5",
0514         .id = MT8186_MEMIF_VUL3,
0515         .capture = {
0516             .stream_name = "UL5",
0517             .channels_min = 1,
0518             .channels_max = 12,
0519             .rates = MTK_PCM_RATES,
0520             .formats = MTK_PCM_FORMATS,
0521         },
0522         .ops = &mt8186_memif_dai_ops,
0523     },
0524     {
0525         .name = "UL6",
0526         .id = MT8186_MEMIF_VUL4,
0527         .capture = {
0528             .stream_name = "UL6",
0529             .channels_min = 1,
0530             .channels_max = 2,
0531             .rates = MTK_PCM_RATES,
0532             .formats = MTK_PCM_FORMATS,
0533         },
0534         .ops = &mt8186_memif_dai_ops,
0535     },
0536     {
0537         .name = "UL7",
0538         .id = MT8186_MEMIF_VUL5,
0539         .capture = {
0540             .stream_name = "UL7",
0541             .channels_min = 1,
0542             .channels_max = 2,
0543             .rates = MTK_PCM_RATES,
0544             .formats = MTK_PCM_FORMATS,
0545         },
0546         .ops = &mt8186_memif_dai_ops,
0547     },
0548     {
0549         .name = "UL8",
0550         .id = MT8186_MEMIF_VUL6,
0551         .capture = {
0552             .stream_name = "UL8",
0553             .channels_min = 1,
0554             .channels_max = 2,
0555             .rates = MTK_PCM_RATES,
0556             .formats = MTK_PCM_FORMATS,
0557         },
0558         .ops = &mt8186_memif_dai_ops,
0559     }
0560 };
0561
0562 /* kcontrol */
0563 static int mt8186_irq_cnt1_get(struct snd_kcontrol *kcontrol,
0564                    struct snd_ctl_elem_value *ucontrol)
0565 {
0566     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0567     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0568     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0569
0570     ucontrol->value.integer.value[0] =
0571         afe_priv->irq_cnt[MT8186_PRIMARY_MEMIF];
0572
0573     return 0;
0574 }
0575
0576 static int mt8186_irq_cnt1_set(struct snd_kcontrol *kcontrol,
0577                    struct snd_ctl_elem_value *ucontrol)
0578 {
0579     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0580     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0581     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0582     int memif_num = MT8186_PRIMARY_MEMIF;
0583     struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
0584     int irq_id = memif->irq_usage;
0585     int irq_cnt = afe_priv->irq_cnt[memif_num];
0586
0587     dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n",
0588         __func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]);
0589
0590     if (irq_cnt == ucontrol->value.integer.value[0])
0591         return 0;
0592
0593     irq_cnt = ucontrol->value.integer.value[0];
0594     afe_priv->irq_cnt[memif_num] = irq_cnt;
0595
0596     if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) {
0597         struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
0598         const struct mtk_base_irq_data *irq_data = irqs->irq_data;
0599
0600         regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
0601                    irq_data->irq_cnt_maskbit
0602                    << irq_data->irq_cnt_shift,
0603                    irq_cnt << irq_data->irq_cnt_shift);
0604     } else {
0605         dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n",
0606             __func__, irq_id);
0607     }
0608
0609     return 1;
0610 }
0611
0612 static int mt8186_irq_cnt2_get(struct snd_kcontrol *kcontrol,
0613                    struct snd_ctl_elem_value *ucontrol)
0614 {
0615     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0616     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0617     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0618
0619     ucontrol->value.integer.value[0] =
0620         afe_priv->irq_cnt[MT8186_RECORD_MEMIF];
0621
0622     return 0;
0623 }
0624
0625 static int mt8186_irq_cnt2_set(struct snd_kcontrol *kcontrol,
0626                    struct snd_ctl_elem_value *ucontrol)
0627 {
0628     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0629     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0630     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0631     int memif_num = MT8186_RECORD_MEMIF;
0632     struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
0633     int irq_id = memif->irq_usage;
0634     int irq_cnt = afe_priv->irq_cnt[memif_num];
0635
0636     dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n",
0637         __func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]);
0638
0639     if (irq_cnt == ucontrol->value.integer.value[0])
0640         return 0;
0641
0642     irq_cnt = ucontrol->value.integer.value[0];
0643     afe_priv->irq_cnt[memif_num] = irq_cnt;
0644
0645     if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) {
0646         struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
0647         const struct mtk_base_irq_data *irq_data = irqs->irq_data;
0648
0649         regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
0650                    irq_data->irq_cnt_maskbit
0651                    << irq_data->irq_cnt_shift,
0652                    irq_cnt << irq_data->irq_cnt_shift);
0653     } else {
0654         dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n",
0655             __func__, irq_id);
0656     }
0657
0658     return 1;
0659 }
0660
0661 static int mt8186_record_xrun_assert_get(struct snd_kcontrol *kcontrol,
0662                      struct snd_ctl_elem_value *ucontrol)
0663 {
0664     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0665     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0666     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0667     int xrun_assert = afe_priv->xrun_assert[MT8186_RECORD_MEMIF];
0668
0669     ucontrol->value.integer.value[0] = xrun_assert;
0670
0671     return 0;
0672 }
0673
0674 static int mt8186_record_xrun_assert_set(struct snd_kcontrol *kcontrol,
0675                      struct snd_ctl_elem_value *ucontrol)
0676 {
0677     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
0678     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0679     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0680     int xrun_assert = ucontrol->value.integer.value[0];
0681
0682     dev_dbg(afe->dev, "%s(), xrun_assert %d\n", __func__, xrun_assert);
0683
0684     if (xrun_assert == afe_priv->xrun_assert[MT8186_RECORD_MEMIF])
0685         return 0;
0686
0687     afe_priv->xrun_assert[MT8186_RECORD_MEMIF] = xrun_assert;
0688
0689     return 1;
0690 }
0691
0692 static const struct snd_kcontrol_new mt8186_pcm_kcontrols[] = {
0693     SOC_SINGLE_EXT("Audio IRQ1 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0,
0694                mt8186_irq_cnt1_get, mt8186_irq_cnt1_set),
0695     SOC_SINGLE_EXT("Audio IRQ2 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0,
0696                mt8186_irq_cnt2_get, mt8186_irq_cnt2_set),
0697     SOC_SINGLE_EXT("record_xrun_assert", SND_SOC_NOPM, 0, 0x1, 0,
0698                mt8186_record_xrun_assert_get,
0699                mt8186_record_xrun_assert_set),
0700 };
0701
0702 /* dma widget & routes*/
0703 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
0704     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN21,
0705                     I_ADDA_UL_CH1, 1, 0),
0706     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN21,
0707                     I_ADDA_UL_CH2, 1, 0),
0708     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN21,
0709                     I_ADDA_UL_CH3, 1, 0),
0710     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN21_1,
0711                     I_TDM_IN_CH1, 1, 0),
0712 };
0713
0714 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
0715     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN22,
0716                     I_ADDA_UL_CH1, 1, 0),
0717     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN22,
0718                     I_ADDA_UL_CH2, 1, 0),
0719     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN22,
0720                     I_ADDA_UL_CH3, 1, 0),
0721     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN22,
0722                     I_ADDA_UL_CH4, 1, 0),
0723     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN22_1,
0724                     I_TDM_IN_CH2, 1, 0),
0725 };
0726
0727 static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = {
0728     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN9,
0729                     I_ADDA_UL_CH1, 1, 0),
0730     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN9,
0731                     I_ADDA_UL_CH2, 1, 0),
0732     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN9,
0733                     I_ADDA_UL_CH3, 1, 0),
0734     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN9_1,
0735                     I_TDM_IN_CH3, 1, 0),
0736 };
0737
0738 static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = {
0739     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN10,
0740                     I_ADDA_UL_CH1, 1, 0),
0741     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN10,
0742                     I_ADDA_UL_CH2, 1, 0),
0743     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN10,
0744                     I_ADDA_UL_CH3, 1, 0),
0745     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN10,
0746                     I_ADDA_UL_CH4, 1, 0),
0747     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN10_1,
0748                     I_TDM_IN_CH4, 1, 0),
0749 };
0750
0751 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
0752     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN5,
0753                     I_I2S0_CH1, 1, 0),
0754     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN5,
0755                     I_DL1_CH1, 1, 0),
0756     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN5,
0757                     I_DL12_CH1, 1, 0),
0758     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN5,
0759                     I_DL2_CH1, 1, 0),
0760     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN5,
0761                     I_DL3_CH1, 1, 0),
0762     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN5_1,
0763                     I_DL4_CH1, 1, 0),
0764     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN5_1,
0765                     I_DL5_CH1, 1, 0),
0766     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN5_1,
0767                     I_DL6_CH1, 1, 0),
0768     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN5,
0769                     I_PCM_1_CAP_CH1, 1, 0),
0770     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN5,
0771                     I_I2S2_CH1, 1, 0),
0772     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN5_1,
0773                     I_CONNSYS_I2S_CH1, 1, 0),
0774     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN5_1,
0775                     I_SRC_1_OUT_CH1, 1, 0),
0776 };
0777
0778 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
0779     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN6,
0780                     I_I2S0_CH2, 1, 0),
0781     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN6,
0782                     I_DL1_CH2, 1, 0),
0783     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN6,
0784                     I_DL12_CH2, 1, 0),
0785     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN6,
0786                     I_DL2_CH2, 1, 0),
0787     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN6,
0788                     I_DL3_CH2, 1, 0),
0789     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN6_1,
0790                     I_DL4_CH2, 1, 0),
0791     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN6_1,
0792                     I_DL5_CH2, 1, 0),
0793     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN6_1,
0794                     I_DL6_CH2, 1, 0),
0795     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN6,
0796                     I_PCM_1_CAP_CH2, 1, 0),
0797     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN6,
0798                     I_I2S2_CH2, 1, 0),
0799     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN6_1,
0800                     I_CONNSYS_I2S_CH2, 1, 0),
0801     SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN6_1,
0802                     I_SRC_1_OUT_CH2, 1, 0),
0803 };
0804
0805 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
0806     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN32_1,
0807                     I_CONNSYS_I2S_CH1, 1, 0),
0808     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN32,
0809                     I_DL1_CH1, 1, 0),
0810     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN32,
0811                     I_DL2_CH1, 1, 0),
0812 };
0813
0814 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
0815     SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN33_1,
0816                     I_CONNSYS_I2S_CH2, 1, 0),
0817 };
0818
0819 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
0820     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN38,
0821                     I_ADDA_UL_CH1, 1, 0),
0822     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN38,
0823                     I_I2S0_CH1, 1, 0),
0824 };
0825
0826 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
0827     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN39,
0828                     I_ADDA_UL_CH2, 1, 0),
0829     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN39,
0830                     I_I2S0_CH2, 1, 0),
0831 };
0832
0833 static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
0834     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN44,
0835                     I_ADDA_UL_CH1, 1, 0),
0836 };
0837
0838 static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
0839     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN45,
0840                     I_ADDA_UL_CH2, 1, 0),
0841 };
0842
0843 static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
0844     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN46,
0845                     I_ADDA_UL_CH1, 1, 0),
0846     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN46,
0847                     I_DL1_CH1, 1, 0),
0848     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN46,
0849                     I_DL12_CH1, 1, 0),
0850     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN46_1,
0851                     I_DL6_CH1, 1, 0),
0852     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN46,
0853                     I_DL2_CH1, 1, 0),
0854     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN46,
0855                     I_DL3_CH1, 1, 0),
0856     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN46_1,
0857                     I_DL4_CH1, 1, 0),
0858     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN46,
0859                     I_PCM_1_CAP_CH1, 1, 0),
0860     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN46,
0861                     I_GAIN1_OUT_CH1, 1, 0),
0862 };
0863
0864 static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
0865     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN47,
0866                     I_ADDA_UL_CH2, 1, 0),
0867     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN47,
0868                     I_DL1_CH2, 1, 0),
0869     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN47,
0870                     I_DL12_CH2, 1, 0),
0871     SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN47_1,
0872                     I_DL6_CH2, 1, 0),
0873     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN47,
0874                     I_DL2_CH2, 1, 0),
0875     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN47,
0876                     I_DL3_CH2, 1, 0),
0877     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN47_1,
0878                     I_DL4_CH2, 1, 0),
0879     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN47,
0880                     I_PCM_1_CAP_CH2, 1, 0),
0881     SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN47,
0882                     I_GAIN1_OUT_CH2, 1, 0),
0883 };
0884
0885 static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
0886     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN48,
0887                     I_ADDA_UL_CH1, 1, 0),
0888     SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH1 Switch", AFE_CONN48,
0889                     I_GAIN2_OUT_CH1, 1, 0),
0890     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1 Switch", AFE_CONN48_1,
0891                     I_SRC_2_OUT_CH1, 1, 0),
0892 };
0893
0894 static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
0895     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN49,
0896                     I_ADDA_UL_CH2, 1, 0),
0897     SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH2 Switch", AFE_CONN49,
0898                     I_GAIN2_OUT_CH2, 1, 0),
0899     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2 Switch", AFE_CONN49_1,
0900                     I_SRC_2_OUT_CH2, 1, 0),
0901 };
0902
0903 static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
0904     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN50,
0905                     I_ADDA_UL_CH1, 1, 0),
0906 };
0907
0908 static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
0909     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN51,
0910                     I_ADDA_UL_CH2, 1, 0),
0911 };
0912
0913 static const struct snd_kcontrol_new hw_cm1_ch1_mix[] = {
0914     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN58_1,
0915                     I_TDM_IN_CH1, 1, 0),
0916     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN58,
0917                     I_I2S0_CH1, 1, 0),
0918     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN58,
0919                     I_I2S2_CH1, 1, 0),
0920     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN58,
0921                     I_ADDA_UL_CH1, 1, 0),
0922     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN58,
0923                     I_DL1_CH1, 1, 0),
0924     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN58,
0925                     I_DL12_CH1, 1, 0),
0926     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN58,
0927                     I_DL12_CH3, 1, 0),
0928     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN58,
0929                     I_DL2_CH1, 1, 0),
0930     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN58,
0931                     I_DL3_CH1, 1, 0),
0932     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN58_1,
0933                     I_DL4_CH1, 1, 0),
0934     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN58_1,
0935                     I_DL5_CH1, 1, 0),
0936     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN58_1,
0937                     I_SRC_1_OUT_CH1, 1, 0),
0938     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN58_1,
0939                     I_SRC_2_OUT_CH1, 1, 0),
0940 };
0941
0942 static const struct snd_kcontrol_new hw_cm1_ch2_mix[] = {
0943     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN59_1,
0944                     I_TDM_IN_CH2, 1, 0),
0945     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN59,
0946                     I_I2S0_CH2, 1, 0),
0947     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN59,
0948                     I_I2S2_CH2, 1, 0),
0949     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN59,
0950                     I_ADDA_UL_CH2, 1, 0),
0951     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN59,
0952                     I_DL1_CH2, 1, 0),
0953     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN59,
0954                     I_DL12_CH2, 1, 0),
0955     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN59,
0956                     I_DL12_CH4, 1, 0),
0957     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN59,
0958                     I_DL2_CH2, 1, 0),
0959     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN59,
0960                     I_DL3_CH2, 1, 0),
0961     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN59_1,
0962                     I_DL4_CH2, 1, 0),
0963     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN59_1,
0964                     I_DL5_CH2, 1, 0),
0965     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN59_1,
0966                     I_SRC_1_OUT_CH2, 1, 0),
0967     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN59_1,
0968                     I_SRC_2_OUT_CH2, 1, 0),
0969 };
0970
0971 static const struct snd_kcontrol_new hw_cm1_ch3_mix[] = {
0972     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN60_1,
0973                     I_TDM_IN_CH3, 1, 0),
0974     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN60,
0975                     I_I2S0_CH1, 1, 0),
0976     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN60,
0977                     I_I2S2_CH1, 1, 0),
0978     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN60,
0979                     I_ADDA_UL_CH1, 1, 0),
0980     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN60,
0981                     I_DL1_CH1, 1, 0),
0982     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN60,
0983                     I_DL12_CH1, 1, 0),
0984     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN60,
0985                     I_DL12_CH3, 1, 0),
0986     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN60,
0987                     I_DL2_CH1, 1, 0),
0988     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN60,
0989                     I_DL3_CH1, 1, 0),
0990     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN60_1,
0991                     I_DL4_CH1, 1, 0),
0992     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN60_1,
0993                     I_DL5_CH1, 1, 0),
0994     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN60_1,
0995                     I_SRC_1_OUT_CH1, 1, 0),
0996     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN60_1,
0997                     I_SRC_2_OUT_CH1, 1, 0),
0998 };
0999
1000 static const struct snd_kcontrol_new hw_cm1_ch4_mix[] = {
1001     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN61_1,
1002                     I_TDM_IN_CH4, 1, 0),
1003     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN61,
1004                     I_I2S0_CH2, 1, 0),
1005     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN61,
1006                     I_I2S2_CH2, 1, 0),
1007     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN61,
1008                     I_ADDA_UL_CH2, 1, 0),
1009     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN61,
1010                     I_DL1_CH2, 1, 0),
1011     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN61,
1012                     I_DL12_CH2, 1, 0),
1013     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN61,
1014                     I_DL12_CH4, 1, 0),
1015     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN61,
1016                     I_DL2_CH2, 1, 0),
1017     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN61,
1018                     I_DL3_CH2, 1, 0),
1019     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN61_1,
1020                     I_DL4_CH2, 1, 0),
1021     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN61_1,
1022                     I_DL5_CH2, 1, 0),
1023     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN61_1,
1024                     I_SRC_1_OUT_CH2, 1, 0),
1025     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN61_1,
1026                     I_SRC_2_OUT_CH2, 1, 0),
1027 };
1028
1029 static const struct snd_kcontrol_new hw_cm1_ch5_mix[] = {
1030     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH5 Switch", AFE_CONN62_1,
1031                     I_TDM_IN_CH5, 1, 0),
1032     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN62,
1033                     I_I2S0_CH1, 1, 0),
1034     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN62,
1035                     I_I2S2_CH1, 1, 0),
1036     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN62,
1037                     I_ADDA_UL_CH1, 1, 0),
1038     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN62,
1039                     I_DL1_CH1, 1, 0),
1040     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN62,
1041                     I_DL12_CH1, 1, 0),
1042     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN62,
1043                     I_DL12_CH3, 1, 0),
1044     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN62,
1045                     I_DL2_CH1, 1, 0),
1046     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN62,
1047                     I_DL3_CH1, 1, 0),
1048     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN62_1,
1049                     I_DL4_CH1, 1, 0),
1050     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN62_1,
1051                     I_DL5_CH1, 1, 0),
1052     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN62_1,
1053                     I_SRC_1_OUT_CH1, 1, 0),
1054     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN62_1,
1055                     I_SRC_2_OUT_CH1, 1, 0),
1056 };
1057
1058 static const struct snd_kcontrol_new hw_cm1_ch6_mix[] = {
1059     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH6 Switch", AFE_CONN63_1,
1060                     I_TDM_IN_CH6, 1, 0),
1061     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN63,
1062                     I_I2S0_CH2, 1, 0),
1063     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN63,
1064                     I_I2S2_CH2, 1, 0),
1065     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN63,
1066                     I_ADDA_UL_CH2, 1, 0),
1067     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN63,
1068                     I_DL1_CH2, 1, 0),
1069     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN63,
1070                     I_DL12_CH2, 1, 0),
1071     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN63,
1072                     I_DL12_CH4, 1, 0),
1073     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN63,
1074                     I_DL2_CH2, 1, 0),
1075     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN63,
1076                     I_DL3_CH2, 1, 0),
1077     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN63_1,
1078                     I_DL4_CH2, 1, 0),
1079     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN63_1,
1080                     I_DL5_CH2, 1, 0),
1081     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN63_1,
1082                     I_SRC_1_OUT_CH2, 1, 0),
1083     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN63_1,
1084                     I_SRC_2_OUT_CH2, 1, 0),
1085 };
1086
1087 static const struct snd_kcontrol_new hw_cm1_ch7_mix[] = {
1088     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH7 Switch", AFE_CONN64_1,
1089                     I_TDM_IN_CH7, 1, 0),
1090     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN64,
1091                     I_I2S0_CH1, 1, 0),
1092     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN64,
1093                     I_I2S2_CH1, 1, 0),
1094     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN64,
1095                     I_ADDA_UL_CH1, 1, 0),
1096     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN64,
1097                     I_DL1_CH1, 1, 0),
1098     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1v", AFE_CONN64,
1099                     I_DL12_CH1, 1, 0),
1100     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN64,
1101                     I_DL12_CH3, 1, 0),
1102     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN64,
1103                     I_DL2_CH1, 1, 0),
1104     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN64,
1105                     I_DL3_CH1, 1, 0),
1106     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN64_1,
1107                     I_DL4_CH1, 1, 0),
1108     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN64_1,
1109                     I_DL5_CH1, 1, 0),
1110     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN64_1,
1111                     I_SRC_1_OUT_CH1, 1, 0),
1112     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN64_1,
1113                     I_SRC_2_OUT_CH1, 1, 0),
1114 };
1115
1116 static const struct snd_kcontrol_new hw_cm1_ch8_mix[] = {
1117     SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH8 Switch", AFE_CONN65_1,
1118                     I_TDM_IN_CH8, 1, 0),
1119     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN65,
1120                     I_I2S0_CH2, 1, 0),
1121     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN65,
1122                     I_I2S2_CH2, 1, 0),
1123     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN65,
1124                     I_ADDA_UL_CH2, 1, 0),
1125     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN65,
1126                     I_DL1_CH2, 1, 0),
1127     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN65,
1128                     I_DL12_CH2, 1, 0),
1129     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN65,
1130                     I_DL12_CH4, 1, 0),
1131     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN65,
1132                     I_DL2_CH2, 1, 0),
1133     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN65,
1134                     I_DL3_CH2, 1, 0),
1135     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN65_1,
1136                     I_DL4_CH2, 1, 0),
1137     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN65_1,
1138                     I_DL5_CH2, 1, 0),
1139     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN65_1,
1140                     I_SRC_1_OUT_CH2, 1, 0),
1141     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN65_1,
1142                     I_SRC_2_OUT_CH2, 1, 0),
1143 };
1144
1145 static const struct snd_kcontrol_new hw_cm1_ch9_mix[] = {
1146     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN66,
1147                     I_I2S0_CH1, 1, 0),
1148     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN66,
1149                     I_I2S2_CH1, 1, 0),
1150     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN66,
1151                     I_ADDA_UL_CH1, 1, 0),
1152     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN66,
1153                     I_DL1_CH1, 1, 0),
1154     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN66,
1155                     I_DL12_CH1, 1, 0),
1156     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN66,
1157                     I_DL12_CH3, 1, 0),
1158     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN66,
1159                     I_DL2_CH1, 1, 0),
1160     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN66,
1161                     I_DL3_CH1, 1, 0),
1162     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN66_1,
1163                     I_DL4_CH1, 1, 0),
1164     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN66_1,
1165                     I_DL5_CH1, 1, 0),
1166     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN66_1,
1167                     I_SRC_1_OUT_CH1, 1, 0),
1168     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN66_1,
1169                     I_SRC_2_OUT_CH1, 1, 0),
1170 };
1171
1172 static const struct snd_kcontrol_new hw_cm1_ch10_mix[] = {
1173     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN67,
1174                     I_I2S0_CH2, 1, 0),
1175     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN67,
1176                     I_I2S2_CH2, 1, 0),
1177     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN67,
1178                     I_ADDA_UL_CH2, 1, 0),
1179     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN67,
1180                     I_DL1_CH2, 1, 0),
1181     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN67,
1182                     I_DL12_CH2, 1, 0),
1183     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN67,
1184                     I_DL12_CH4, 1, 0),
1185     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN67,
1186                     I_DL2_CH2, 1, 0),
1187     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN67,
1188                     I_DL3_CH2, 1, 0),
1189     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN67_1,
1190                     I_DL4_CH2, 1, 0),
1191     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN67_1,
1192                     I_DL5_CH2, 1, 0),
1193     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN67_1,
1194                     I_SRC_1_OUT_CH2, 1, 0),
1195     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN67_1,
1196                     I_SRC_2_OUT_CH2, 1, 0),
1197 };
1198
1199 static const struct snd_kcontrol_new hw_cm1_ch11_mix[] = {
1200     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN68,
1201                     I_I2S0_CH1, 1, 0),
1202     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN68,
1203                     I_I2S2_CH1, 1, 0),
1204     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN68,
1205                     I_ADDA_UL_CH1, 1, 0),
1206     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN68,
1207                     I_DL1_CH1, 1, 0),
1208     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN68,
1209                     I_DL12_CH1, 1, 0),
1210     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN68,
1211                     I_DL12_CH3, 1, 0),
1212     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN68,
1213                     I_DL2_CH1, 1, 0),
1214     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN68,
1215                     I_DL3_CH1, 1, 0),
1216     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN68_1,
1217                     I_DL4_CH1, 1, 0),
1218     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN68_1,
1219                     I_DL5_CH1, 1, 0),
1220     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN68_1,
1221                     I_SRC_1_OUT_CH1, 1, 0),
1222     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN68_1,
1223                     I_SRC_2_OUT_CH1, 1, 0),
1224 };
1225
1226 static const struct snd_kcontrol_new hw_cm1_ch12_mix[] = {
1227     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN69,
1228                     I_I2S0_CH2, 1, 0),
1229     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN69,
1230                     I_I2S2_CH2, 1, 0),
1231     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN69,
1232                     I_ADDA_UL_CH2, 1, 0),
1233     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN69,
1234                     I_DL1_CH2, 1, 0),
1235     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN69,
1236                     I_DL12_CH2, 1, 0),
1237     SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN69,
1238                     I_DL12_CH4, 1, 0),
1239     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN69,
1240                     I_DL2_CH2, 1, 0),
1241     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN69,
1242                     I_DL3_CH2, 1, 0),
1243     SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN69_1,
1244                     I_DL4_CH2, 1, 0),
1245     SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN69_1,
1246                     I_DL5_CH2, 1, 0),
1247     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN69_1,
1248                     I_SRC_1_OUT_CH2, 1, 0),
1249     SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN69_1,
1250                     I_SRC_2_OUT_CH2, 1, 0),
1251 };
1252
1253 /* ADDA UL MUX */
1254 enum {
1255     UL5_IN_MUX_CM1 = 0,
1256     UL5_IN_MUX_NORMAL,
1257     UL5_IN_MUX_MASK = 0x1,
1258 };
1259
1260 static const char * const ul5_in_mux_map[] = {
1261     "UL5_IN_FROM_CM1", "UL5_IN_FROM_Normal"
1262 };
1263
1264 static int ul5_in_map_value[] = {
1265     UL5_IN_MUX_CM1,
1266     UL5_IN_MUX_NORMAL,
1267 };
1268
1269 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_in_mux_map_enum,
1270                   AFE_CM1_CON,
1271                   VUL3_BYPASS_CM_SFT,
1272                   VUL3_BYPASS_CM_MASK,
1273                   ul5_in_mux_map,
1274                   ul5_in_map_value);
1275
1276 static const struct snd_kcontrol_new ul5_in_mux_control =
1277     SOC_DAPM_ENUM("UL5_IN_MUX Select", ul5_in_mux_map_enum);
1278
1279 static const struct snd_soc_dapm_widget mt8186_memif_widgets[] = {
1280     /* inter-connections */
1281     SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
1282                memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
1283     SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
1284                memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
1285     SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0,
1286                memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)),
1287     SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0,
1288                memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)),
1289
1290     SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
1291                memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
1292     SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
1293                memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
1294
1295     SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
1296                memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
1297     SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
1298                memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
1299
1300     SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
1301                memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
1302     SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
1303                memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
1304
1305     SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
1306                memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
1307     SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
1308                memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
1309
1310     SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
1311                memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
1312     SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
1313                memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
1314
1315     SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
1316                memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
1317     SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
1318                memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
1319
1320     SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
1321                memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
1322     SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
1323                memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
1324
1325     SND_SOC_DAPM_MIXER("UL5_2CH", SND_SOC_NOPM, 0, 0, NULL, 0),
1326
1327     SND_SOC_DAPM_MIXER("HW_CM1", SND_SOC_NOPM, 0, 0, NULL, 0),
1328
1329     /* CM1 en*/
1330     SND_SOC_DAPM_SUPPLY_S("CM1_EN", 0, AFE_CM1_CON,
1331                   CHANNEL_MERGE0_EN_SFT, 0, NULL,
1332                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1333
1334     SND_SOC_DAPM_MIXER("HW_CM1_CH1", SND_SOC_NOPM, 0, 0,
1335                hw_cm1_ch1_mix, ARRAY_SIZE(hw_cm1_ch1_mix)),
1336     SND_SOC_DAPM_MIXER("HW_CM1_CH2", SND_SOC_NOPM, 0, 0,
1337                hw_cm1_ch2_mix, ARRAY_SIZE(hw_cm1_ch2_mix)),
1338     SND_SOC_DAPM_MIXER("HW_CM1_CH3", SND_SOC_NOPM, 0, 0,
1339                hw_cm1_ch3_mix, ARRAY_SIZE(hw_cm1_ch3_mix)),
1340     SND_SOC_DAPM_MIXER("HW_CM1_CH4", SND_SOC_NOPM, 0, 0,
1341                hw_cm1_ch4_mix, ARRAY_SIZE(hw_cm1_ch4_mix)),
1342     SND_SOC_DAPM_MIXER("HW_CM1_CH5", SND_SOC_NOPM, 0, 0,
1343                hw_cm1_ch5_mix, ARRAY_SIZE(hw_cm1_ch5_mix)),
1344     SND_SOC_DAPM_MIXER("HW_CM1_CH6", SND_SOC_NOPM, 0, 0,
1345                hw_cm1_ch6_mix, ARRAY_SIZE(hw_cm1_ch6_mix)),
1346     SND_SOC_DAPM_MIXER("HW_CM1_CH7", SND_SOC_NOPM, 0, 0,
1347                hw_cm1_ch7_mix, ARRAY_SIZE(hw_cm1_ch7_mix)),
1348     SND_SOC_DAPM_MIXER("HW_CM1_CH8", SND_SOC_NOPM, 0, 0,
1349                hw_cm1_ch8_mix, ARRAY_SIZE(hw_cm1_ch8_mix)),
1350     SND_SOC_DAPM_MIXER("HW_CM1_CH9", SND_SOC_NOPM, 0, 0,
1351                hw_cm1_ch9_mix, ARRAY_SIZE(hw_cm1_ch9_mix)),
1352     SND_SOC_DAPM_MIXER("HW_CM1_CH10", SND_SOC_NOPM, 0, 0,
1353                hw_cm1_ch10_mix, ARRAY_SIZE(hw_cm1_ch10_mix)),
1354     SND_SOC_DAPM_MIXER("HW_CM1_CH11", SND_SOC_NOPM, 0, 0,
1355                hw_cm1_ch11_mix, ARRAY_SIZE(hw_cm1_ch11_mix)),
1356     SND_SOC_DAPM_MIXER("HW_CM1_CH12", SND_SOC_NOPM, 0, 0,
1357                hw_cm1_ch12_mix, ARRAY_SIZE(hw_cm1_ch12_mix)),
1358
1359     SND_SOC_DAPM_MUX("UL5_IN_MUX", SND_SOC_NOPM, 0, 0,
1360              &ul5_in_mux_control),
1361
1362     SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"),
1363     SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"),
1364     SND_SOC_DAPM_INPUT("UL3_VIRTUAL_INPUT"),
1365     SND_SOC_DAPM_INPUT("UL4_VIRTUAL_INPUT"),
1366     SND_SOC_DAPM_INPUT("UL5_VIRTUAL_INPUT"),
1367     SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"),
1368 };
1369
1370 static const struct snd_soc_dapm_route mt8186_memif_routes[] = {
1371     {"UL1", NULL, "UL1_CH1"},
1372     {"UL1", NULL, "UL1_CH2"},
1373     {"UL1", NULL, "UL1_CH3"},
1374     {"UL1", NULL, "UL1_CH4"},
1375     {"UL1_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1376     {"UL1_CH1", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1377     {"UL1_CH2", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1378     {"UL1_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1379     {"UL1_CH3", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1380     {"UL1_CH3", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1381     {"UL1_CH4", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1382     {"UL1_CH4", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1383     {"UL1_CH1", "TDM_IN_CH1 Switch", "TDM IN"},
1384     {"UL1_CH2", "TDM_IN_CH2 Switch", "TDM IN"},
1385     {"UL1_CH3", "TDM_IN_CH3 Switch", "TDM IN"},
1386     {"UL1_CH4", "TDM_IN_CH4 Switch", "TDM IN"},
1387
1388     {"UL2", NULL, "UL2_CH1"},
1389     {"UL2", NULL, "UL2_CH2"},
1390
1391     /* cannot connect FE to FE directly */
1392     {"UL2_CH1", "DL1_CH1 Switch", "Hostless_UL2 UL"},
1393     {"UL2_CH2", "DL1_CH2 Switch", "Hostless_UL2 UL"},
1394     {"UL2_CH1", "DL12_CH1 Switch", "Hostless_UL2 UL"},
1395     {"UL2_CH2", "DL12_CH2 Switch", "Hostless_UL2 UL"},
1396     {"UL2_CH1", "DL6_CH1 Switch", "Hostless_UL2 UL"},
1397     {"UL2_CH2", "DL6_CH2 Switch", "Hostless_UL2 UL"},
1398     {"UL2_CH1", "DL2_CH1 Switch", "Hostless_UL2 UL"},
1399     {"UL2_CH2", "DL2_CH2 Switch", "Hostless_UL2 UL"},
1400     {"UL2_CH1", "DL3_CH1 Switch", "Hostless_UL2 UL"},
1401     {"UL2_CH2", "DL3_CH2 Switch", "Hostless_UL2 UL"},
1402     {"UL2_CH1", "DL4_CH1 Switch", "Hostless_UL2 UL"},
1403     {"UL2_CH2", "DL4_CH2 Switch", "Hostless_UL2 UL"},
1404     {"UL2_CH1", "DL5_CH1 Switch", "Hostless_UL2 UL"},
1405     {"UL2_CH2", "DL5_CH2 Switch", "Hostless_UL2 UL"},
1406
1407     {"Hostless_UL2 UL", NULL, "UL2_VIRTUAL_INPUT"},
1408
1409     {"UL2_CH1", "I2S0_CH1 Switch", "I2S0"},
1410     {"UL2_CH2", "I2S0_CH2 Switch", "I2S0"},
1411     {"UL2_CH1", "I2S2_CH1 Switch", "I2S2"},
1412     {"UL2_CH2", "I2S2_CH2 Switch", "I2S2"},
1413
1414     {"UL2_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"},
1415     {"UL2_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"},
1416
1417     {"UL2_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"},
1418     {"UL2_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"},
1419
1420     {"UL2_CH1", "SRC_1_OUT_CH1 Switch", "HW_SRC_1_Out"},
1421     {"UL2_CH2", "SRC_1_OUT_CH2 Switch", "HW_SRC_1_Out"},
1422
1423     {"UL3", NULL, "UL3_CH1"},
1424     {"UL3", NULL, "UL3_CH2"},
1425     {"UL3_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"},
1426     {"UL3_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"},
1427
1428     {"UL4", NULL, "UL4_CH1"},
1429     {"UL4", NULL, "UL4_CH2"},
1430     {"UL4_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1431     {"UL4_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1432     {"UL4_CH1", "I2S0_CH1 Switch", "I2S0"},
1433     {"UL4_CH2", "I2S0_CH2 Switch", "I2S0"},
1434
1435     {"UL5", NULL, "UL5_IN_MUX"},
1436     {"UL5_IN_MUX", "UL5_IN_FROM_Normal", "UL5_2CH"},
1437     {"UL5_IN_MUX", "UL5_IN_FROM_CM1", "HW_CM1"},
1438     {"UL5_2CH", NULL, "UL5_CH1"},
1439     {"UL5_2CH", NULL, "UL5_CH2"},
1440     {"UL5_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1441     {"UL5_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1442     {"HW_CM1", NULL, "CM1_EN"},
1443     {"HW_CM1", NULL, "HW_CM1_CH1"},
1444     {"HW_CM1", NULL, "HW_CM1_CH2"},
1445     {"HW_CM1", NULL, "HW_CM1_CH3"},
1446     {"HW_CM1", NULL, "HW_CM1_CH4"},
1447     {"HW_CM1", NULL, "HW_CM1_CH5"},
1448     {"HW_CM1", NULL, "HW_CM1_CH6"},
1449     {"HW_CM1", NULL, "HW_CM1_CH7"},
1450     {"HW_CM1", NULL, "HW_CM1_CH8"},
1451     {"HW_CM1", NULL, "HW_CM1_CH9"},
1452     {"HW_CM1", NULL, "HW_CM1_CH10"},
1453     {"HW_CM1", NULL, "HW_CM1_CH11"},
1454     {"HW_CM1", NULL, "HW_CM1_CH12"},
1455     {"HW_CM1_CH1", "TDM_IN_CH1 Switch", "TDM IN"},
1456     {"HW_CM1_CH2", "TDM_IN_CH2 Switch", "TDM IN"},
1457     {"HW_CM1_CH3", "TDM_IN_CH3 Switch", "TDM IN"},
1458     {"HW_CM1_CH4", "TDM_IN_CH4 Switch", "TDM IN"},
1459     {"HW_CM1_CH5", "TDM_IN_CH5 Switch", "TDM IN"},
1460     {"HW_CM1_CH6", "TDM_IN_CH6 Switch", "TDM IN"},
1461     {"HW_CM1_CH7", "TDM_IN_CH7 Switch", "TDM IN"},
1462     {"HW_CM1_CH8", "TDM_IN_CH8 Switch", "TDM IN"},
1463     {"HW_CM1_CH9", "DL1_CH1 Switch", "Hostless_UL5 UL"},
1464     {"HW_CM1_CH10", "DL1_CH2 Switch", "Hostless_UL5 UL"},
1465
1466     {"HW_CM1_CH3", "DL1_CH1 Switch", "Hostless_UL5 UL"},
1467     {"HW_CM1_CH4", "DL1_CH2 Switch", "Hostless_UL5 UL"},
1468
1469     {"HW_CM1_CH3", "DL3_CH1 Switch", "Hostless_UL5 UL"},
1470     {"HW_CM1_CH4", "DL3_CH2 Switch", "Hostless_UL5 UL"},
1471
1472     {"HW_CM1_CH5", "HW_SRC1_OUT_CH1 Switch", "HW_SRC_1_Out"},
1473     {"HW_CM1_CH6", "HW_SRC1_OUT_CH2 Switch", "HW_SRC_1_Out"},
1474
1475     {"HW_CM1_CH9", "DL12_CH1 Switch", "Hostless_UL5 UL"},
1476     {"HW_CM1_CH10", "DL12_CH2 Switch", "Hostless_UL5 UL"},
1477     {"HW_CM1_CH11", "DL12_CH3 Switch", "Hostless_UL5 UL"},
1478     {"HW_CM1_CH12", "DL12_CH4 Switch", "Hostless_UL5 UL"},
1479
1480     {"Hostless_UL5 UL", NULL, "UL5_VIRTUAL_INPUT"},
1481
1482     {"UL6", NULL, "UL6_CH1"},
1483     {"UL6", NULL, "UL6_CH2"},
1484
1485     {"UL6_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1486     {"UL6_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1487     {"UL6_CH1", "DL1_CH1 Switch", "Hostless_UL6 UL"},
1488     {"UL6_CH2", "DL1_CH2 Switch", "Hostless_UL6 UL"},
1489     {"UL6_CH1", "DL2_CH1 Switch", "Hostless_UL6 UL"},
1490     {"UL6_CH2", "DL2_CH2 Switch", "Hostless_UL6 UL"},
1491     {"UL6_CH1", "DL12_CH1 Switch", "Hostless_UL6 UL"},
1492     {"UL6_CH2", "DL12_CH2 Switch", "Hostless_UL6 UL"},
1493     {"UL6_CH1", "DL6_CH1 Switch", "Hostless_UL6 UL"},
1494     {"UL6_CH2", "DL6_CH2 Switch", "Hostless_UL6 UL"},
1495     {"UL6_CH1", "DL3_CH1 Switch", "Hostless_UL6 UL"},
1496     {"UL6_CH2", "DL3_CH2 Switch", "Hostless_UL6 UL"},
1497     {"UL6_CH1", "DL4_CH1 Switch", "Hostless_UL6 UL"},
1498     {"UL6_CH2", "DL4_CH2 Switch", "Hostless_UL6 UL"},
1499     {"Hostless_UL6 UL", NULL, "UL6_VIRTUAL_INPUT"},
1500     {"UL6_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"},
1501     {"UL6_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"},
1502     {"UL6_CH1", "GAIN1_OUT_CH1 Switch", "HW Gain 1 Out"},
1503     {"UL6_CH2", "GAIN1_OUT_CH2 Switch", "HW Gain 1 Out"},
1504
1505     {"UL7", NULL, "UL7_CH1"},
1506     {"UL7", NULL, "UL7_CH2"},
1507     {"UL7_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1508     {"UL7_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1509     {"UL7_CH1", "HW_GAIN2_OUT_CH1 Switch", "HW Gain 2 Out"},
1510     {"UL7_CH2", "HW_GAIN2_OUT_CH2 Switch", "HW Gain 2 Out"},
1511     {"UL7_CH1", "HW_SRC_2_OUT_CH1 Switch", "HW_SRC_2_Out"},
1512     {"UL7_CH2", "HW_SRC_2_OUT_CH2 Switch", "HW_SRC_2_Out"},
1513
1514     {"UL8", NULL, "UL8_CH1"},
1515     {"UL8", NULL, "UL8_CH2"},
1516     {"UL8_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1517     {"UL8_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1518
1519     {"HW_GAIN2_IN_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
1520     {"HW_GAIN2_IN_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
1521 };
1522
1523 static const struct mtk_base_memif_data memif_data[MT8186_MEMIF_NUM] = {
1524     [MT8186_MEMIF_DL1] = {
1525         .name = "DL1",
1526         .id = MT8186_MEMIF_DL1,
1527         .reg_ofs_base = AFE_DL1_BASE,
1528         .reg_ofs_cur = AFE_DL1_CUR,
1529         .reg_ofs_end = AFE_DL1_END,
1530         .reg_ofs_base_msb = AFE_DL1_BASE_MSB,
1531         .reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
1532         .reg_ofs_end_msb = AFE_DL1_END_MSB,
1533         .fs_reg = AFE_DL1_CON0,
1534         .fs_shift = DL1_MODE_SFT,
1535         .fs_maskbit = DL1_MODE_MASK,
1536         .mono_reg = AFE_DL1_CON0,
1537         .mono_shift = DL1_MONO_SFT,
1538         .enable_reg = AFE_DAC_CON0,
1539         .enable_shift = DL1_ON_SFT,
1540         .hd_reg = AFE_DL1_CON0,
1541         .hd_shift = DL1_HD_MODE_SFT,
1542         .hd_align_reg = AFE_DL1_CON0,
1543         .hd_align_mshift = DL1_HALIGN_SFT,
1544         .agent_disable_reg = -1,
1545         .agent_disable_shift = -1,
1546         .msb_reg = -1,
1547         .msb_shift = -1,
1548         .pbuf_reg = AFE_DL1_CON0,
1549         .pbuf_mask = DL1_PBUF_SIZE_MASK,
1550         .pbuf_shift = DL1_PBUF_SIZE_SFT,
1551         .minlen_reg = AFE_DL1_CON0,
1552         .minlen_mask = DL1_MINLEN_MASK,
1553         .minlen_shift = DL1_MINLEN_SFT,
1554     },
1555     [MT8186_MEMIF_DL12] = {
1556         .name = "DL12",
1557         .id = MT8186_MEMIF_DL12,
1558         .reg_ofs_base = AFE_DL12_BASE,
1559         .reg_ofs_cur = AFE_DL12_CUR,
1560         .reg_ofs_end = AFE_DL12_END,
1561         .reg_ofs_base_msb = AFE_DL12_BASE_MSB,
1562         .reg_ofs_cur_msb = AFE_DL12_CUR_MSB,
1563         .reg_ofs_end_msb = AFE_DL12_END_MSB,
1564         .fs_reg = AFE_DL12_CON0,
1565         .fs_shift = DL12_MODE_SFT,
1566         .fs_maskbit = DL12_MODE_MASK,
1567         .mono_reg = AFE_DL12_CON0,
1568         .mono_shift = DL12_MONO_SFT,
1569         .quad_ch_reg = AFE_DL12_CON0,
1570         .quad_ch_mask = DL12_4CH_EN_MASK,
1571         .quad_ch_shift = DL12_4CH_EN_SFT,
1572         .enable_reg = AFE_DAC_CON0,
1573         .enable_shift = DL12_ON_SFT,
1574         .hd_reg = AFE_DL12_CON0,
1575         .hd_shift = DL12_HD_MODE_SFT,
1576         .hd_align_reg = AFE_DL12_CON0,
1577         .hd_align_mshift = DL12_HALIGN_SFT,
1578         .agent_disable_reg = -1,
1579         .agent_disable_shift = -1,
1580         .msb_reg = -1,
1581         .msb_shift = -1,
1582         .pbuf_reg = AFE_DL12_CON0,
1583         .pbuf_mask = DL12_PBUF_SIZE_MASK,
1584         .pbuf_shift = DL12_PBUF_SIZE_SFT,
1585         .minlen_reg = AFE_DL12_CON0,
1586         .minlen_mask = DL12_MINLEN_MASK,
1587         .minlen_shift = DL12_MINLEN_SFT,
1588     },
1589     [MT8186_MEMIF_DL2] = {
1590         .name = "DL2",
1591         .id = MT8186_MEMIF_DL2,
1592         .reg_ofs_base = AFE_DL2_BASE,
1593         .reg_ofs_cur = AFE_DL2_CUR,
1594         .reg_ofs_end = AFE_DL2_END,
1595         .reg_ofs_base_msb = AFE_DL2_BASE_MSB,
1596         .reg_ofs_cur_msb = AFE_DL2_CUR_MSB,
1597         .reg_ofs_end_msb = AFE_DL2_END_MSB,
1598         .fs_reg = AFE_DL2_CON0,
1599         .fs_shift = DL2_MODE_SFT,
1600         .fs_maskbit = DL2_MODE_MASK,
1601         .mono_reg = AFE_DL2_CON0,
1602         .mono_shift = DL2_MONO_SFT,
1603         .enable_reg = AFE_DAC_CON0,
1604         .enable_shift = DL2_ON_SFT,
1605         .hd_reg = AFE_DL2_CON0,
1606         .hd_shift = DL2_HD_MODE_SFT,
1607         .hd_align_reg = AFE_DL2_CON0,
1608         .hd_align_mshift = DL2_HALIGN_SFT,
1609         .agent_disable_reg = -1,
1610         .agent_disable_shift = -1,
1611         .msb_reg = -1,
1612         .msb_shift = -1,
1613         .pbuf_reg = AFE_DL2_CON0,
1614         .pbuf_mask = DL2_PBUF_SIZE_MASK,
1615         .pbuf_shift = DL2_PBUF_SIZE_SFT,
1616         .minlen_reg = AFE_DL2_CON0,
1617         .minlen_mask = DL2_MINLEN_MASK,
1618         .minlen_shift = DL2_MINLEN_SFT,
1619     },
1620     [MT8186_MEMIF_DL3] = {
1621         .name = "DL3",
1622         .id = MT8186_MEMIF_DL3,
1623         .reg_ofs_base = AFE_DL3_BASE,
1624         .reg_ofs_cur = AFE_DL3_CUR,
1625         .reg_ofs_end = AFE_DL3_END,
1626         .reg_ofs_base_msb = AFE_DL3_BASE_MSB,
1627         .reg_ofs_cur_msb = AFE_DL3_CUR_MSB,
1628         .reg_ofs_end_msb = AFE_DL3_END_MSB,
1629         .fs_reg = AFE_DL3_CON0,
1630         .fs_shift = DL3_MODE_SFT,
1631         .fs_maskbit = DL3_MODE_MASK,
1632         .mono_reg = AFE_DL3_CON0,
1633         .mono_shift = DL3_MONO_SFT,
1634         .enable_reg = AFE_DAC_CON0,
1635         .enable_shift = DL3_ON_SFT,
1636         .hd_reg = AFE_DL3_CON0,
1637         .hd_shift = DL3_HD_MODE_SFT,
1638         .hd_align_reg = AFE_DL3_CON0,
1639         .hd_align_mshift = DL3_HALIGN_SFT,
1640         .agent_disable_reg = -1,
1641         .agent_disable_shift = -1,
1642         .msb_reg = -1,
1643         .msb_shift = -1,
1644         .pbuf_reg = AFE_DL3_CON0,
1645         .pbuf_mask = DL3_PBUF_SIZE_MASK,
1646         .pbuf_shift = DL3_PBUF_SIZE_SFT,
1647         .minlen_reg = AFE_DL3_CON0,
1648         .minlen_mask = DL3_MINLEN_MASK,
1649         .minlen_shift = DL3_MINLEN_SFT,
1650     },
1651     [MT8186_MEMIF_DL4] = {
1652         .name = "DL4",
1653         .id = MT8186_MEMIF_DL4,
1654         .reg_ofs_base = AFE_DL4_BASE,
1655         .reg_ofs_cur = AFE_DL4_CUR,
1656         .reg_ofs_end = AFE_DL4_END,
1657         .reg_ofs_base_msb = AFE_DL4_BASE_MSB,
1658         .reg_ofs_cur_msb = AFE_DL4_CUR_MSB,
1659         .reg_ofs_end_msb = AFE_DL4_END_MSB,
1660         .fs_reg = AFE_DL4_CON0,
1661         .fs_shift = DL4_MODE_SFT,
1662         .fs_maskbit = DL4_MODE_MASK,
1663         .mono_reg = AFE_DL4_CON0,
1664         .mono_shift = DL4_MONO_SFT,
1665         .enable_reg = AFE_DAC_CON0,
1666         .enable_shift = DL4_ON_SFT,
1667         .hd_reg = AFE_DL4_CON0,
1668         .hd_shift = DL4_HD_MODE_SFT,
1669         .hd_align_reg = AFE_DL4_CON0,
1670         .hd_align_mshift = DL4_HALIGN_SFT,
1671         .agent_disable_reg = -1,
1672         .agent_disable_shift = -1,
1673         .msb_reg = -1,
1674         .msb_shift = -1,
1675         .pbuf_reg = AFE_DL4_CON0,
1676         .pbuf_mask = DL4_PBUF_SIZE_MASK,
1677         .pbuf_shift = DL4_PBUF_SIZE_SFT,
1678         .minlen_reg = AFE_DL4_CON0,
1679         .minlen_mask = DL4_MINLEN_MASK,
1680         .minlen_shift = DL4_MINLEN_SFT,
1681     },
1682     [MT8186_MEMIF_DL5] = {
1683         .name = "DL5",
1684         .id = MT8186_MEMIF_DL5,
1685         .reg_ofs_base = AFE_DL5_BASE,
1686         .reg_ofs_cur = AFE_DL5_CUR,
1687         .reg_ofs_end = AFE_DL5_END,
1688         .reg_ofs_base_msb = AFE_DL5_BASE_MSB,
1689         .reg_ofs_cur_msb = AFE_DL5_CUR_MSB,
1690         .reg_ofs_end_msb = AFE_DL5_END_MSB,
1691         .fs_reg = AFE_DL5_CON0,
1692         .fs_shift = DL5_MODE_SFT,
1693         .fs_maskbit = DL5_MODE_MASK,
1694         .mono_reg = AFE_DL5_CON0,
1695         .mono_shift = DL5_MONO_SFT,
1696         .enable_reg = AFE_DAC_CON0,
1697         .enable_shift = DL5_ON_SFT,
1698         .hd_reg = AFE_DL5_CON0,
1699         .hd_shift = DL5_HD_MODE_SFT,
1700         .hd_align_reg = AFE_DL5_CON0,
1701         .hd_align_mshift = DL5_HALIGN_SFT,
1702         .agent_disable_reg = -1,
1703         .agent_disable_shift = -1,
1704         .msb_reg = -1,
1705         .msb_shift = -1,
1706         .pbuf_reg = AFE_DL5_CON0,
1707         .pbuf_mask = DL5_PBUF_SIZE_MASK,
1708         .pbuf_shift = DL5_PBUF_SIZE_SFT,
1709         .minlen_reg = AFE_DL5_CON0,
1710         .minlen_mask = DL5_MINLEN_MASK,
1711         .minlen_shift = DL5_MINLEN_SFT,
1712     },
1713     [MT8186_MEMIF_DL6] = {
1714         .name = "DL6",
1715         .id = MT8186_MEMIF_DL6,
1716         .reg_ofs_base = AFE_DL6_BASE,
1717         .reg_ofs_cur = AFE_DL6_CUR,
1718         .reg_ofs_end = AFE_DL6_END,
1719         .reg_ofs_base_msb = AFE_DL6_BASE_MSB,
1720         .reg_ofs_cur_msb = AFE_DL6_CUR_MSB,
1721         .reg_ofs_end_msb = AFE_DL6_END_MSB,
1722         .fs_reg = AFE_DL6_CON0,
1723         .fs_shift = DL6_MODE_SFT,
1724         .fs_maskbit = DL6_MODE_MASK,
1725         .mono_reg = AFE_DL6_CON0,
1726         .mono_shift = DL6_MONO_SFT,
1727         .enable_reg = AFE_DAC_CON0,
1728         .enable_shift = DL6_ON_SFT,
1729         .hd_reg = AFE_DL6_CON0,
1730         .hd_shift = DL6_HD_MODE_SFT,
1731         .hd_align_reg = AFE_DL6_CON0,
1732         .hd_align_mshift = DL6_HALIGN_SFT,
1733         .agent_disable_reg = -1,
1734         .agent_disable_shift = -1,
1735         .msb_reg = -1,
1736         .msb_shift = -1,
1737         .pbuf_reg = AFE_DL6_CON0,
1738         .pbuf_mask = DL6_PBUF_SIZE_MASK,
1739         .pbuf_shift = DL6_PBUF_SIZE_SFT,
1740         .minlen_reg = AFE_DL6_CON0,
1741         .minlen_mask = DL6_MINLEN_MASK,
1742         .minlen_shift = DL6_MINLEN_SFT,
1743     },
1744     [MT8186_MEMIF_DL7] = {
1745         .name = "DL7",
1746         .id = MT8186_MEMIF_DL7,
1747         .reg_ofs_base = AFE_DL7_BASE,
1748         .reg_ofs_cur = AFE_DL7_CUR,
1749         .reg_ofs_end = AFE_DL7_END,
1750         .reg_ofs_base_msb = AFE_DL7_BASE_MSB,
1751         .reg_ofs_cur_msb = AFE_DL7_CUR_MSB,
1752         .reg_ofs_end_msb = AFE_DL7_END_MSB,
1753         .fs_reg = AFE_DL7_CON0,
1754         .fs_shift = DL7_MODE_SFT,
1755         .fs_maskbit = DL7_MODE_MASK,
1756         .mono_reg = AFE_DL7_CON0,
1757         .mono_shift = DL7_MONO_SFT,
1758         .enable_reg = AFE_DAC_CON0,
1759         .enable_shift = DL7_ON_SFT,
1760         .hd_reg = AFE_DL7_CON0,
1761         .hd_shift = DL7_HD_MODE_SFT,
1762         .hd_align_reg = AFE_DL7_CON0,
1763         .hd_align_mshift = DL7_HALIGN_SFT,
1764         .agent_disable_reg = -1,
1765         .agent_disable_shift = -1,
1766         .msb_reg = -1,
1767         .msb_shift = -1,
1768         .pbuf_reg = AFE_DL7_CON0,
1769         .pbuf_mask = DL7_PBUF_SIZE_MASK,
1770         .pbuf_shift = DL7_PBUF_SIZE_SFT,
1771         .minlen_reg = AFE_DL7_CON0,
1772         .minlen_mask = DL7_MINLEN_MASK,
1773         .minlen_shift = DL7_MINLEN_SFT,
1774     },
1775     [MT8186_MEMIF_DL8] = {
1776         .name = "DL8",
1777         .id = MT8186_MEMIF_DL8,
1778         .reg_ofs_base = AFE_DL8_BASE,
1779         .reg_ofs_cur = AFE_DL8_CUR,
1780         .reg_ofs_end = AFE_DL8_END,
1781         .reg_ofs_base_msb = AFE_DL8_BASE_MSB,
1782         .reg_ofs_cur_msb = AFE_DL8_CUR_MSB,
1783         .reg_ofs_end_msb = AFE_DL8_END_MSB,
1784         .fs_reg = AFE_DL8_CON0,
1785         .fs_shift = DL8_MODE_SFT,
1786         .fs_maskbit = DL8_MODE_MASK,
1787         .mono_reg = AFE_DL8_CON0,
1788         .mono_shift = DL8_MONO_SFT,
1789         .enable_reg = AFE_DAC_CON0,
1790         .enable_shift = DL8_ON_SFT,
1791         .hd_reg = AFE_DL8_CON0,
1792         .hd_shift = DL8_HD_MODE_SFT,
1793         .hd_align_reg = AFE_DL8_CON0,
1794         .hd_align_mshift = DL8_HALIGN_SFT,
1795         .agent_disable_reg = -1,
1796         .agent_disable_shift = -1,
1797         .msb_reg = -1,
1798         .msb_shift = -1,
1799         .pbuf_reg = AFE_DL8_CON0,
1800         .pbuf_mask = DL8_PBUF_SIZE_MASK,
1801         .pbuf_shift = DL8_PBUF_SIZE_SFT,
1802         .minlen_reg = AFE_DL8_CON0,
1803         .minlen_mask = DL8_MINLEN_MASK,
1804         .minlen_shift = DL8_MINLEN_SFT,
1805     },
1806     [MT8186_MEMIF_VUL12] = {
1807         .name = "VUL12",
1808         .id = MT8186_MEMIF_VUL12,
1809         .reg_ofs_base = AFE_VUL12_BASE,
1810         .reg_ofs_cur = AFE_VUL12_CUR,
1811         .reg_ofs_end = AFE_VUL12_END,
1812         .reg_ofs_base_msb = AFE_VUL12_BASE_MSB,
1813         .reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,
1814         .reg_ofs_end_msb = AFE_VUL12_END_MSB,
1815         .fs_reg = AFE_VUL12_CON0,
1816         .fs_shift = VUL12_MODE_SFT,
1817         .fs_maskbit = VUL12_MODE_MASK,
1818         .mono_reg = AFE_VUL12_CON0,
1819         .mono_shift = VUL12_MONO_SFT,
1820         .quad_ch_reg = AFE_VUL12_CON0,
1821         .quad_ch_mask = VUL12_4CH_EN_MASK,
1822         .quad_ch_shift = VUL12_4CH_EN_SFT,
1823         .enable_reg = AFE_DAC_CON0,
1824         .enable_shift = VUL12_ON_SFT,
1825         .hd_reg = AFE_VUL12_CON0,
1826         .hd_shift = VUL12_HD_MODE_SFT,
1827         .hd_align_reg = AFE_VUL12_CON0,
1828         .hd_align_mshift = VUL12_HALIGN_SFT,
1829         .agent_disable_reg = -1,
1830         .agent_disable_shift = -1,
1831         .msb_reg = -1,
1832         .msb_shift = -1,
1833     },
1834     [MT8186_MEMIF_VUL2] = {
1835         .name = "VUL2",
1836         .id = MT8186_MEMIF_VUL2,
1837         .reg_ofs_base = AFE_VUL2_BASE,
1838         .reg_ofs_cur = AFE_VUL2_CUR,
1839         .reg_ofs_end = AFE_VUL2_END,
1840         .reg_ofs_base_msb = AFE_VUL2_BASE_MSB,
1841         .reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,
1842         .reg_ofs_end_msb = AFE_VUL2_END_MSB,
1843         .fs_reg = AFE_VUL2_CON0,
1844         .fs_shift = VUL2_MODE_SFT,
1845         .fs_maskbit = VUL2_MODE_MASK,
1846         .mono_reg = AFE_VUL2_CON0,
1847         .mono_shift = VUL2_MONO_SFT,
1848         .enable_reg = AFE_DAC_CON0,
1849         .enable_shift = VUL2_ON_SFT,
1850         .hd_reg = AFE_VUL2_CON0,
1851         .hd_shift = VUL2_HD_MODE_SFT,
1852         .hd_align_reg = AFE_VUL2_CON0,
1853         .hd_align_mshift = VUL2_HALIGN_SFT,
1854         .agent_disable_reg = -1,
1855         .agent_disable_shift = -1,
1856         .msb_reg = -1,
1857         .msb_shift = -1,
1858     },
1859     [MT8186_MEMIF_AWB] = {
1860         .name = "AWB",
1861         .id = MT8186_MEMIF_AWB,
1862         .reg_ofs_base = AFE_AWB_BASE,
1863         .reg_ofs_cur = AFE_AWB_CUR,
1864         .reg_ofs_end = AFE_AWB_END,
1865         .reg_ofs_base_msb = AFE_AWB_BASE_MSB,
1866         .reg_ofs_cur_msb = AFE_AWB_CUR_MSB,
1867         .reg_ofs_end_msb = AFE_AWB_END_MSB,
1868         .fs_reg = AFE_AWB_CON0,
1869         .fs_shift = AWB_MODE_SFT,
1870         .fs_maskbit = AWB_MODE_MASK,
1871         .mono_reg = AFE_AWB_CON0,
1872         .mono_shift = AWB_MONO_SFT,
1873         .enable_reg = AFE_DAC_CON0,
1874         .enable_shift = AWB_ON_SFT,
1875         .hd_reg = AFE_AWB_CON0,
1876         .hd_shift = AWB_HD_MODE_SFT,
1877         .hd_align_reg = AFE_AWB_CON0,
1878         .hd_align_mshift = AWB_HALIGN_SFT,
1879         .agent_disable_reg = -1,
1880         .agent_disable_shift = -1,
1881         .msb_reg = -1,
1882         .msb_shift = -1,
1883     },
1884     [MT8186_MEMIF_AWB2] = {
1885         .name = "AWB2",
1886         .id = MT8186_MEMIF_AWB2,
1887         .reg_ofs_base = AFE_AWB2_BASE,
1888         .reg_ofs_cur = AFE_AWB2_CUR,
1889         .reg_ofs_end = AFE_AWB2_END,
1890         .reg_ofs_base_msb = AFE_AWB2_BASE_MSB,
1891         .reg_ofs_cur_msb = AFE_AWB2_CUR_MSB,
1892         .reg_ofs_end_msb = AFE_AWB2_END_MSB,
1893         .fs_reg = AFE_AWB2_CON0,
1894         .fs_shift = AWB2_MODE_SFT,
1895         .fs_maskbit = AWB2_MODE_MASK,
1896         .mono_reg = AFE_AWB2_CON0,
1897         .mono_shift = AWB2_MONO_SFT,
1898         .enable_reg = AFE_DAC_CON0,
1899         .enable_shift = AWB2_ON_SFT,
1900         .hd_reg = AFE_AWB2_CON0,
1901         .hd_shift = AWB2_HD_MODE_SFT,
1902         .hd_align_reg = AFE_AWB2_CON0,
1903         .hd_align_mshift = AWB2_HALIGN_SFT,
1904         .agent_disable_reg = -1,
1905         .agent_disable_shift = -1,
1906         .msb_reg = -1,
1907         .msb_shift = -1,
1908     },
1909     [MT8186_MEMIF_VUL3] = {
1910         .name = "VUL3",
1911         .id = MT8186_MEMIF_VUL3,
1912         .reg_ofs_base = AFE_VUL3_BASE,
1913         .reg_ofs_cur = AFE_VUL3_CUR,
1914         .reg_ofs_end = AFE_VUL3_END,
1915         .reg_ofs_base_msb = AFE_VUL3_BASE_MSB,
1916         .reg_ofs_cur_msb = AFE_VUL3_CUR_MSB,
1917         .reg_ofs_end_msb = AFE_VUL3_END_MSB,
1918         .fs_reg = AFE_VUL3_CON0,
1919         .fs_shift = VUL3_MODE_SFT,
1920         .fs_maskbit = VUL3_MODE_MASK,
1921         .mono_reg = AFE_VUL3_CON0,
1922         .mono_shift = VUL3_MONO_SFT,
1923         .enable_reg = AFE_DAC_CON0,
1924         .enable_shift = VUL3_ON_SFT,
1925         .hd_reg = AFE_VUL3_CON0,
1926         .hd_shift = VUL3_HD_MODE_SFT,
1927         .hd_align_reg = AFE_VUL3_CON0,
1928         .hd_align_mshift = VUL3_HALIGN_SFT,
1929         .agent_disable_reg = -1,
1930         .agent_disable_shift = -1,
1931         .msb_reg = -1,
1932         .msb_shift = -1,
1933     },
1934     [MT8186_MEMIF_VUL4] = {
1935         .name = "VUL4",
1936         .id = MT8186_MEMIF_VUL4,
1937         .reg_ofs_base = AFE_VUL4_BASE,
1938         .reg_ofs_cur = AFE_VUL4_CUR,
1939         .reg_ofs_end = AFE_VUL4_END,
1940         .reg_ofs_base_msb = AFE_VUL4_BASE_MSB,
1941         .reg_ofs_cur_msb = AFE_VUL4_CUR_MSB,
1942         .reg_ofs_end_msb = AFE_VUL4_END_MSB,
1943         .fs_reg = AFE_VUL4_CON0,
1944         .fs_shift = VUL4_MODE_SFT,
1945         .fs_maskbit = VUL4_MODE_MASK,
1946         .mono_reg = AFE_VUL4_CON0,
1947         .mono_shift = VUL4_MONO_SFT,
1948         .enable_reg = AFE_DAC_CON0,
1949         .enable_shift = VUL4_ON_SFT,
1950         .hd_reg = AFE_VUL4_CON0,
1951         .hd_shift = VUL4_HD_MODE_SFT,
1952         .hd_align_reg = AFE_VUL4_CON0,
1953         .hd_align_mshift = VUL4_HALIGN_SFT,
1954         .agent_disable_reg = -1,
1955         .agent_disable_shift = -1,
1956         .msb_reg = -1,
1957         .msb_shift = -1,
1958     },
1959     [MT8186_MEMIF_VUL5] = {
1960         .name = "VUL5",
1961         .id = MT8186_MEMIF_VUL5,
1962         .reg_ofs_base = AFE_VUL5_BASE,
1963         .reg_ofs_cur = AFE_VUL5_CUR,
1964         .reg_ofs_end = AFE_VUL5_END,
1965         .reg_ofs_base_msb = AFE_VUL5_BASE_MSB,
1966         .reg_ofs_cur_msb = AFE_VUL5_CUR_MSB,
1967         .reg_ofs_end_msb = AFE_VUL5_END_MSB,
1968         .fs_reg = AFE_VUL5_CON0,
1969         .fs_shift = VUL5_MODE_SFT,
1970         .fs_maskbit = VUL5_MODE_MASK,
1971         .mono_reg = AFE_VUL5_CON0,
1972         .mono_shift = VUL5_MONO_SFT,
1973         .enable_reg = AFE_DAC_CON0,
1974         .enable_shift = VUL5_ON_SFT,
1975         .hd_reg = AFE_VUL5_CON0,
1976         .hd_shift = VUL5_HD_MODE_SFT,
1977         .hd_align_reg = AFE_VUL5_CON0,
1978         .hd_align_mshift = VUL5_HALIGN_SFT,
1979         .agent_disable_reg = -1,
1980         .agent_disable_shift = -1,
1981         .msb_reg = -1,
1982         .msb_shift = -1,
1983     },
1984     [MT8186_MEMIF_VUL6] = {
1985         .name = "VUL6",
1986         .id = MT8186_MEMIF_VUL6,
1987         .reg_ofs_base = AFE_VUL6_BASE,
1988         .reg_ofs_cur = AFE_VUL6_CUR,
1989         .reg_ofs_end = AFE_VUL6_END,
1990         .reg_ofs_base_msb = AFE_VUL6_BASE_MSB,
1991         .reg_ofs_cur_msb = AFE_VUL6_CUR_MSB,
1992         .reg_ofs_end_msb = AFE_VUL6_END_MSB,
1993         .fs_reg = AFE_VUL6_CON0,
1994         .fs_shift = VUL6_MODE_SFT,
1995         .fs_maskbit = VUL6_MODE_MASK,
1996         .mono_reg = AFE_VUL6_CON0,
1997         .mono_shift = VUL6_MONO_SFT,
1998         .enable_reg = AFE_DAC_CON0,
1999         .enable_shift = VUL6_ON_SFT,
2000         .hd_reg = AFE_VUL6_CON0,
2001         .hd_shift = VUL6_HD_MODE_SFT,
2002         .hd_align_reg = AFE_VUL6_CON0,
2003         .hd_align_mshift = VUL6_HALIGN_SFT,
2004         .agent_disable_reg = -1,
2005         .agent_disable_shift = -1,
2006         .msb_reg = -1,
2007         .msb_shift = -1,
2008     },
2009 };
2010
2011 static const struct mtk_base_irq_data irq_data[MT8186_IRQ_NUM] = {
2012     [MT8186_IRQ_0] = {
2013         .id = MT8186_IRQ_0,
2014         .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
2015         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2016         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2017         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2018         .irq_fs_shift = IRQ0_MCU_MODE_SFT,
2019         .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
2020         .irq_en_reg = AFE_IRQ_MCU_CON0,
2021         .irq_en_shift = IRQ0_MCU_ON_SFT,
2022         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2023         .irq_clr_shift = IRQ0_MCU_CLR_SFT,
2024     },
2025     [MT8186_IRQ_1] = {
2026         .id = MT8186_IRQ_1,
2027         .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
2028         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2029         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2030         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2031         .irq_fs_shift = IRQ1_MCU_MODE_SFT,
2032         .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
2033         .irq_en_reg = AFE_IRQ_MCU_CON0,
2034         .irq_en_shift = IRQ1_MCU_ON_SFT,
2035         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2036         .irq_clr_shift = IRQ1_MCU_CLR_SFT,
2037     },
2038     [MT8186_IRQ_2] = {
2039         .id = MT8186_IRQ_2,
2040         .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
2041         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2042         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2043         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2044         .irq_fs_shift = IRQ2_MCU_MODE_SFT,
2045         .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
2046         .irq_en_reg = AFE_IRQ_MCU_CON0,
2047         .irq_en_shift = IRQ2_MCU_ON_SFT,
2048         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2049         .irq_clr_shift = IRQ2_MCU_CLR_SFT,
2050     },
2051     [MT8186_IRQ_3] = {
2052         .id = MT8186_IRQ_3,
2053         .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
2054         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2055         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2056         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2057         .irq_fs_shift = IRQ3_MCU_MODE_SFT,
2058         .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
2059         .irq_en_reg = AFE_IRQ_MCU_CON0,
2060         .irq_en_shift = IRQ3_MCU_ON_SFT,
2061         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2062         .irq_clr_shift = IRQ3_MCU_CLR_SFT,
2063     },
2064     [MT8186_IRQ_4] = {
2065         .id = MT8186_IRQ_4,
2066         .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
2067         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2068         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2069         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2070         .irq_fs_shift = IRQ4_MCU_MODE_SFT,
2071         .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
2072         .irq_en_reg = AFE_IRQ_MCU_CON0,
2073         .irq_en_shift = IRQ4_MCU_ON_SFT,
2074         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2075         .irq_clr_shift = IRQ4_MCU_CLR_SFT,
2076     },
2077     [MT8186_IRQ_5] = {
2078         .id = MT8186_IRQ_5,
2079         .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
2080         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2081         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2082         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2083         .irq_fs_shift = IRQ5_MCU_MODE_SFT,
2084         .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
2085         .irq_en_reg = AFE_IRQ_MCU_CON0,
2086         .irq_en_shift = IRQ5_MCU_ON_SFT,
2087         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2088         .irq_clr_shift = IRQ5_MCU_CLR_SFT,
2089     },
2090     [MT8186_IRQ_6] = {
2091         .id = MT8186_IRQ_6,
2092         .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
2093         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2094         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2095         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2096         .irq_fs_shift = IRQ6_MCU_MODE_SFT,
2097         .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
2098         .irq_en_reg = AFE_IRQ_MCU_CON0,
2099         .irq_en_shift = IRQ6_MCU_ON_SFT,
2100         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2101         .irq_clr_shift = IRQ6_MCU_CLR_SFT,
2102     },
2103     [MT8186_IRQ_7] = {
2104         .id = MT8186_IRQ_7,
2105         .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
2106         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2107         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2108         .irq_fs_reg = AFE_IRQ_MCU_CON1,
2109         .irq_fs_shift = IRQ7_MCU_MODE_SFT,
2110         .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
2111         .irq_en_reg = AFE_IRQ_MCU_CON0,
2112         .irq_en_shift = IRQ7_MCU_ON_SFT,
2113         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2114         .irq_clr_shift = IRQ7_MCU_CLR_SFT,
2115     },
2116     [MT8186_IRQ_8] = {
2117         .id = MT8186_IRQ_8,
2118         .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
2119         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2120         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2121         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2122         .irq_fs_shift = IRQ8_MCU_MODE_SFT,
2123         .irq_fs_maskbit = IRQ8_MCU_MODE_MASK,
2124         .irq_en_reg = AFE_IRQ_MCU_CON0,
2125         .irq_en_shift = IRQ8_MCU_ON_SFT,
2126         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2127         .irq_clr_shift = IRQ8_MCU_CLR_SFT,
2128     },
2129     [MT8186_IRQ_9] = {
2130         .id = MT8186_IRQ_9,
2131         .irq_cnt_reg = AFE_IRQ_MCU_CNT9,
2132         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2133         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2134         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2135         .irq_fs_shift = IRQ9_MCU_MODE_SFT,
2136         .irq_fs_maskbit = IRQ9_MCU_MODE_MASK,
2137         .irq_en_reg = AFE_IRQ_MCU_CON0,
2138         .irq_en_shift = IRQ9_MCU_ON_SFT,
2139         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2140         .irq_clr_shift = IRQ9_MCU_CLR_SFT,
2141     },
2142     [MT8186_IRQ_10] = {
2143         .id = MT8186_IRQ_10,
2144         .irq_cnt_reg = AFE_IRQ_MCU_CNT10,
2145         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2146         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2147         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2148         .irq_fs_shift = IRQ10_MCU_MODE_SFT,
2149         .irq_fs_maskbit = IRQ10_MCU_MODE_MASK,
2150         .irq_en_reg = AFE_IRQ_MCU_CON0,
2151         .irq_en_shift = IRQ10_MCU_ON_SFT,
2152         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2153         .irq_clr_shift = IRQ10_MCU_CLR_SFT,
2154     },
2155     [MT8186_IRQ_11] = {
2156         .id = MT8186_IRQ_11,
2157         .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
2158         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2159         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2160         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2161         .irq_fs_shift = IRQ11_MCU_MODE_SFT,
2162         .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
2163         .irq_en_reg = AFE_IRQ_MCU_CON0,
2164         .irq_en_shift = IRQ11_MCU_ON_SFT,
2165         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2166         .irq_clr_shift = IRQ11_MCU_CLR_SFT,
2167     },
2168     [MT8186_IRQ_12] = {
2169         .id = MT8186_IRQ_12,
2170         .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
2171         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2172         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2173         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2174         .irq_fs_shift = IRQ12_MCU_MODE_SFT,
2175         .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
2176         .irq_en_reg = AFE_IRQ_MCU_CON0,
2177         .irq_en_shift = IRQ12_MCU_ON_SFT,
2178         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2179         .irq_clr_shift = IRQ12_MCU_CLR_SFT,
2180     },
2181     [MT8186_IRQ_13] = {
2182         .id = MT8186_IRQ_13,
2183         .irq_cnt_reg = AFE_IRQ_MCU_CNT13,
2184         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2185         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2186         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2187         .irq_fs_shift = IRQ13_MCU_MODE_SFT,
2188         .irq_fs_maskbit = IRQ13_MCU_MODE_MASK,
2189         .irq_en_reg = AFE_IRQ_MCU_CON0,
2190         .irq_en_shift = IRQ13_MCU_ON_SFT,
2191         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2192         .irq_clr_shift = IRQ13_MCU_CLR_SFT,
2193     },
2194     [MT8186_IRQ_14] = {
2195         .id = MT8186_IRQ_14,
2196         .irq_cnt_reg = AFE_IRQ_MCU_CNT14,
2197         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2198         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2199         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2200         .irq_fs_shift = IRQ14_MCU_MODE_SFT,
2201         .irq_fs_maskbit = IRQ14_MCU_MODE_MASK,
2202         .irq_en_reg = AFE_IRQ_MCU_CON0,
2203         .irq_en_shift = IRQ14_MCU_ON_SFT,
2204         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2205         .irq_clr_shift = IRQ14_MCU_CLR_SFT,
2206     },
2207     [MT8186_IRQ_15] = {
2208         .id = MT8186_IRQ_15,
2209         .irq_cnt_reg = AFE_IRQ_MCU_CNT15,
2210         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2211         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2212         .irq_fs_reg = AFE_IRQ_MCU_CON2,
2213         .irq_fs_shift = IRQ15_MCU_MODE_SFT,
2214         .irq_fs_maskbit = IRQ15_MCU_MODE_MASK,
2215         .irq_en_reg = AFE_IRQ_MCU_CON0,
2216         .irq_en_shift = IRQ15_MCU_ON_SFT,
2217         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2218         .irq_clr_shift = IRQ15_MCU_CLR_SFT,
2219     },
2220     [MT8186_IRQ_16] = {
2221         .id = MT8186_IRQ_16,
2222         .irq_cnt_reg = AFE_IRQ_MCU_CNT16,
2223         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2224         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2225         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2226         .irq_fs_shift = IRQ16_MCU_MODE_SFT,
2227         .irq_fs_maskbit = IRQ16_MCU_MODE_MASK,
2228         .irq_en_reg = AFE_IRQ_MCU_CON0,
2229         .irq_en_shift = IRQ16_MCU_ON_SFT,
2230         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2231         .irq_clr_shift = IRQ16_MCU_CLR_SFT,
2232     },
2233     [MT8186_IRQ_17] = {
2234         .id = MT8186_IRQ_17,
2235         .irq_cnt_reg = AFE_IRQ_MCU_CNT17,
2236         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2237         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2238         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2239         .irq_fs_shift = IRQ17_MCU_MODE_SFT,
2240         .irq_fs_maskbit = IRQ17_MCU_MODE_MASK,
2241         .irq_en_reg = AFE_IRQ_MCU_CON0,
2242         .irq_en_shift = IRQ17_MCU_ON_SFT,
2243         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2244         .irq_clr_shift = IRQ17_MCU_CLR_SFT,
2245     },
2246     [MT8186_IRQ_18] = {
2247         .id = MT8186_IRQ_18,
2248         .irq_cnt_reg = AFE_IRQ_MCU_CNT18,
2249         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2250         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2251         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2252         .irq_fs_shift = IRQ18_MCU_MODE_SFT,
2253         .irq_fs_maskbit = IRQ18_MCU_MODE_MASK,
2254         .irq_en_reg = AFE_IRQ_MCU_CON0,
2255         .irq_en_shift = IRQ18_MCU_ON_SFT,
2256         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2257         .irq_clr_shift = IRQ18_MCU_CLR_SFT,
2258     },
2259     [MT8186_IRQ_19] = {
2260         .id = MT8186_IRQ_19,
2261         .irq_cnt_reg = AFE_IRQ_MCU_CNT19,
2262         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2263         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2264         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2265         .irq_fs_shift = IRQ19_MCU_MODE_SFT,
2266         .irq_fs_maskbit = IRQ19_MCU_MODE_MASK,
2267         .irq_en_reg = AFE_IRQ_MCU_CON0,
2268         .irq_en_shift = IRQ19_MCU_ON_SFT,
2269         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2270         .irq_clr_shift = IRQ19_MCU_CLR_SFT,
2271     },
2272     [MT8186_IRQ_20] = {
2273         .id = MT8186_IRQ_20,
2274         .irq_cnt_reg = AFE_IRQ_MCU_CNT20,
2275         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2276         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2277         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2278         .irq_fs_shift = IRQ20_MCU_MODE_SFT,
2279         .irq_fs_maskbit = IRQ20_MCU_MODE_MASK,
2280         .irq_en_reg = AFE_IRQ_MCU_CON0,
2281         .irq_en_shift = IRQ20_MCU_ON_SFT,
2282         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2283         .irq_clr_shift = IRQ20_MCU_CLR_SFT,
2284     },
2285     [MT8186_IRQ_21] = {
2286         .id = MT8186_IRQ_21,
2287         .irq_cnt_reg = AFE_IRQ_MCU_CNT21,
2288         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2289         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2290         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2291         .irq_fs_shift = IRQ21_MCU_MODE_SFT,
2292         .irq_fs_maskbit = IRQ21_MCU_MODE_MASK,
2293         .irq_en_reg = AFE_IRQ_MCU_CON0,
2294         .irq_en_shift = IRQ21_MCU_ON_SFT,
2295         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2296         .irq_clr_shift = IRQ21_MCU_CLR_SFT,
2297     },
2298     [MT8186_IRQ_22] = {
2299         .id = MT8186_IRQ_22,
2300         .irq_cnt_reg = AFE_IRQ_MCU_CNT22,
2301         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2302         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2303         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2304         .irq_fs_shift = IRQ22_MCU_MODE_SFT,
2305         .irq_fs_maskbit = IRQ22_MCU_MODE_MASK,
2306         .irq_en_reg = AFE_IRQ_MCU_CON0,
2307         .irq_en_shift = IRQ22_MCU_ON_SFT,
2308         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2309         .irq_clr_shift = IRQ22_MCU_CLR_SFT,
2310     },
2311     [MT8186_IRQ_23] = {
2312         .id = MT8186_IRQ_23,
2313         .irq_cnt_reg = AFE_IRQ_MCU_CNT23,
2314         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2315         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2316         .irq_fs_reg = AFE_IRQ_MCU_CON3,
2317         .irq_fs_shift = IRQ23_MCU_MODE_SFT,
2318         .irq_fs_maskbit = IRQ23_MCU_MODE_MASK,
2319         .irq_en_reg = AFE_IRQ_MCU_CON0,
2320         .irq_en_shift = IRQ23_MCU_ON_SFT,
2321         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2322         .irq_clr_shift = IRQ23_MCU_CLR_SFT,
2323     },
2324     [MT8186_IRQ_24] = {
2325         .id = MT8186_IRQ_24,
2326         .irq_cnt_reg = AFE_IRQ_MCU_CNT24,
2327         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2328         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2329         .irq_fs_reg = AFE_IRQ_MCU_CON4,
2330         .irq_fs_shift = IRQ24_MCU_MODE_SFT,
2331         .irq_fs_maskbit = IRQ24_MCU_MODE_MASK,
2332         .irq_en_reg = AFE_IRQ_MCU_CON0,
2333         .irq_en_shift = IRQ24_MCU_ON_SFT,
2334         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2335         .irq_clr_shift = IRQ24_MCU_CLR_SFT,
2336     },
2337     [MT8186_IRQ_25] = {
2338         .id = MT8186_IRQ_25,
2339         .irq_cnt_reg = AFE_IRQ_MCU_CNT25,
2340         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2341         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2342         .irq_fs_reg = AFE_IRQ_MCU_CON4,
2343         .irq_fs_shift = IRQ25_MCU_MODE_SFT,
2344         .irq_fs_maskbit = IRQ25_MCU_MODE_MASK,
2345         .irq_en_reg = AFE_IRQ_MCU_CON0,
2346         .irq_en_shift = IRQ25_MCU_ON_SFT,
2347         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2348         .irq_clr_shift = IRQ25_MCU_CLR_SFT,
2349     },
2350     [MT8186_IRQ_26] = {
2351         .id = MT8186_IRQ_26,
2352         .irq_cnt_reg = AFE_IRQ_MCU_CNT26,
2353         .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
2354         .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
2355         .irq_fs_reg = AFE_IRQ_MCU_CON4,
2356         .irq_fs_shift = IRQ26_MCU_MODE_SFT,
2357         .irq_fs_maskbit = IRQ26_MCU_MODE_MASK,
2358         .irq_en_reg = AFE_IRQ_MCU_CON0,
2359         .irq_en_shift = IRQ26_MCU_ON_SFT,
2360         .irq_clr_reg = AFE_IRQ_MCU_CLR,
2361         .irq_clr_shift = IRQ26_MCU_CLR_SFT,
2362     },
2363 };
2364
2365 static const int memif_irq_usage[MT8186_MEMIF_NUM] = {
2366     /* TODO: verify each memif & irq */
2367     [MT8186_MEMIF_DL1] = MT8186_IRQ_0,
2368     [MT8186_MEMIF_DL2] = MT8186_IRQ_1,
2369     [MT8186_MEMIF_DL3] = MT8186_IRQ_2,
2370     [MT8186_MEMIF_DL4] = MT8186_IRQ_3,
2371     [MT8186_MEMIF_DL5] = MT8186_IRQ_4,
2372     [MT8186_MEMIF_DL6] = MT8186_IRQ_5,
2373     [MT8186_MEMIF_DL7] = MT8186_IRQ_6,
2374     [MT8186_MEMIF_DL8] = MT8186_IRQ_7,
2375     [MT8186_MEMIF_DL12] = MT8186_IRQ_9,
2376     [MT8186_MEMIF_VUL12] = MT8186_IRQ_10,
2377     [MT8186_MEMIF_VUL2] = MT8186_IRQ_11,
2378     [MT8186_MEMIF_AWB] = MT8186_IRQ_12,
2379     [MT8186_MEMIF_AWB2] = MT8186_IRQ_13,
2380     [MT8186_MEMIF_VUL3] = MT8186_IRQ_14,
2381     [MT8186_MEMIF_VUL4] = MT8186_IRQ_15,
2382     [MT8186_MEMIF_VUL5] = MT8186_IRQ_16,
2383     [MT8186_MEMIF_VUL6] = MT8186_IRQ_17,
2384 };
2385
2386 static bool mt8186_is_volatile_reg(struct device *dev, unsigned int reg)
2387 {
2388     /* these auto-gen reg has read-only bit, so put it as volatile */
2389     /* volatile reg cannot be cached, so cannot be set when power off */
2390     switch (reg) {
2391     case AUDIO_TOP_CON0:    /* reg bit controlled by CCF */
2392     case AUDIO_TOP_CON1:    /* reg bit controlled by CCF */
2393     case AUDIO_TOP_CON2:
2394     case AUDIO_TOP_CON3:
2395     case AFE_DL1_CUR_MSB:
2396     case AFE_DL1_CUR:
2397     case AFE_DL1_END:
2398     case AFE_DL2_CUR_MSB:
2399     case AFE_DL2_CUR:
2400     case AFE_DL2_END:
2401     case AFE_DL3_CUR_MSB:
2402     case AFE_DL3_CUR:
2403     case AFE_DL3_END:
2404     case AFE_DL4_CUR_MSB:
2405     case AFE_DL4_CUR:
2406     case AFE_DL4_END:
2407     case AFE_DL12_CUR_MSB:
2408     case AFE_DL12_CUR:
2409     case AFE_DL12_END:
2410     case AFE_ADDA_SRC_DEBUG_MON0:
2411     case AFE_ADDA_SRC_DEBUG_MON1:
2412     case AFE_ADDA_UL_SRC_MON0:
2413     case AFE_ADDA_UL_SRC_MON1:
2414     case AFE_SECURE_CON0:
2415     case AFE_SRAM_BOUND:
2416     case AFE_SECURE_CON1:
2417     case AFE_VUL_CUR_MSB:
2418     case AFE_VUL_CUR:
2419     case AFE_VUL_END:
2420     case AFE_SIDETONE_MON:
2421     case AFE_SIDETONE_CON0:
2422     case AFE_SIDETONE_COEFF:
2423     case AFE_VUL2_CUR_MSB:
2424     case AFE_VUL2_CUR:
2425     case AFE_VUL2_END:
2426     case AFE_VUL3_CUR_MSB:
2427     case AFE_VUL3_CUR:
2428     case AFE_VUL3_END:
2429     case AFE_I2S_MON:
2430     case AFE_DAC_MON:
2431     case AFE_IRQ0_MCU_CNT_MON:
2432     case AFE_IRQ6_MCU_CNT_MON:
2433     case AFE_VUL4_CUR_MSB:
2434     case AFE_VUL4_CUR:
2435     case AFE_VUL4_END:
2436     case AFE_VUL12_CUR_MSB:
2437     case AFE_VUL12_CUR:
2438     case AFE_VUL12_END:
2439     case AFE_IRQ3_MCU_CNT_MON:
2440     case AFE_IRQ4_MCU_CNT_MON:
2441     case AFE_IRQ_MCU_STATUS:
2442     case AFE_IRQ_MCU_CLR:
2443     case AFE_IRQ_MCU_MON2:
2444     case AFE_IRQ1_MCU_CNT_MON:
2445     case AFE_IRQ2_MCU_CNT_MON:
2446     case AFE_IRQ5_MCU_CNT_MON:
2447     case AFE_IRQ7_MCU_CNT_MON:
2448     case AFE_IRQ_MCU_MISS_CLR:
2449     case AFE_GAIN1_CUR:
2450     case AFE_GAIN2_CUR:
2451     case AFE_SRAM_DELSEL_CON1:
2452     case PCM_INTF_CON2:
2453     case FPGA_CFG0:
2454     case FPGA_CFG1:
2455     case FPGA_CFG2:
2456     case FPGA_CFG3:
2457     case AUDIO_TOP_DBG_MON0:
2458     case AUDIO_TOP_DBG_MON1:
2459     case AFE_IRQ8_MCU_CNT_MON:
2460     case AFE_IRQ11_MCU_CNT_MON:
2461     case AFE_IRQ12_MCU_CNT_MON:
2462     case AFE_IRQ9_MCU_CNT_MON:
2463     case AFE_IRQ10_MCU_CNT_MON:
2464     case AFE_IRQ13_MCU_CNT_MON:
2465     case AFE_IRQ14_MCU_CNT_MON:
2466     case AFE_IRQ15_MCU_CNT_MON:
2467     case AFE_IRQ16_MCU_CNT_MON:
2468     case AFE_IRQ17_MCU_CNT_MON:
2469     case AFE_IRQ18_MCU_CNT_MON:
2470     case AFE_IRQ19_MCU_CNT_MON:
2471     case AFE_IRQ20_MCU_CNT_MON:
2472     case AFE_IRQ21_MCU_CNT_MON:
2473     case AFE_IRQ22_MCU_CNT_MON:
2474     case AFE_IRQ23_MCU_CNT_MON:
2475     case AFE_IRQ24_MCU_CNT_MON:
2476     case AFE_IRQ25_MCU_CNT_MON:
2477     case AFE_IRQ26_MCU_CNT_MON:
2478     case AFE_IRQ31_MCU_CNT_MON:
2479     case AFE_CBIP_MON0:
2480     case AFE_CBIP_SLV_MUX_MON0:
2481     case AFE_CBIP_SLV_DECODER_MON0:
2482     case AFE_ADDA6_MTKAIF_MON0:
2483     case AFE_ADDA6_MTKAIF_MON1:
2484     case AFE_AWB_CUR_MSB:
2485     case AFE_AWB_CUR:
2486     case AFE_AWB_END:
2487     case AFE_AWB2_CUR_MSB:
2488     case AFE_AWB2_CUR:
2489     case AFE_AWB2_END:
2490     case AFE_DAI_CUR_MSB:
2491     case AFE_DAI_CUR:
2492     case AFE_DAI_END:
2493     case AFE_DAI2_CUR_MSB:
2494     case AFE_DAI2_CUR:
2495     case AFE_DAI2_END:
2496     case AFE_ADDA6_SRC_DEBUG_MON0:
2497     case AFE_ADD6A_UL_SRC_MON0:
2498     case AFE_ADDA6_UL_SRC_MON1:
2499     case AFE_MOD_DAI_CUR_MSB:
2500     case AFE_MOD_DAI_CUR:
2501     case AFE_MOD_DAI_END:
2502     case AFE_AWB_RCH_MON:
2503     case AFE_AWB_LCH_MON:
2504     case AFE_VUL_RCH_MON:
2505     case AFE_VUL_LCH_MON:
2506     case AFE_VUL12_RCH_MON:
2507     case AFE_VUL12_LCH_MON:
2508     case AFE_VUL2_RCH_MON:
2509     case AFE_VUL2_LCH_MON:
2510     case AFE_DAI_DATA_MON:
2511     case AFE_MOD_DAI_DATA_MON:
2512     case AFE_DAI2_DATA_MON:
2513     case AFE_AWB2_RCH_MON:
2514     case AFE_AWB2_LCH_MON:
2515     case AFE_VUL3_RCH_MON:
2516     case AFE_VUL3_LCH_MON:
2517     case AFE_VUL4_RCH_MON:
2518     case AFE_VUL4_LCH_MON:
2519     case AFE_VUL5_RCH_MON:
2520     case AFE_VUL5_LCH_MON:
2521     case AFE_VUL6_RCH_MON:
2522     case AFE_VUL6_LCH_MON:
2523     case AFE_DL1_RCH_MON:
2524     case AFE_DL1_LCH_MON:
2525     case AFE_DL2_RCH_MON:
2526     case AFE_DL2_LCH_MON:
2527     case AFE_DL12_RCH1_MON:
2528     case AFE_DL12_LCH1_MON:
2529     case AFE_DL12_RCH2_MON:
2530     case AFE_DL12_LCH2_MON:
2531     case AFE_DL3_RCH_MON:
2532     case AFE_DL3_LCH_MON:
2533     case AFE_DL4_RCH_MON:
2534     case AFE_DL4_LCH_MON:
2535     case AFE_DL5_RCH_MON:
2536     case AFE_DL5_LCH_MON:
2537     case AFE_DL6_RCH_MON:
2538     case AFE_DL6_LCH_MON:
2539     case AFE_DL7_RCH_MON:
2540     case AFE_DL7_LCH_MON:
2541     case AFE_DL8_RCH_MON:
2542     case AFE_DL8_LCH_MON:
2543     case AFE_VUL5_CUR_MSB:
2544     case AFE_VUL5_CUR:
2545     case AFE_VUL5_END:
2546     case AFE_VUL6_CUR_MSB:
2547     case AFE_VUL6_CUR:
2548     case AFE_VUL6_END:
2549     case AFE_ADDA_DL_SDM_FIFO_MON:
2550     case AFE_ADDA_DL_SRC_LCH_MON:
2551     case AFE_ADDA_DL_SRC_RCH_MON:
2552     case AFE_ADDA_DL_SDM_OUT_MON:
2553     case AFE_CONNSYS_I2S_MON:
2554     case AFE_ASRC_2CH_CON0:
2555     case AFE_ASRC_2CH_CON2:
2556     case AFE_ASRC_2CH_CON3:
2557     case AFE_ASRC_2CH_CON4:
2558     case AFE_ASRC_2CH_CON5:
2559     case AFE_ASRC_2CH_CON7:
2560     case AFE_ASRC_2CH_CON8:
2561     case AFE_ASRC_2CH_CON12:
2562     case AFE_ASRC_2CH_CON13:
2563     case AFE_ADDA_MTKAIF_MON0:
2564     case AFE_ADDA_MTKAIF_MON1:
2565     case AFE_AUD_PAD_TOP:
2566     case AFE_DL_NLE_R_MON0:
2567     case AFE_DL_NLE_R_MON1:
2568     case AFE_DL_NLE_R_MON2:
2569     case AFE_DL_NLE_L_MON0:
2570     case AFE_DL_NLE_L_MON1:
2571     case AFE_DL_NLE_L_MON2:
2572     case AFE_GENERAL1_ASRC_2CH_CON0:
2573     case AFE_GENERAL1_ASRC_2CH_CON2:
2574     case AFE_GENERAL1_ASRC_2CH_CON3:
2575     case AFE_GENERAL1_ASRC_2CH_CON4:
2576     case AFE_GENERAL1_ASRC_2CH_CON5:
2577     case AFE_GENERAL1_ASRC_2CH_CON7:
2578     case AFE_GENERAL1_ASRC_2CH_CON8:
2579     case AFE_GENERAL1_ASRC_2CH_CON12:
2580     case AFE_GENERAL1_ASRC_2CH_CON13:
2581     case AFE_GENERAL2_ASRC_2CH_CON0:
2582     case AFE_GENERAL2_ASRC_2CH_CON2:
2583     case AFE_GENERAL2_ASRC_2CH_CON3:
2584     case AFE_GENERAL2_ASRC_2CH_CON4:
2585     case AFE_GENERAL2_ASRC_2CH_CON5:
2586     case AFE_GENERAL2_ASRC_2CH_CON7:
2587     case AFE_GENERAL2_ASRC_2CH_CON8:
2588     case AFE_GENERAL2_ASRC_2CH_CON12:
2589     case AFE_GENERAL2_ASRC_2CH_CON13:
2590     case AFE_DL5_CUR_MSB:
2591     case AFE_DL5_CUR:
2592     case AFE_DL5_END:
2593     case AFE_DL6_CUR_MSB:
2594     case AFE_DL6_CUR:
2595     case AFE_DL6_END:
2596     case AFE_DL7_CUR_MSB:
2597     case AFE_DL7_CUR:
2598     case AFE_DL7_END:
2599     case AFE_DL8_CUR_MSB:
2600     case AFE_DL8_CUR:
2601     case AFE_DL8_END:
2602     case AFE_PROT_SIDEBAND_MON:
2603     case AFE_DOMAIN_SIDEBAND0_MON:
2604     case AFE_DOMAIN_SIDEBAND1_MON:
2605     case AFE_DOMAIN_SIDEBAND2_MON:
2606     case AFE_DOMAIN_SIDEBAND3_MON:
2607     case AFE_APLL1_TUNER_CFG:   /* [20:31] is monitor */
2608     case AFE_APLL2_TUNER_CFG:   /* [20:31] is monitor */
2609         return true;
2610     default:
2611         return false;
2612     };
2613 }
2614
2615 static const struct regmap_config mt8186_afe_regmap_config = {
2616     .reg_bits = 32,
2617     .reg_stride = 4,
2618     .val_bits = 32,
2619
2620     .volatile_reg = mt8186_is_volatile_reg,
2621
2622     .max_register = AFE_MAX_REGISTER,
2623     .num_reg_defaults_raw = AFE_MAX_REGISTER,
2624
2625     .cache_type = REGCACHE_FLAT,
2626 };
2627
2628 static irqreturn_t mt8186_afe_irq_handler(int irq_id, void *dev)
2629 {
2630     struct mtk_base_afe *afe = dev;
2631     struct mtk_base_afe_irq *irq;
2632     unsigned int status;
2633     unsigned int status_mcu;
2634     unsigned int mcu_en;
2635     int ret;
2636     int i;
2637
2638     /* get irq that is sent to MCU */
2639     ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
2640     if (ret) {
2641         dev_err(afe->dev, "%s, get irq direction fail, ret %d", __func__, ret);
2642         return ret;
2643     }
2644
2645     ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
2646     /* only care IRQ which is sent to MCU */
2647     status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
2648
2649     if (ret || status_mcu == 0) {
2650         dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
2651             __func__, ret, status, mcu_en);
2652
2653         goto err_irq;
2654     }
2655
2656     for (i = 0; i < MT8186_MEMIF_NUM; i++) {
2657         struct mtk_base_afe_memif *memif = &afe->memif[i];
2658
2659         if (!memif->substream)
2660             continue;
2661
2662         if (memif->irq_usage < 0)
2663             continue;
2664
2665         irq = &afe->irqs[memif->irq_usage];
2666
2667         if (status_mcu & (1 << irq->irq_data->irq_en_shift))
2668             snd_pcm_period_elapsed(memif->substream);
2669     }
2670
2671 err_irq:
2672     /* clear irq */
2673     regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
2674
2675     return IRQ_HANDLED;
2676 }
2677
2678 static int mt8186_afe_runtime_suspend(struct device *dev)
2679 {
2680     struct mtk_base_afe *afe = dev_get_drvdata(dev);
2681     struct mt8186_afe_private *afe_priv = afe->platform_priv;
2682     unsigned int value = 0;
2683     int ret;
2684
2685     if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
2686         goto skip_regmap;
2687
2688     /* disable AFE */
2689     regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
2690
2691     ret = regmap_read_poll_timeout(afe->regmap,
2692                        AFE_DAC_MON,
2693                        value,
2694                        (value & AFE_ON_RETM_MASK_SFT) == 0,
2695                        20,
2696                        1 * 1000 * 1000);
2697     if (ret) {
2698         dev_err(afe->dev, "%s(), ret %d\n", __func__, ret);
2699         return ret;
2700     }
2701
2702     /* make sure all irq status are cleared */
2703     regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
2704     regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
2705
2706     /* reset sgen */
2707     regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0);
2708     regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
2709                INNER_LOOP_BACK_MODE_MASK_SFT,
2710                0x3f << INNER_LOOP_BACK_MODE_SFT);
2711
2712     /* cache only */
2713     regcache_cache_only(afe->regmap, true);
2714     regcache_mark_dirty(afe->regmap);
2715
2716 skip_regmap:
2717     mt8186_afe_disable_cgs(afe);
2718     mt8186_afe_disable_clock(afe);
2719
2720     return 0;
2721 }
2722
2723 static int mt8186_afe_runtime_resume(struct device *dev)
2724 {
2725     struct mtk_base_afe *afe = dev_get_drvdata(dev);
2726     struct mt8186_afe_private *afe_priv = afe->platform_priv;
2727     int ret;
2728
2729     ret = mt8186_afe_enable_clock(afe);
2730     if (ret)
2731         return ret;
2732
2733     ret = mt8186_afe_enable_cgs(afe);
2734     if (ret)
2735         return ret;
2736
2737     if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
2738         goto skip_regmap;
2739
2740     regcache_cache_only(afe->regmap, false);
2741     regcache_sync(afe->regmap);
2742
2743     /* enable audio sys DCM for power saving */
2744     regmap_update_bits(afe_priv->infracfg, PERI_BUS_DCM_CTRL, BIT(29), BIT(29));
2745     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, BIT(29), BIT(29));
2746
2747     /* force cpu use 8_24 format when writing 32bit data */
2748     regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, CPU_HD_ALIGN_MASK_SFT, 0);
2749
2750     /* set all output port to 24bit */
2751     regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
2752     regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
2753
2754     /* enable AFE */
2755     regmap_update_bits(afe->regmap, AFE_DAC_CON0, AUDIO_AFE_ON_MASK_SFT, BIT(0));
2756
2757 skip_regmap:
2758     return 0;
2759 }
2760
2761 static int mt8186_afe_component_probe(struct snd_soc_component *component)
2762 {
2763     mtk_afe_add_sub_dai_control(component);
2764     mt8186_add_misc_control(component);
2765
2766     return 0;
2767 }
2768
2769 static const struct snd_soc_component_driver mt8186_afe_component = {
2770     .name = AFE_PCM_NAME,
2771     .pcm_construct = mtk_afe_pcm_new,
2772     .pointer = mtk_afe_pcm_pointer,
2773     .probe = mt8186_afe_component_probe,
2774 };
2775
2776 static int mt8186_dai_memif_register(struct mtk_base_afe *afe)
2777 {
2778     struct mtk_base_afe_dai *dai;
2779
2780     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2781     if (!dai)
2782         return -ENOMEM;
2783
2784     list_add(&dai->list, &afe->sub_dais);
2785
2786     dai->dai_drivers = mt8186_memif_dai_driver;
2787     dai->num_dai_drivers = ARRAY_SIZE(mt8186_memif_dai_driver);
2788
2789     dai->controls = mt8186_pcm_kcontrols;
2790     dai->num_controls = ARRAY_SIZE(mt8186_pcm_kcontrols);
2791     dai->dapm_widgets = mt8186_memif_widgets;
2792     dai->num_dapm_widgets = ARRAY_SIZE(mt8186_memif_widgets);
2793     dai->dapm_routes = mt8186_memif_routes;
2794     dai->num_dapm_routes = ARRAY_SIZE(mt8186_memif_routes);
2795     return 0;
2796 }
2797
2798 typedef int (*dai_register_cb)(struct mtk_base_afe *);
2799 static const dai_register_cb dai_register_cbs[] = {
2800     mt8186_dai_adda_register,
2801     mt8186_dai_i2s_register,
2802     mt8186_dai_tdm_register,
2803     mt8186_dai_hw_gain_register,
2804     mt8186_dai_src_register,
2805     mt8186_dai_pcm_register,
2806     mt8186_dai_hostless_register,
2807     mt8186_dai_memif_register,
2808 };
2809
2810 static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev)
2811 {
2812     struct mtk_base_afe *afe;
2813     struct mt8186_afe_private *afe_priv;
2814     struct resource *res;
2815     struct reset_control *rstc;
2816     struct device *dev = &pdev->dev;
2817     int i, ret, irq_id;
2818
2819     ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
2820     if (ret)
2821         return ret;
2822
2823     afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
2824     if (!afe)
2825         return -ENOMEM;
2826     platform_set_drvdata(pdev, afe);
2827
2828     afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL);
2829     if (!afe->platform_priv)
2830         return -ENOMEM;
2831
2832     afe_priv = afe->platform_priv;
2833     afe->dev = &pdev->dev;
2834
2835     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2836     afe->base_addr = devm_ioremap_resource(dev, res);
2837     if (IS_ERR(afe->base_addr))
2838         return PTR_ERR(afe->base_addr);
2839
2840     /* init audio related clock */
2841     ret = mt8186_init_clock(afe);
2842     if (ret) {
2843         dev_err(dev, "init clock error, ret %d\n", ret);
2844         return ret;
2845     }
2846
2847     ret = devm_add_action_or_reset(dev, mt8186_deinit_clock, (void *)afe);
2848     if (ret)
2849         return ret;
2850
2851     /* init memif */
2852     afe->memif_32bit_supported = 0;
2853     afe->memif_size = MT8186_MEMIF_NUM;
2854     afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), GFP_KERNEL);
2855     if (!afe->memif)
2856         return -ENOMEM;
2857
2858     for (i = 0; i < afe->memif_size; i++) {
2859         afe->memif[i].data = &memif_data[i];
2860         afe->memif[i].irq_usage = memif_irq_usage[i];
2861         afe->memif[i].const_irq = 1;
2862     }
2863
2864     mutex_init(&afe->irq_alloc_lock);   /* needed when dynamic irq */
2865
2866     /* init irq */
2867     afe->irqs_size = MT8186_IRQ_NUM;
2868     afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
2869                  GFP_KERNEL);
2870
2871     if (!afe->irqs)
2872         return -ENOMEM;
2873
2874     for (i = 0; i < afe->irqs_size; i++)
2875         afe->irqs[i].irq_data = &irq_data[i];
2876
2877     /* request irq */
2878     irq_id = platform_get_irq(pdev, 0);
2879     if (irq_id <= 0)
2880         return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO,
2881                      "no irq found");
2882
2883     ret = devm_request_irq(dev, irq_id, mt8186_afe_irq_handler,
2884                    IRQF_TRIGGER_NONE,
2885                    "Afe_ISR_Handle", (void *)afe);
2886     if (ret)
2887         return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");
2888
2889     ret = enable_irq_wake(irq_id);
2890     if (ret < 0)
2891         return dev_err_probe(dev, ret, "enable_irq_wake %d\n", irq_id);
2892
2893     /* init sub_dais */
2894     INIT_LIST_HEAD(&afe->sub_dais);
2895
2896     for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
2897         ret = dai_register_cbs[i](afe);
2898         if (ret)
2899             return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
2900     }
2901
2902     /* init dai_driver and component_driver */
2903     ret = mtk_afe_combine_sub_dai(afe);
2904     if (ret)
2905         return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
2906
2907     /* reset controller to reset audio regs before regmap cache */
2908     rstc = devm_reset_control_get_exclusive(dev, "audiosys");
2909     if (IS_ERR(rstc))
2910         return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n");
2911
2912     ret = reset_control_reset(rstc);
2913     if (ret)
2914         return dev_err_probe(dev, ret, "failed to trigger audio reset\n");
2915
2916     /* enable clock for regcache get default value from hw */
2917     afe_priv->pm_runtime_bypass_reg_ctl = true;
2918
2919     ret = devm_pm_runtime_enable(dev);
2920     if (ret)
2921         return ret;
2922
2923     ret = pm_runtime_resume_and_get(dev);
2924     if (ret)
2925         return dev_err_probe(dev, ret, "failed to resume device\n");
2926
2927     afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,
2928                         &mt8186_afe_regmap_config);
2929     if (IS_ERR(afe->regmap)) {
2930         ret = PTR_ERR(afe->regmap);
2931         goto err_pm_disable;
2932     }
2933
2934     /* others */
2935     afe->mtk_afe_hardware = &mt8186_afe_hardware;
2936     afe->memif_fs = mt8186_memif_fs;
2937     afe->irq_fs = mt8186_irq_fs;
2938     afe->get_dai_fs = mt8186_get_dai_fs;
2939     afe->get_memif_pbuf_size = mt8186_get_memif_pbuf_size;
2940
2941     afe->runtime_resume = mt8186_afe_runtime_resume;
2942     afe->runtime_suspend = mt8186_afe_runtime_suspend;
2943
2944     /* register platform */
2945     dev_dbg(dev, "%s(), devm_snd_soc_register_component\n", __func__);
2946
2947     ret = devm_snd_soc_register_component(dev,
2948                           &mt8186_afe_component,
2949                           afe->dai_drivers,
2950                           afe->num_dai_drivers);
2951     if (ret) {
2952         dev_err(dev, "err_dai_component\n");
2953         goto err_pm_disable;
2954     }
2955
2956     ret = pm_runtime_put_sync(dev);
2957     if (ret) {
2958         pm_runtime_get_noresume(dev);
2959         dev_err(dev, "failed to suspend device: %d\n", ret);
2960         goto err_pm_disable;
2961     }
2962     afe_priv->pm_runtime_bypass_reg_ctl = false;
2963
2964     regcache_cache_only(afe->regmap, true);
2965     regcache_mark_dirty(afe->regmap);
2966
2967     return 0;
2968
2969 err_pm_disable:
2970     pm_runtime_put_noidle(dev);
2971     pm_runtime_set_suspended(dev);
2972
2973     return ret;
2974 }
2975
2976 static const struct of_device_id mt8186_afe_pcm_dt_match[] = {
2977     { .compatible = "mediatek,mt8186-sound", },
2978     {},
2979 };
2980 MODULE_DEVICE_TABLE(of, mt8186_afe_pcm_dt_match);
2981
2982 static const struct dev_pm_ops mt8186_afe_pm_ops = {
2983     SET_RUNTIME_PM_OPS(mt8186_afe_runtime_suspend,
2984                mt8186_afe_runtime_resume, NULL)
2985 };
2986
2987 static struct platform_driver mt8186_afe_pcm_driver = {
2988     .driver = {
2989            .name = "mt8186-audio",
2990            .of_match_table = mt8186_afe_pcm_dt_match,
2991            .pm = &mt8186_afe_pm_ops,
2992     },
2993     .probe = mt8186_afe_pcm_dev_probe,
2994 };
2995
2996 module_platform_driver(mt8186_afe_pcm_driver);
2997
2998 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8186");
2999 MODULE_AUTHOR("Jiaxin Yu <jiaxin.yu@mediatek.com>");
3000 MODULE_LICENSE("GPL v2");