mediatek/mt8186/mt8186-afe-common.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * mt8186-afe-common.h  --  Mediatek 8186 audio driver definitions
0004  *
0005  * Copyright (c) 2022 MediaTek Inc.
0006  * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007  */
0008
0009 #ifndef _MT_8186_AFE_COMMON_H_
0010 #define _MT_8186_AFE_COMMON_H_
0011 #include <sound/soc.h>
0012 #include <linux/list.h>
0013 #include <linux/regmap.h>
0014 #include "mt8186-reg.h"
0015 #include "../common/mtk-base-afe.h"
0016
0017 enum {
0018     MT8186_MEMIF_DL1,
0019     MT8186_MEMIF_DL12,
0020     MT8186_MEMIF_DL2,
0021     MT8186_MEMIF_DL3,
0022     MT8186_MEMIF_DL4,
0023     MT8186_MEMIF_DL5,
0024     MT8186_MEMIF_DL6,
0025     MT8186_MEMIF_DL7,
0026     MT8186_MEMIF_DL8,
0027     MT8186_MEMIF_VUL12,
0028     MT8186_MEMIF_VUL2,
0029     MT8186_MEMIF_VUL3,
0030     MT8186_MEMIF_VUL4,
0031     MT8186_MEMIF_VUL5,
0032     MT8186_MEMIF_VUL6,
0033     MT8186_MEMIF_AWB,
0034     MT8186_MEMIF_AWB2,
0035     MT8186_MEMIF_NUM,
0036     MT8186_DAI_ADDA = MT8186_MEMIF_NUM,
0037     MT8186_DAI_AP_DMIC,
0038     MT8186_DAI_CONNSYS_I2S,
0039     MT8186_DAI_I2S_0,
0040     MT8186_DAI_I2S_1,
0041     MT8186_DAI_I2S_2,
0042     MT8186_DAI_I2S_3,
0043     MT8186_DAI_HW_GAIN_1,
0044     MT8186_DAI_HW_GAIN_2,
0045     MT8186_DAI_SRC_1,
0046     MT8186_DAI_SRC_2,
0047     MT8186_DAI_PCM,
0048     MT8186_DAI_TDM_IN,
0049     MT8186_DAI_HOSTLESS_LPBK,
0050     MT8186_DAI_HOSTLESS_FM,
0051     MT8186_DAI_HOSTLESS_HW_GAIN_AAUDIO,
0052     MT8186_DAI_HOSTLESS_SRC_AAUDIO,
0053     MT8186_DAI_HOSTLESS_SRC_1,
0054     MT8186_DAI_HOSTLESS_SRC_BARGEIN,
0055     MT8186_DAI_HOSTLESS_UL1,
0056     MT8186_DAI_HOSTLESS_UL2,
0057     MT8186_DAI_HOSTLESS_UL3,
0058     MT8186_DAI_HOSTLESS_UL5,
0059     MT8186_DAI_HOSTLESS_UL6,
0060     MT8186_DAI_NUM,
0061 };
0062
0063 #define MT8186_RECORD_MEMIF MT8186_MEMIF_VUL12
0064 #define MT8186_ECHO_REF_MEMIF MT8186_MEMIF_AWB
0065 #define MT8186_PRIMARY_MEMIF MT8186_MEMIF_DL1
0066 #define MT8186_FAST_MEMIF MT8186_MEMIF_DL2
0067 #define MT8186_DEEP_MEMIF MT8186_MEMIF_DL3
0068 #define MT8186_VOIP_MEMIF MT8186_MEMIF_DL12
0069 #define MT8186_MMAP_DL_MEMIF MT8186_MEMIF_DL5
0070 #define MT8186_MMAP_UL_MEMIF MT8186_MEMIF_VUL5
0071 #define MT8186_BARGEIN_MEMIF MT8186_MEMIF_AWB
0072
0073 enum {
0074     MT8186_IRQ_0,
0075     MT8186_IRQ_1,
0076     MT8186_IRQ_2,
0077     MT8186_IRQ_3,
0078     MT8186_IRQ_4,
0079     MT8186_IRQ_5,
0080     MT8186_IRQ_6,
0081     MT8186_IRQ_7,
0082     MT8186_IRQ_8,
0083     MT8186_IRQ_9,
0084     MT8186_IRQ_10,
0085     MT8186_IRQ_11,
0086     MT8186_IRQ_12,
0087     MT8186_IRQ_13,
0088     MT8186_IRQ_14,
0089     MT8186_IRQ_15,
0090     MT8186_IRQ_16,
0091     MT8186_IRQ_17,
0092     MT8186_IRQ_18,
0093     MT8186_IRQ_19,
0094     MT8186_IRQ_20,
0095     MT8186_IRQ_21,
0096     MT8186_IRQ_22,
0097     MT8186_IRQ_23,
0098     MT8186_IRQ_24,
0099     MT8186_IRQ_25,
0100     MT8186_IRQ_26,
0101     MT8186_IRQ_NUM,
0102 };
0103
0104 enum {
0105     MT8186_AFE_IRQ_DIR_MCU = 0,
0106     MT8186_AFE_IRQ_DIR_DSP,
0107     MT8186_AFE_IRQ_DIR_BOTH,
0108 };
0109
0110 enum {
0111     MTKAIF_PROTOCOL_1 = 0,
0112     MTKAIF_PROTOCOL_2,
0113     MTKAIF_PROTOCOL_2_CLK_P2,
0114 };
0115
0116 enum {
0117     MTK_AFE_ADDA_DL_GAIN_MUTE = 0,
0118     MTK_AFE_ADDA_DL_GAIN_NORMAL = 0xf74f,
0119     /* SA suggest apply -0.3db to audio/speech path */
0120 };
0121
0122 #define MTK_SPK_I2S_0_STR "MTK_SPK_I2S_0"
0123 #define MTK_SPK_I2S_1_STR "MTK_SPK_I2S_1"
0124 #define MTK_SPK_I2S_2_STR "MTK_SPK_I2S_2"
0125 #define MTK_SPK_I2S_3_STR "MTK_SPK_I2S_3"
0126
0127 /* MCLK */
0128 enum {
0129     MT8186_I2S0_MCK = 0,
0130     MT8186_I2S1_MCK,
0131     MT8186_I2S2_MCK,
0132     MT8186_I2S4_MCK,
0133     MT8186_TDM_MCK,
0134     MT8186_MCK_NUM,
0135 };
0136
0137 struct snd_pcm_substream;
0138 struct mtk_base_irq_data;
0139 struct clk;
0140
0141 struct mt8186_afe_private {
0142     struct clk **clk;
0143     struct clk_lookup **lookup;
0144     struct regmap *topckgen;
0145     struct regmap *apmixedsys;
0146     struct regmap *infracfg;
0147     int irq_cnt[MT8186_MEMIF_NUM];
0148     int stf_positive_gain_db;
0149     int pm_runtime_bypass_reg_ctl;
0150     int sgen_mode;
0151     int sgen_rate;
0152     int sgen_amplitude;
0153
0154     /* xrun assert */
0155     int xrun_assert[MT8186_MEMIF_NUM];
0156
0157     /* dai */
0158     bool dai_on[MT8186_DAI_NUM];
0159     void *dai_priv[MT8186_DAI_NUM];
0160
0161     /* adda */
0162     bool mtkaif_calibration_ok;
0163     int mtkaif_protocol;
0164     int mtkaif_chosen_phase[4];
0165     int mtkaif_phase_cycle[4];
0166     int mtkaif_calibration_num_phase;
0167     int mtkaif_dmic;
0168     int mtkaif_looback0;
0169     int mtkaif_looback1;
0170
0171     /* mck */
0172     int mck_rate[MT8186_MCK_NUM];
0173 };
0174
0175 int mt8186_dai_adda_register(struct mtk_base_afe *afe);
0176 int mt8186_dai_i2s_register(struct mtk_base_afe *afe);
0177 int mt8186_dai_tdm_register(struct mtk_base_afe *afe);
0178 int mt8186_dai_hw_gain_register(struct mtk_base_afe *afe);
0179 int mt8186_dai_src_register(struct mtk_base_afe *afe);
0180 int mt8186_dai_pcm_register(struct mtk_base_afe *afe);
0181 int mt8186_dai_hostless_register(struct mtk_base_afe *afe);
0182
0183 int mt8186_add_misc_control(struct snd_soc_component *component);
0184
0185 unsigned int mt8186_general_rate_transform(struct device *dev,
0186                        unsigned int rate);
0187 unsigned int mt8186_rate_transform(struct device *dev,
0188                    unsigned int rate, int aud_blk);
0189 unsigned int mt8186_tdm_relatch_rate_transform(struct device *dev,
0190                            unsigned int rate);
0191
0192 int mt8186_dai_set_priv(struct mtk_base_afe *afe, int id,
0193             int priv_size, const void *priv_data);
0194
0195 #endif