mediatek/mt8186/mt8186-afe-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * mt8186-afe-clk.h  --  Mediatek 8186 afe clock ctrl definition
0004  *
0005  * Copyright (c) 2022 MediaTek Inc.
0006  * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007  */
0008
0009 #ifndef _MT8186_AFE_CLOCK_CTRL_H_
0010 #define _MT8186_AFE_CLOCK_CTRL_H_
0011
0012 #define PERI_BUS_DCM_CTRL   0x74
0013
0014 /* APLL */
0015 #define APLL1_W_NAME "APLL1"
0016 #define APLL2_W_NAME "APLL2"
0017 enum {
0018     MT8186_APLL1 = 0,
0019     MT8186_APLL2,
0020 };
0021
0022 enum {
0023     CLK_AFE = 0,
0024     CLK_DAC,
0025     CLK_DAC_PREDIS,
0026     CLK_ADC,
0027     CLK_TML,
0028     CLK_APLL22M,
0029     CLK_APLL24M,
0030     CLK_APLL1_TUNER,
0031     CLK_APLL2_TUNER,
0032     CLK_TDM,
0033     CLK_NLE,
0034     CLK_DAC_HIRES,
0035     CLK_ADC_HIRES,
0036     CLK_I2S1_BCLK,
0037     CLK_I2S2_BCLK,
0038     CLK_I2S3_BCLK,
0039     CLK_I2S4_BCLK,
0040     CLK_CONNSYS_I2S_ASRC,
0041     CLK_GENERAL1_ASRC,
0042     CLK_GENERAL2_ASRC,
0043     CLK_ADC_HIRES_TML,
0044     CLK_ADDA6_ADC,
0045     CLK_ADDA6_ADC_HIRES,
0046     CLK_3RD_DAC,
0047     CLK_3RD_DAC_PREDIS,
0048     CLK_3RD_DAC_TML,
0049     CLK_3RD_DAC_HIRES,
0050     CLK_ETDM_IN1_BCLK,
0051     CLK_ETDM_OUT1_BCLK,
0052     CLK_INFRA_SYS_AUDIO,
0053     CLK_INFRA_AUDIO_26M,
0054     CLK_MUX_AUDIO,
0055     CLK_MUX_AUDIOINTBUS,
0056     CLK_TOP_MAINPLL_D2_D4,
0057     /* apll related mux */
0058     CLK_TOP_MUX_AUD_1,
0059     CLK_TOP_APLL1_CK,
0060     CLK_TOP_MUX_AUD_2,
0061     CLK_TOP_APLL2_CK,
0062     CLK_TOP_MUX_AUD_ENG1,
0063     CLK_TOP_APLL1_D8,
0064     CLK_TOP_MUX_AUD_ENG2,
0065     CLK_TOP_APLL2_D8,
0066     CLK_TOP_MUX_AUDIO_H,
0067     CLK_TOP_I2S0_M_SEL,
0068     CLK_TOP_I2S1_M_SEL,
0069     CLK_TOP_I2S2_M_SEL,
0070     CLK_TOP_I2S4_M_SEL,
0071     CLK_TOP_TDM_M_SEL,
0072     CLK_TOP_APLL12_DIV0,
0073     CLK_TOP_APLL12_DIV1,
0074     CLK_TOP_APLL12_DIV2,
0075     CLK_TOP_APLL12_DIV4,
0076     CLK_TOP_APLL12_DIV_TDM,
0077     CLK_CLK26M,
0078     CLK_NUM
0079 };
0080
0081 struct mtk_base_afe;
0082 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, int clk_id);
0083 int mt8186_init_clock(struct mtk_base_afe *afe);
0084 void mt8186_deinit_clock(void *priv);
0085 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe);
0086 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe);
0087 int mt8186_afe_enable_clock(struct mtk_base_afe *afe);
0088 void mt8186_afe_disable_clock(struct mtk_base_afe *afe);
0089 int mt8186_afe_suspend_clock(struct mtk_base_afe *afe);
0090 int mt8186_afe_resume_clock(struct mtk_base_afe *afe);
0091
0092 int mt8186_apll1_enable(struct mtk_base_afe *afe);
0093 void mt8186_apll1_disable(struct mtk_base_afe *afe);
0094
0095 int mt8186_apll2_enable(struct mtk_base_afe *afe);
0096 void mt8186_apll2_disable(struct mtk_base_afe *afe);
0097
0098 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll);
0099 int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
0100 int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
0101
0102 /* these will be replaced by using CCF */
0103 int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
0104 void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id);
0105
0106 #endif