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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt8186-afe-clk.c  --  Mediatek 8186 afe clock ctrl
0004 //
0005 // Copyright (c) 2022 MediaTek Inc.
0006 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
0007 
0008 #include <linux/clk.h>
0009 #include <linux/regmap.h>
0010 #include <linux/mfd/syscon.h>
0011 
0012 #include "mt8186-afe-common.h"
0013 #include "mt8186-afe-clk.h"
0014 #include "mt8186-audsys-clk.h"
0015 
0016 static DEFINE_MUTEX(mutex_request_dram);
0017 
0018 static const char *aud_clks[CLK_NUM] = {
0019     [CLK_AFE] = "aud_afe_clk",
0020     [CLK_DAC] = "aud_dac_clk",
0021     [CLK_DAC_PREDIS] = "aud_dac_predis_clk",
0022     [CLK_ADC] = "aud_adc_clk",
0023     [CLK_TML] = "aud_tml_clk",
0024     [CLK_APLL22M] = "aud_apll22m_clk",
0025     [CLK_APLL24M] = "aud_apll24m_clk",
0026     [CLK_APLL1_TUNER] = "aud_apll_tuner_clk",
0027     [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
0028     [CLK_TDM] = "aud_tdm_clk",
0029     [CLK_NLE] = "aud_nle_clk",
0030     [CLK_DAC_HIRES] = "aud_dac_hires_clk",
0031     [CLK_ADC_HIRES] = "aud_adc_hires_clk",
0032     [CLK_I2S1_BCLK] = "aud_i2s1_bclk",
0033     [CLK_I2S2_BCLK] = "aud_i2s2_bclk",
0034     [CLK_I2S3_BCLK] = "aud_i2s3_bclk",
0035     [CLK_I2S4_BCLK] = "aud_i2s4_bclk",
0036     [CLK_CONNSYS_I2S_ASRC] = "aud_connsys_i2s_asrc",
0037     [CLK_GENERAL1_ASRC] = "aud_general1_asrc",
0038     [CLK_GENERAL2_ASRC] = "aud_general2_asrc",
0039     [CLK_ADC_HIRES_TML] = "aud_adc_hires_tml",
0040     [CLK_ADDA6_ADC] = "aud_adda6_adc",
0041     [CLK_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
0042     [CLK_3RD_DAC] = "aud_3rd_dac",
0043     [CLK_3RD_DAC_PREDIS] = "aud_3rd_dac_predis",
0044     [CLK_3RD_DAC_TML] = "aud_3rd_dac_tml",
0045     [CLK_3RD_DAC_HIRES] = "aud_3rd_dac_hires",
0046     [CLK_ETDM_IN1_BCLK] = "aud_etdm_in1_bclk",
0047     [CLK_ETDM_OUT1_BCLK] = "aud_etdm_out1_bclk",
0048     [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
0049     [CLK_INFRA_AUDIO_26M] = "mtkaif_26m_clk",
0050     [CLK_MUX_AUDIO] = "top_mux_audio",
0051     [CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
0052     [CLK_TOP_MAINPLL_D2_D4] = "top_mainpll_d2_d4",
0053     [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
0054     [CLK_TOP_APLL1_CK] = "top_apll1_ck",
0055     [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
0056     [CLK_TOP_APLL2_CK] = "top_apll2_ck",
0057     [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
0058     [CLK_TOP_APLL1_D8] = "top_apll1_d8",
0059     [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
0060     [CLK_TOP_APLL2_D8] = "top_apll2_d8",
0061     [CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
0062     [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
0063     [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
0064     [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
0065     [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
0066     [CLK_TOP_TDM_M_SEL] = "top_tdm_m_sel",
0067     [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
0068     [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
0069     [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
0070     [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
0071     [CLK_TOP_APLL12_DIV_TDM] = "top_apll12_div_tdm",
0072     [CLK_CLK26M] = "top_clk26m_clk",
0073 };
0074 
0075 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe,
0076                     int clk_id)
0077 {
0078     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0079     int ret;
0080 
0081     ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
0082                  afe_priv->clk[clk_id]);
0083     if (ret) {
0084         dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0085             __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
0086             aud_clks[clk_id], ret);
0087         return ret;
0088     }
0089 
0090     return 0;
0091 }
0092 
0093 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
0094 {
0095     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0096     int ret;
0097 
0098     if (enable) {
0099         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0100         if (ret) {
0101             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0102                 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
0103             return ret;
0104         }
0105         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0106                      afe_priv->clk[CLK_TOP_APLL1_CK]);
0107         if (ret) {
0108             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0109                 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
0110                 aud_clks[CLK_TOP_APLL1_CK], ret);
0111             return ret;
0112         }
0113 
0114         /* 180.6336 / 8 = 22.5792MHz */
0115         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0116         if (ret) {
0117             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0118                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
0119             return ret;
0120         }
0121         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0122                      afe_priv->clk[CLK_TOP_APLL1_D8]);
0123         if (ret) {
0124             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0125                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
0126                 aud_clks[CLK_TOP_APLL1_D8], ret);
0127             return ret;
0128         }
0129     } else {
0130         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0131                      afe_priv->clk[CLK_CLK26M]);
0132         if (ret) {
0133             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0134                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
0135                 aud_clks[CLK_CLK26M], ret);
0136             return ret;
0137         }
0138         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0139 
0140         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0141                      afe_priv->clk[CLK_CLK26M]);
0142         if (ret) {
0143             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0144                 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
0145                 aud_clks[CLK_CLK26M], ret);
0146             return ret;
0147         }
0148         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0149     }
0150 
0151     return 0;
0152 }
0153 
0154 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
0155 {
0156     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0157     int ret;
0158 
0159     if (enable) {
0160         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0161         if (ret) {
0162             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0163                 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
0164             return ret;
0165         }
0166         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0167                      afe_priv->clk[CLK_TOP_APLL2_CK]);
0168         if (ret) {
0169             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0170                 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
0171                 aud_clks[CLK_TOP_APLL2_CK], ret);
0172             return ret;
0173         }
0174 
0175         /* 196.608 / 8 = 24.576MHz */
0176         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0177         if (ret) {
0178             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0179                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
0180             return ret;
0181         }
0182         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0183                      afe_priv->clk[CLK_TOP_APLL2_D8]);
0184         if (ret) {
0185             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0186                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
0187                 aud_clks[CLK_TOP_APLL2_D8], ret);
0188             return ret;
0189         }
0190     } else {
0191         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0192                      afe_priv->clk[CLK_CLK26M]);
0193         if (ret) {
0194             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0195                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
0196                 aud_clks[CLK_CLK26M], ret);
0197             return ret;
0198         }
0199         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0200 
0201         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0202                      afe_priv->clk[CLK_CLK26M]);
0203         if (ret) {
0204             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0205                 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
0206                 aud_clks[CLK_CLK26M], ret);
0207             return ret;
0208         }
0209         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0210     }
0211 
0212     return 0;
0213 }
0214 
0215 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe)
0216 {
0217     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0218     int ret = 0;
0219     int i;
0220 
0221     for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++) {
0222         ret = clk_prepare_enable(afe_priv->clk[i]);
0223         if (ret) {
0224             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0225                 __func__, aud_clks[i], ret);
0226             return ret;
0227         }
0228     }
0229 
0230     return 0;
0231 }
0232 
0233 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe)
0234 {
0235     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0236     int i;
0237 
0238     for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++)
0239         clk_disable_unprepare(afe_priv->clk[i]);
0240 }
0241 
0242 int mt8186_afe_enable_clock(struct mtk_base_afe *afe)
0243 {
0244     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0245     int ret = 0;
0246 
0247     ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0248     if (ret) {
0249         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0250             __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
0251         goto clk_infra_sys_audio_err;
0252     }
0253 
0254     ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
0255     if (ret) {
0256         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0257             __func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
0258         goto clk_infra_audio_26m_err;
0259     }
0260 
0261     ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
0262     if (ret) {
0263         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0264             __func__, aud_clks[CLK_MUX_AUDIO], ret);
0265         goto clk_mux_audio_err;
0266     }
0267     ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
0268                  afe_priv->clk[CLK_CLK26M]);
0269     if (ret) {
0270         dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0271             __func__, aud_clks[CLK_MUX_AUDIO],
0272             aud_clks[CLK_CLK26M], ret);
0273         goto clk_mux_audio_err;
0274     }
0275 
0276     ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0277     if (ret) {
0278         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0279             __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
0280         goto clk_mux_audio_intbus_err;
0281     }
0282     ret = mt8186_set_audio_int_bus_parent(afe,
0283                           CLK_TOP_MAINPLL_D2_D4);
0284     if (ret)
0285         goto clk_mux_audio_intbus_parent_err;
0286 
0287     ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
0288                  afe_priv->clk[CLK_TOP_APLL2_CK]);
0289     if (ret) {
0290         dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0291             __func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
0292             aud_clks[CLK_TOP_APLL2_CK], ret);
0293         goto clk_mux_audio_h_parent_err;
0294     }
0295 
0296     ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
0297     if (ret) {
0298         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0299             __func__, aud_clks[CLK_AFE], ret);
0300         goto clk_afe_err;
0301     }
0302 
0303     return 0;
0304 
0305 clk_afe_err:
0306     clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
0307 clk_mux_audio_h_parent_err:
0308 clk_mux_audio_intbus_parent_err:
0309     mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
0310 clk_mux_audio_intbus_err:
0311     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0312 clk_mux_audio_err:
0313     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
0314 clk_infra_sys_audio_err:
0315     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0316 clk_infra_audio_26m_err:
0317     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
0318 
0319     return ret;
0320 }
0321 
0322 void mt8186_afe_disable_clock(struct mtk_base_afe *afe)
0323 {
0324     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0325 
0326     clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
0327     mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
0328     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0329     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
0330     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
0331     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0332 }
0333 
0334 int mt8186_afe_suspend_clock(struct mtk_base_afe *afe)
0335 {
0336     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0337     int ret;
0338 
0339     /* set audio int bus to 26M */
0340     ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0341     if (ret) {
0342         dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0343              __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
0344         goto clk_mux_audio_intbus_err;
0345     }
0346     ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
0347     if (ret)
0348         goto clk_mux_audio_intbus_parent_err;
0349 
0350     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0351 
0352     return 0;
0353 
0354 clk_mux_audio_intbus_parent_err:
0355     mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4);
0356 clk_mux_audio_intbus_err:
0357     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0358     return ret;
0359 }
0360 
0361 int mt8186_afe_resume_clock(struct mtk_base_afe *afe)
0362 {
0363     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0364     int ret;
0365 
0366     /* set audio int bus to normal working clock */
0367     ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0368     if (ret) {
0369         dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0370              __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
0371         goto clk_mux_audio_intbus_err;
0372     }
0373     ret = mt8186_set_audio_int_bus_parent(afe,
0374                           CLK_TOP_MAINPLL_D2_D4);
0375     if (ret)
0376         goto clk_mux_audio_intbus_parent_err;
0377 
0378     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0379 
0380     return 0;
0381 
0382 clk_mux_audio_intbus_parent_err:
0383     mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
0384 clk_mux_audio_intbus_err:
0385     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0386     return ret;
0387 }
0388 
0389 int mt8186_apll1_enable(struct mtk_base_afe *afe)
0390 {
0391     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0392     int ret;
0393 
0394     /* setting for APLL */
0395     apll1_mux_setting(afe, true);
0396 
0397     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
0398     if (ret) {
0399         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0400             __func__, aud_clks[CLK_APLL22M], ret);
0401         goto err_clk_apll22m;
0402     }
0403 
0404     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
0405     if (ret) {
0406         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0407             __func__, aud_clks[CLK_APLL1_TUNER], ret);
0408         goto err_clk_apll1_tuner;
0409     }
0410 
0411     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832);
0412     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
0413 
0414     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0415                AFE_22M_ON_MASK_SFT, BIT(AFE_22M_ON_SFT));
0416 
0417     return 0;
0418 
0419 err_clk_apll1_tuner:
0420     clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
0421 err_clk_apll22m:
0422     clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
0423 
0424     return ret;
0425 }
0426 
0427 void mt8186_apll1_disable(struct mtk_base_afe *afe)
0428 {
0429     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0430 
0431     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0432                AFE_22M_ON_MASK_SFT, 0);
0433 
0434     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0);
0435 
0436     clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
0437     clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
0438 
0439     apll1_mux_setting(afe, false);
0440 }
0441 
0442 int mt8186_apll2_enable(struct mtk_base_afe *afe)
0443 {
0444     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0445     int ret;
0446 
0447     /* setting for APLL */
0448     apll2_mux_setting(afe, true);
0449 
0450     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
0451     if (ret) {
0452         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0453             __func__, aud_clks[CLK_APLL24M], ret);
0454         goto err_clk_apll24m;
0455     }
0456 
0457     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
0458     if (ret) {
0459         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0460             __func__, aud_clks[CLK_APLL2_TUNER], ret);
0461         goto err_clk_apll2_tuner;
0462     }
0463 
0464     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634);
0465     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
0466 
0467     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0468                AFE_24M_ON_MASK_SFT, BIT(AFE_24M_ON_SFT));
0469 
0470     return 0;
0471 
0472 err_clk_apll2_tuner:
0473     clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
0474 err_clk_apll24m:
0475     clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
0476 
0477     return ret;
0478 }
0479 
0480 void mt8186_apll2_disable(struct mtk_base_afe *afe)
0481 {
0482     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0483 
0484     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0485                AFE_24M_ON_MASK_SFT, 0);
0486 
0487     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0);
0488 
0489     clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
0490     clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
0491 
0492     apll2_mux_setting(afe, false);
0493 }
0494 
0495 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll)
0496 {
0497     return (apll == MT8186_APLL1) ? 180633600 : 196608000;
0498 }
0499 
0500 int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
0501 {
0502     return ((rate % 8000) == 0) ? MT8186_APLL2 : MT8186_APLL1;
0503 }
0504 
0505 int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
0506 {
0507     if (strcmp(name, APLL1_W_NAME) == 0)
0508         return MT8186_APLL1;
0509 
0510     return MT8186_APLL2;
0511 }
0512 
0513 /* mck */
0514 struct mt8186_mck_div {
0515     u32 m_sel_id;
0516     u32 div_clk_id;
0517 };
0518 
0519 static const struct mt8186_mck_div mck_div[MT8186_MCK_NUM] = {
0520     [MT8186_I2S0_MCK] = {
0521         .m_sel_id = CLK_TOP_I2S0_M_SEL,
0522         .div_clk_id = CLK_TOP_APLL12_DIV0,
0523     },
0524     [MT8186_I2S1_MCK] = {
0525         .m_sel_id = CLK_TOP_I2S1_M_SEL,
0526         .div_clk_id = CLK_TOP_APLL12_DIV1,
0527     },
0528     [MT8186_I2S2_MCK] = {
0529         .m_sel_id = CLK_TOP_I2S2_M_SEL,
0530         .div_clk_id = CLK_TOP_APLL12_DIV2,
0531     },
0532     [MT8186_I2S4_MCK] = {
0533         .m_sel_id = CLK_TOP_I2S4_M_SEL,
0534         .div_clk_id = CLK_TOP_APLL12_DIV4,
0535     },
0536     [MT8186_TDM_MCK] = {
0537         .m_sel_id = CLK_TOP_TDM_M_SEL,
0538         .div_clk_id = CLK_TOP_APLL12_DIV_TDM,
0539     },
0540 };
0541 
0542 int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
0543 {
0544     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0545     int apll = mt8186_get_apll_by_rate(afe, rate);
0546     int apll_clk_id = apll == MT8186_APLL1 ?
0547               CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
0548     int m_sel_id = mck_div[mck_id].m_sel_id;
0549     int div_clk_id = mck_div[mck_id].div_clk_id;
0550     int ret;
0551 
0552     /* select apll */
0553     if (m_sel_id >= 0) {
0554         ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
0555         if (ret) {
0556             dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0557                 __func__, aud_clks[m_sel_id], ret);
0558             return ret;
0559         }
0560         ret = clk_set_parent(afe_priv->clk[m_sel_id],
0561                      afe_priv->clk[apll_clk_id]);
0562         if (ret) {
0563             dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
0564                 __func__, aud_clks[m_sel_id],
0565                 aud_clks[apll_clk_id], ret);
0566             return ret;
0567         }
0568     }
0569 
0570     /* enable div, set rate */
0571     ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
0572     if (ret) {
0573         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0574             __func__, aud_clks[div_clk_id], ret);
0575         return ret;
0576     }
0577     ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
0578     if (ret) {
0579         dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
0580             __func__, aud_clks[div_clk_id], rate, ret);
0581         return ret;
0582     }
0583 
0584     return 0;
0585 }
0586 
0587 void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id)
0588 {
0589     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0590     int m_sel_id = mck_div[mck_id].m_sel_id;
0591     int div_clk_id = mck_div[mck_id].div_clk_id;
0592 
0593     clk_disable_unprepare(afe_priv->clk[div_clk_id]);
0594     if (m_sel_id >= 0)
0595         clk_disable_unprepare(afe_priv->clk[m_sel_id]);
0596 }
0597 
0598 int mt8186_init_clock(struct mtk_base_afe *afe)
0599 {
0600     struct mt8186_afe_private *afe_priv = afe->platform_priv;
0601     struct device_node *of_node = afe->dev->of_node;
0602     int i = 0;
0603 
0604     mt8186_audsys_clk_register(afe);
0605 
0606     afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
0607                      GFP_KERNEL);
0608     if (!afe_priv->clk)
0609         return -ENOMEM;
0610 
0611     for (i = 0; i < CLK_NUM; i++) {
0612         afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
0613         if (IS_ERR(afe_priv->clk[i])) {
0614             dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
0615                 __func__,
0616                 aud_clks[i], PTR_ERR(afe_priv->clk[i]));
0617             afe_priv->clk[i] = NULL;
0618         }
0619     }
0620 
0621     afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
0622                                    "mediatek,apmixedsys");
0623     if (IS_ERR(afe_priv->apmixedsys)) {
0624         dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
0625             __func__, PTR_ERR(afe_priv->apmixedsys));
0626         return PTR_ERR(afe_priv->apmixedsys);
0627     }
0628 
0629     afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
0630                                  "mediatek,topckgen");
0631     if (IS_ERR(afe_priv->topckgen)) {
0632         dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
0633             __func__, PTR_ERR(afe_priv->topckgen));
0634         return PTR_ERR(afe_priv->topckgen);
0635     }
0636 
0637     afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
0638                                  "mediatek,infracfg");
0639     if (IS_ERR(afe_priv->infracfg)) {
0640         dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
0641             __func__, PTR_ERR(afe_priv->infracfg));
0642         return PTR_ERR(afe_priv->infracfg);
0643     }
0644 
0645     return 0;
0646 }
0647 
0648 void mt8186_deinit_clock(void *priv)
0649 {
0650     struct mtk_base_afe *afe = priv;
0651     mt8186_audsys_clk_unregister(afe);
0652 }
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