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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Mediatek ALSA SoC AFE platform driver for 8183
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007 
0008 #include <linux/delay.h>
0009 #include <linux/module.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/reset.h>
0015 
0016 #include "mt8183-afe-common.h"
0017 #include "mt8183-afe-clk.h"
0018 #include "mt8183-interconnection.h"
0019 #include "mt8183-reg.h"
0020 #include "../common/mtk-afe-platform-driver.h"
0021 #include "../common/mtk-afe-fe-dai.h"
0022 
0023 enum {
0024     MTK_AFE_RATE_8K = 0,
0025     MTK_AFE_RATE_11K = 1,
0026     MTK_AFE_RATE_12K = 2,
0027     MTK_AFE_RATE_384K = 3,
0028     MTK_AFE_RATE_16K = 4,
0029     MTK_AFE_RATE_22K = 5,
0030     MTK_AFE_RATE_24K = 6,
0031     MTK_AFE_RATE_130K = 7,
0032     MTK_AFE_RATE_32K = 8,
0033     MTK_AFE_RATE_44K = 9,
0034     MTK_AFE_RATE_48K = 10,
0035     MTK_AFE_RATE_88K = 11,
0036     MTK_AFE_RATE_96K = 12,
0037     MTK_AFE_RATE_176K = 13,
0038     MTK_AFE_RATE_192K = 14,
0039     MTK_AFE_RATE_260K = 15,
0040 };
0041 
0042 enum {
0043     MTK_AFE_DAI_MEMIF_RATE_8K = 0,
0044     MTK_AFE_DAI_MEMIF_RATE_16K = 1,
0045     MTK_AFE_DAI_MEMIF_RATE_32K = 2,
0046     MTK_AFE_DAI_MEMIF_RATE_48K = 3,
0047 };
0048 
0049 enum {
0050     MTK_AFE_PCM_RATE_8K = 0,
0051     MTK_AFE_PCM_RATE_16K = 1,
0052     MTK_AFE_PCM_RATE_32K = 2,
0053     MTK_AFE_PCM_RATE_48K = 3,
0054 };
0055 
0056 unsigned int mt8183_general_rate_transform(struct device *dev,
0057                        unsigned int rate)
0058 {
0059     switch (rate) {
0060     case 8000:
0061         return MTK_AFE_RATE_8K;
0062     case 11025:
0063         return MTK_AFE_RATE_11K;
0064     case 12000:
0065         return MTK_AFE_RATE_12K;
0066     case 16000:
0067         return MTK_AFE_RATE_16K;
0068     case 22050:
0069         return MTK_AFE_RATE_22K;
0070     case 24000:
0071         return MTK_AFE_RATE_24K;
0072     case 32000:
0073         return MTK_AFE_RATE_32K;
0074     case 44100:
0075         return MTK_AFE_RATE_44K;
0076     case 48000:
0077         return MTK_AFE_RATE_48K;
0078     case 88200:
0079         return MTK_AFE_RATE_88K;
0080     case 96000:
0081         return MTK_AFE_RATE_96K;
0082     case 130000:
0083         return MTK_AFE_RATE_130K;
0084     case 176400:
0085         return MTK_AFE_RATE_176K;
0086     case 192000:
0087         return MTK_AFE_RATE_192K;
0088     case 260000:
0089         return MTK_AFE_RATE_260K;
0090     default:
0091         dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
0092              __func__, rate, MTK_AFE_RATE_48K);
0093         return MTK_AFE_RATE_48K;
0094     }
0095 }
0096 
0097 static unsigned int dai_memif_rate_transform(struct device *dev,
0098                          unsigned int rate)
0099 {
0100     switch (rate) {
0101     case 8000:
0102         return MTK_AFE_DAI_MEMIF_RATE_8K;
0103     case 16000:
0104         return MTK_AFE_DAI_MEMIF_RATE_16K;
0105     case 32000:
0106         return MTK_AFE_DAI_MEMIF_RATE_32K;
0107     case 48000:
0108         return MTK_AFE_DAI_MEMIF_RATE_48K;
0109     default:
0110         dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
0111              __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
0112         return MTK_AFE_DAI_MEMIF_RATE_16K;
0113     }
0114 }
0115 
0116 unsigned int mt8183_rate_transform(struct device *dev,
0117                    unsigned int rate, int aud_blk)
0118 {
0119     switch (aud_blk) {
0120     case MT8183_MEMIF_MOD_DAI:
0121         return dai_memif_rate_transform(dev, rate);
0122     default:
0123         return mt8183_general_rate_transform(dev, rate);
0124     }
0125 }
0126 
0127 static const struct snd_pcm_hardware mt8183_afe_hardware = {
0128     .info = SNDRV_PCM_INFO_MMAP |
0129         SNDRV_PCM_INFO_INTERLEAVED |
0130         SNDRV_PCM_INFO_MMAP_VALID,
0131     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0132            SNDRV_PCM_FMTBIT_S24_LE |
0133            SNDRV_PCM_FMTBIT_S32_LE,
0134     .period_bytes_min = 256,
0135     .period_bytes_max = 4 * 48 * 1024,
0136     .periods_min = 2,
0137     .periods_max = 256,
0138     .buffer_bytes_max = 8 * 48 * 1024,
0139     .fifo_size = 0,
0140 };
0141 
0142 static int mt8183_memif_fs(struct snd_pcm_substream *substream,
0143                unsigned int rate)
0144 {
0145     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0146     struct snd_soc_component *component =
0147         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0148     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0149     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0150 
0151     return mt8183_rate_transform(afe->dev, rate, id);
0152 }
0153 
0154 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
0155 {
0156     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0157     struct snd_soc_component *component =
0158         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0159     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0160 
0161     return mt8183_general_rate_transform(afe->dev, rate);
0162 }
0163 
0164 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
0165                SNDRV_PCM_RATE_88200 |\
0166                SNDRV_PCM_RATE_96000 |\
0167                SNDRV_PCM_RATE_176400 |\
0168                SNDRV_PCM_RATE_192000)
0169 
0170 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
0171                SNDRV_PCM_RATE_16000 |\
0172                SNDRV_PCM_RATE_32000 |\
0173                SNDRV_PCM_RATE_48000)
0174 
0175 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0176              SNDRV_PCM_FMTBIT_S24_LE |\
0177              SNDRV_PCM_FMTBIT_S32_LE)
0178 
0179 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
0180     /* FE DAIs: memory intefaces to CPU */
0181     {
0182         .name = "DL1",
0183         .id = MT8183_MEMIF_DL1,
0184         .playback = {
0185             .stream_name = "DL1",
0186             .channels_min = 1,
0187             .channels_max = 2,
0188             .rates = MTK_PCM_RATES,
0189             .formats = MTK_PCM_FORMATS,
0190         },
0191         .ops = &mtk_afe_fe_ops,
0192     },
0193     {
0194         .name = "DL2",
0195         .id = MT8183_MEMIF_DL2,
0196         .playback = {
0197             .stream_name = "DL2",
0198             .channels_min = 1,
0199             .channels_max = 2,
0200             .rates = MTK_PCM_RATES,
0201             .formats = MTK_PCM_FORMATS,
0202         },
0203         .ops = &mtk_afe_fe_ops,
0204     },
0205     {
0206         .name = "DL3",
0207         .id = MT8183_MEMIF_DL3,
0208         .playback = {
0209             .stream_name = "DL3",
0210             .channels_min = 1,
0211             .channels_max = 2,
0212             .rates = MTK_PCM_RATES,
0213             .formats = MTK_PCM_FORMATS,
0214         },
0215         .ops = &mtk_afe_fe_ops,
0216     },
0217     {
0218         .name = "UL1",
0219         .id = MT8183_MEMIF_VUL12,
0220         .capture = {
0221             .stream_name = "UL1",
0222             .channels_min = 1,
0223             .channels_max = 2,
0224             .rates = MTK_PCM_RATES,
0225             .formats = MTK_PCM_FORMATS,
0226         },
0227         .ops = &mtk_afe_fe_ops,
0228     },
0229     {
0230         .name = "UL2",
0231         .id = MT8183_MEMIF_AWB,
0232         .capture = {
0233             .stream_name = "UL2",
0234             .channels_min = 1,
0235             .channels_max = 2,
0236             .rates = MTK_PCM_RATES,
0237             .formats = MTK_PCM_FORMATS,
0238         },
0239         .ops = &mtk_afe_fe_ops,
0240     },
0241     {
0242         .name = "UL3",
0243         .id = MT8183_MEMIF_VUL2,
0244         .capture = {
0245             .stream_name = "UL3",
0246             .channels_min = 1,
0247             .channels_max = 2,
0248             .rates = MTK_PCM_RATES,
0249             .formats = MTK_PCM_FORMATS,
0250         },
0251         .ops = &mtk_afe_fe_ops,
0252     },
0253     {
0254         .name = "UL4",
0255         .id = MT8183_MEMIF_AWB2,
0256         .capture = {
0257             .stream_name = "UL4",
0258             .channels_min = 1,
0259             .channels_max = 2,
0260             .rates = MTK_PCM_RATES,
0261             .formats = MTK_PCM_FORMATS,
0262         },
0263         .ops = &mtk_afe_fe_ops,
0264     },
0265     {
0266         .name = "UL_MONO_1",
0267         .id = MT8183_MEMIF_MOD_DAI,
0268         .capture = {
0269             .stream_name = "UL_MONO_1",
0270             .channels_min = 1,
0271             .channels_max = 1,
0272             .rates = MTK_PCM_DAI_RATES,
0273             .formats = MTK_PCM_FORMATS,
0274         },
0275         .ops = &mtk_afe_fe_ops,
0276     },
0277     {
0278         .name = "HDMI",
0279         .id = MT8183_MEMIF_HDMI,
0280         .playback = {
0281             .stream_name = "HDMI",
0282             .channels_min = 2,
0283             .channels_max = 8,
0284             .rates = MTK_PCM_RATES,
0285             .formats = MTK_PCM_FORMATS,
0286         },
0287         .ops = &mtk_afe_fe_ops,
0288     },
0289 };
0290 
0291 /* dma widget & routes*/
0292 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
0293     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
0294                     I_ADDA_UL_CH1, 1, 0),
0295     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
0296                     I_I2S0_CH1, 1, 0),
0297 };
0298 
0299 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
0300     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
0301                     I_ADDA_UL_CH2, 1, 0),
0302     SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
0303                     I_I2S0_CH2, 1, 0),
0304 };
0305 
0306 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
0307     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
0308                     I_ADDA_UL_CH1, 1, 0),
0309     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
0310                     I_DL1_CH1, 1, 0),
0311     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
0312                     I_DL2_CH1, 1, 0),
0313     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
0314                     I_DL3_CH1, 1, 0),
0315     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
0316                     I_I2S2_CH1, 1, 0),
0317 };
0318 
0319 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
0320     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
0321                     I_ADDA_UL_CH2, 1, 0),
0322     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
0323                     I_DL1_CH2, 1, 0),
0324     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
0325                     I_DL2_CH2, 1, 0),
0326     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
0327                     I_DL3_CH2, 1, 0),
0328     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
0329                     I_I2S2_CH2, 1, 0),
0330 };
0331 
0332 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
0333     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
0334                     I_ADDA_UL_CH1, 1, 0),
0335     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
0336                     I_I2S2_CH1, 1, 0),
0337 };
0338 
0339 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
0340     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
0341                     I_ADDA_UL_CH2, 1, 0),
0342     SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
0343                     I_I2S2_CH2, 1, 0),
0344 };
0345 
0346 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
0347     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
0348                     I_ADDA_UL_CH1, 1, 0),
0349 };
0350 
0351 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
0352     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
0353                     I_ADDA_UL_CH2, 1, 0),
0354 };
0355 
0356 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
0357     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
0358                     I_ADDA_UL_CH1, 1, 0),
0359     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
0360                     I_ADDA_UL_CH2, 1, 0),
0361 };
0362 
0363 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
0364     /* memif */
0365     SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
0366                memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
0367     SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
0368                memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
0369 
0370     SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
0371                memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
0372     SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
0373                memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
0374 
0375     SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
0376                memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
0377     SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
0378                memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
0379 
0380     SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
0381                memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
0382     SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
0383                memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
0384 
0385     SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
0386                memif_ul_mono_1_mix,
0387                ARRAY_SIZE(memif_ul_mono_1_mix)),
0388 };
0389 
0390 static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
0391     /* capture */
0392     {"UL1", NULL, "UL1_CH1"},
0393     {"UL1", NULL, "UL1_CH2"},
0394     {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0395     {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0396     {"UL1_CH1", "I2S0_CH1", "I2S0"},
0397     {"UL1_CH2", "I2S0_CH2", "I2S0"},
0398 
0399     {"UL2", NULL, "UL2_CH1"},
0400     {"UL2", NULL, "UL2_CH2"},
0401     {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0402     {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0403     {"UL2_CH1", "I2S2_CH1", "I2S2"},
0404     {"UL2_CH2", "I2S2_CH2", "I2S2"},
0405 
0406     {"UL3", NULL, "UL3_CH1"},
0407     {"UL3", NULL, "UL3_CH2"},
0408     {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0409     {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0410     {"UL3_CH1", "I2S2_CH1", "I2S2"},
0411     {"UL3_CH2", "I2S2_CH2", "I2S2"},
0412 
0413     {"UL4", NULL, "UL4_CH1"},
0414     {"UL4", NULL, "UL4_CH2"},
0415     {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0416     {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0417 
0418     {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
0419     {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0420     {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
0421 };
0422 
0423 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
0424     .name = "mt8183-afe-pcm-dai",
0425 };
0426 
0427 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
0428     [MT8183_MEMIF_DL1] = {
0429         .name = "DL1",
0430         .id = MT8183_MEMIF_DL1,
0431         .reg_ofs_base = AFE_DL1_BASE,
0432         .reg_ofs_cur = AFE_DL1_CUR,
0433         .fs_reg = AFE_DAC_CON1,
0434         .fs_shift = DL1_MODE_SFT,
0435         .fs_maskbit = DL1_MODE_MASK,
0436         .mono_reg = AFE_DAC_CON1,
0437         .mono_shift = DL1_DATA_SFT,
0438         .enable_reg = AFE_DAC_CON0,
0439         .enable_shift = DL1_ON_SFT,
0440         .hd_reg = AFE_MEMIF_HD_MODE,
0441         .hd_align_reg = AFE_MEMIF_HDALIGN,
0442         .hd_shift = DL1_HD_SFT,
0443         .hd_align_mshift = DL1_HD_ALIGN_SFT,
0444         .agent_disable_reg = -1,
0445         .agent_disable_shift = -1,
0446         .msb_reg = -1,
0447         .msb_shift = -1,
0448     },
0449     [MT8183_MEMIF_DL2] = {
0450         .name = "DL2",
0451         .id = MT8183_MEMIF_DL2,
0452         .reg_ofs_base = AFE_DL2_BASE,
0453         .reg_ofs_cur = AFE_DL2_CUR,
0454         .fs_reg = AFE_DAC_CON1,
0455         .fs_shift = DL2_MODE_SFT,
0456         .fs_maskbit = DL2_MODE_MASK,
0457         .mono_reg = AFE_DAC_CON1,
0458         .mono_shift = DL2_DATA_SFT,
0459         .enable_reg = AFE_DAC_CON0,
0460         .enable_shift = DL2_ON_SFT,
0461         .hd_reg = AFE_MEMIF_HD_MODE,
0462         .hd_align_reg = AFE_MEMIF_HDALIGN,
0463         .hd_shift = DL2_HD_SFT,
0464         .hd_align_mshift = DL2_HD_ALIGN_SFT,
0465         .agent_disable_reg = -1,
0466         .agent_disable_shift = -1,
0467         .msb_reg = -1,
0468         .msb_shift = -1,
0469     },
0470     [MT8183_MEMIF_DL3] = {
0471         .name = "DL3",
0472         .id = MT8183_MEMIF_DL3,
0473         .reg_ofs_base = AFE_DL3_BASE,
0474         .reg_ofs_cur = AFE_DL3_CUR,
0475         .fs_reg = AFE_DAC_CON2,
0476         .fs_shift = DL3_MODE_SFT,
0477         .fs_maskbit = DL3_MODE_MASK,
0478         .mono_reg = AFE_DAC_CON1,
0479         .mono_shift = DL3_DATA_SFT,
0480         .enable_reg = AFE_DAC_CON0,
0481         .enable_shift = DL3_ON_SFT,
0482         .hd_reg = AFE_MEMIF_HD_MODE,
0483         .hd_align_reg = AFE_MEMIF_HDALIGN,
0484         .hd_shift = DL3_HD_SFT,
0485         .hd_align_mshift = DL3_HD_ALIGN_SFT,
0486         .agent_disable_reg = -1,
0487         .agent_disable_shift = -1,
0488         .msb_reg = -1,
0489         .msb_shift = -1,
0490     },
0491     [MT8183_MEMIF_VUL2] = {
0492         .name = "VUL2",
0493         .id = MT8183_MEMIF_VUL2,
0494         .reg_ofs_base = AFE_VUL2_BASE,
0495         .reg_ofs_cur = AFE_VUL2_CUR,
0496         .fs_reg = AFE_DAC_CON2,
0497         .fs_shift = VUL2_MODE_SFT,
0498         .fs_maskbit = VUL2_MODE_MASK,
0499         .mono_reg = AFE_DAC_CON2,
0500         .mono_shift = VUL2_DATA_SFT,
0501         .enable_reg = AFE_DAC_CON0,
0502         .enable_shift = VUL2_ON_SFT,
0503         .hd_reg = AFE_MEMIF_HD_MODE,
0504         .hd_align_reg = AFE_MEMIF_HDALIGN,
0505         .hd_shift = VUL2_HD_SFT,
0506         .hd_align_mshift = VUL2_HD_ALIGN_SFT,
0507         .agent_disable_reg = -1,
0508         .agent_disable_shift = -1,
0509         .msb_reg = -1,
0510         .msb_shift = -1,
0511     },
0512     [MT8183_MEMIF_AWB] = {
0513         .name = "AWB",
0514         .id = MT8183_MEMIF_AWB,
0515         .reg_ofs_base = AFE_AWB_BASE,
0516         .reg_ofs_cur = AFE_AWB_CUR,
0517         .fs_reg = AFE_DAC_CON1,
0518         .fs_shift = AWB_MODE_SFT,
0519         .fs_maskbit = AWB_MODE_MASK,
0520         .mono_reg = AFE_DAC_CON1,
0521         .mono_shift = AWB_DATA_SFT,
0522         .enable_reg = AFE_DAC_CON0,
0523         .enable_shift = AWB_ON_SFT,
0524         .hd_reg = AFE_MEMIF_HD_MODE,
0525         .hd_align_reg = AFE_MEMIF_HDALIGN,
0526         .hd_shift = AWB_HD_SFT,
0527         .hd_align_mshift = AWB_HD_ALIGN_SFT,
0528         .agent_disable_reg = -1,
0529         .agent_disable_shift = -1,
0530         .msb_reg = -1,
0531         .msb_shift = -1,
0532     },
0533     [MT8183_MEMIF_AWB2] = {
0534         .name = "AWB2",
0535         .id = MT8183_MEMIF_AWB2,
0536         .reg_ofs_base = AFE_AWB2_BASE,
0537         .reg_ofs_cur = AFE_AWB2_CUR,
0538         .fs_reg = AFE_DAC_CON2,
0539         .fs_shift = AWB2_MODE_SFT,
0540         .fs_maskbit = AWB2_MODE_MASK,
0541         .mono_reg = AFE_DAC_CON2,
0542         .mono_shift = AWB2_DATA_SFT,
0543         .enable_reg = AFE_DAC_CON0,
0544         .enable_shift = AWB2_ON_SFT,
0545         .hd_reg = AFE_MEMIF_HD_MODE,
0546         .hd_align_reg = AFE_MEMIF_HDALIGN,
0547         .hd_shift = AWB2_HD_SFT,
0548         .hd_align_mshift = AWB2_ALIGN_SFT,
0549         .agent_disable_reg = -1,
0550         .agent_disable_shift = -1,
0551         .msb_reg = -1,
0552         .msb_shift = -1,
0553     },
0554     [MT8183_MEMIF_VUL12] = {
0555         .name = "VUL12",
0556         .id = MT8183_MEMIF_VUL12,
0557         .reg_ofs_base = AFE_VUL_D2_BASE,
0558         .reg_ofs_cur = AFE_VUL_D2_CUR,
0559         .fs_reg = AFE_DAC_CON0,
0560         .fs_shift = VUL12_MODE_SFT,
0561         .fs_maskbit = VUL12_MODE_MASK,
0562         .mono_reg = AFE_DAC_CON0,
0563         .mono_shift = VUL12_MONO_SFT,
0564         .enable_reg = AFE_DAC_CON0,
0565         .enable_shift = VUL12_ON_SFT,
0566         .hd_reg = AFE_MEMIF_HD_MODE,
0567         .hd_align_reg = AFE_MEMIF_HDALIGN,
0568         .hd_shift = VUL12_HD_SFT,
0569         .hd_align_mshift = VUL12_HD_ALIGN_SFT,
0570         .agent_disable_reg = -1,
0571         .agent_disable_shift = -1,
0572         .msb_reg = -1,
0573         .msb_shift = -1,
0574     },
0575     [MT8183_MEMIF_MOD_DAI] = {
0576         .name = "MOD_DAI",
0577         .id = MT8183_MEMIF_MOD_DAI,
0578         .reg_ofs_base = AFE_MOD_DAI_BASE,
0579         .reg_ofs_cur = AFE_MOD_DAI_CUR,
0580         .fs_reg = AFE_DAC_CON1,
0581         .fs_shift = MOD_DAI_MODE_SFT,
0582         .fs_maskbit = MOD_DAI_MODE_MASK,
0583         .mono_reg = -1,
0584         .mono_shift = 0,
0585         .enable_reg = AFE_DAC_CON0,
0586         .enable_shift = MOD_DAI_ON_SFT,
0587         .hd_reg = AFE_MEMIF_HD_MODE,
0588         .hd_align_reg = AFE_MEMIF_HDALIGN,
0589         .hd_shift = MOD_DAI_HD_SFT,
0590         .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
0591         .agent_disable_reg = -1,
0592         .agent_disable_shift = -1,
0593         .msb_reg = -1,
0594         .msb_shift = -1,
0595     },
0596     [MT8183_MEMIF_HDMI] = {
0597         .name = "HDMI",
0598         .id = MT8183_MEMIF_HDMI,
0599         .reg_ofs_base = AFE_HDMI_OUT_BASE,
0600         .reg_ofs_cur = AFE_HDMI_OUT_CUR,
0601         .fs_reg = -1,
0602         .fs_shift = -1,
0603         .fs_maskbit = -1,
0604         .mono_reg = -1,
0605         .mono_shift = -1,
0606         .enable_reg = -1,   /* control in tdm for sync start */
0607         .enable_shift = -1,
0608         .hd_reg = AFE_MEMIF_HD_MODE,
0609         .hd_align_reg = AFE_MEMIF_HDALIGN,
0610         .hd_shift = HDMI_HD_SFT,
0611         .hd_align_mshift = HDMI_HD_ALIGN_SFT,
0612         .agent_disable_reg = -1,
0613         .agent_disable_shift = -1,
0614         .msb_reg = -1,
0615         .msb_shift = -1,
0616     },
0617 };
0618 
0619 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
0620     [MT8183_IRQ_0] = {
0621         .id = MT8183_IRQ_0,
0622         .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
0623         .irq_cnt_shift = 0,
0624         .irq_cnt_maskbit = 0x3ffff,
0625         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0626         .irq_fs_shift = IRQ0_MCU_MODE_SFT,
0627         .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
0628         .irq_en_reg = AFE_IRQ_MCU_CON0,
0629         .irq_en_shift = IRQ0_MCU_ON_SFT,
0630         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0631         .irq_clr_shift = IRQ0_MCU_CLR_SFT,
0632     },
0633     [MT8183_IRQ_1] = {
0634         .id = MT8183_IRQ_1,
0635         .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
0636         .irq_cnt_shift = 0,
0637         .irq_cnt_maskbit = 0x3ffff,
0638         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0639         .irq_fs_shift = IRQ1_MCU_MODE_SFT,
0640         .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
0641         .irq_en_reg = AFE_IRQ_MCU_CON0,
0642         .irq_en_shift = IRQ1_MCU_ON_SFT,
0643         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0644         .irq_clr_shift = IRQ1_MCU_CLR_SFT,
0645     },
0646     [MT8183_IRQ_2] = {
0647         .id = MT8183_IRQ_2,
0648         .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
0649         .irq_cnt_shift = 0,
0650         .irq_cnt_maskbit = 0x3ffff,
0651         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0652         .irq_fs_shift = IRQ2_MCU_MODE_SFT,
0653         .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
0654         .irq_en_reg = AFE_IRQ_MCU_CON0,
0655         .irq_en_shift = IRQ2_MCU_ON_SFT,
0656         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0657         .irq_clr_shift = IRQ2_MCU_CLR_SFT,
0658     },
0659     [MT8183_IRQ_3] = {
0660         .id = MT8183_IRQ_3,
0661         .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
0662         .irq_cnt_shift = 0,
0663         .irq_cnt_maskbit = 0x3ffff,
0664         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0665         .irq_fs_shift = IRQ3_MCU_MODE_SFT,
0666         .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
0667         .irq_en_reg = AFE_IRQ_MCU_CON0,
0668         .irq_en_shift = IRQ3_MCU_ON_SFT,
0669         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0670         .irq_clr_shift = IRQ3_MCU_CLR_SFT,
0671     },
0672     [MT8183_IRQ_4] = {
0673         .id = MT8183_IRQ_4,
0674         .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
0675         .irq_cnt_shift = 0,
0676         .irq_cnt_maskbit = 0x3ffff,
0677         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0678         .irq_fs_shift = IRQ4_MCU_MODE_SFT,
0679         .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
0680         .irq_en_reg = AFE_IRQ_MCU_CON0,
0681         .irq_en_shift = IRQ4_MCU_ON_SFT,
0682         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0683         .irq_clr_shift = IRQ4_MCU_CLR_SFT,
0684     },
0685     [MT8183_IRQ_5] = {
0686         .id = MT8183_IRQ_5,
0687         .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
0688         .irq_cnt_shift = 0,
0689         .irq_cnt_maskbit = 0x3ffff,
0690         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0691         .irq_fs_shift = IRQ5_MCU_MODE_SFT,
0692         .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
0693         .irq_en_reg = AFE_IRQ_MCU_CON0,
0694         .irq_en_shift = IRQ5_MCU_ON_SFT,
0695         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0696         .irq_clr_shift = IRQ5_MCU_CLR_SFT,
0697     },
0698     [MT8183_IRQ_6] = {
0699         .id = MT8183_IRQ_6,
0700         .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
0701         .irq_cnt_shift = 0,
0702         .irq_cnt_maskbit = 0x3ffff,
0703         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0704         .irq_fs_shift = IRQ6_MCU_MODE_SFT,
0705         .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
0706         .irq_en_reg = AFE_IRQ_MCU_CON0,
0707         .irq_en_shift = IRQ6_MCU_ON_SFT,
0708         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0709         .irq_clr_shift = IRQ6_MCU_CLR_SFT,
0710     },
0711     [MT8183_IRQ_7] = {
0712         .id = MT8183_IRQ_7,
0713         .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
0714         .irq_cnt_shift = 0,
0715         .irq_cnt_maskbit = 0x3ffff,
0716         .irq_fs_reg = AFE_IRQ_MCU_CON1,
0717         .irq_fs_shift = IRQ7_MCU_MODE_SFT,
0718         .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
0719         .irq_en_reg = AFE_IRQ_MCU_CON0,
0720         .irq_en_shift = IRQ7_MCU_ON_SFT,
0721         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0722         .irq_clr_shift = IRQ7_MCU_CLR_SFT,
0723     },
0724     [MT8183_IRQ_8] = {
0725         .id = MT8183_IRQ_8,
0726         .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
0727         .irq_cnt_shift = 0,
0728         .irq_cnt_maskbit = 0x3ffff,
0729         .irq_fs_reg = -1,
0730         .irq_fs_shift = -1,
0731         .irq_fs_maskbit = -1,
0732         .irq_en_reg = AFE_IRQ_MCU_CON0,
0733         .irq_en_shift = IRQ8_MCU_ON_SFT,
0734         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0735         .irq_clr_shift = IRQ8_MCU_CLR_SFT,
0736     },
0737     [MT8183_IRQ_11] = {
0738         .id = MT8183_IRQ_11,
0739         .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
0740         .irq_cnt_shift = 0,
0741         .irq_cnt_maskbit = 0x3ffff,
0742         .irq_fs_reg = AFE_IRQ_MCU_CON2,
0743         .irq_fs_shift = IRQ11_MCU_MODE_SFT,
0744         .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
0745         .irq_en_reg = AFE_IRQ_MCU_CON0,
0746         .irq_en_shift = IRQ11_MCU_ON_SFT,
0747         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0748         .irq_clr_shift = IRQ11_MCU_CLR_SFT,
0749     },
0750     [MT8183_IRQ_12] = {
0751         .id = MT8183_IRQ_12,
0752         .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
0753         .irq_cnt_shift = 0,
0754         .irq_cnt_maskbit = 0x3ffff,
0755         .irq_fs_reg = AFE_IRQ_MCU_CON2,
0756         .irq_fs_shift = IRQ12_MCU_MODE_SFT,
0757         .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
0758         .irq_en_reg = AFE_IRQ_MCU_CON0,
0759         .irq_en_shift = IRQ12_MCU_ON_SFT,
0760         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0761         .irq_clr_shift = IRQ12_MCU_CLR_SFT,
0762     },
0763 };
0764 
0765 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
0766 {
0767     /* these auto-gen reg has read-only bit, so put it as volatile */
0768     /* volatile reg cannot be cached, so cannot be set when power off */
0769     switch (reg) {
0770     case AUDIO_TOP_CON0:    /* reg bit controlled by CCF */
0771     case AUDIO_TOP_CON1:    /* reg bit controlled by CCF */
0772     case AUDIO_TOP_CON3:
0773     case AFE_DL1_CUR:
0774     case AFE_DL1_END:
0775     case AFE_DL2_CUR:
0776     case AFE_DL2_END:
0777     case AFE_AWB_END:
0778     case AFE_AWB_CUR:
0779     case AFE_VUL_END:
0780     case AFE_VUL_CUR:
0781     case AFE_MEMIF_MON0:
0782     case AFE_MEMIF_MON1:
0783     case AFE_MEMIF_MON2:
0784     case AFE_MEMIF_MON3:
0785     case AFE_MEMIF_MON4:
0786     case AFE_MEMIF_MON5:
0787     case AFE_MEMIF_MON6:
0788     case AFE_MEMIF_MON7:
0789     case AFE_MEMIF_MON8:
0790     case AFE_MEMIF_MON9:
0791     case AFE_ADDA_SRC_DEBUG_MON0:
0792     case AFE_ADDA_SRC_DEBUG_MON1:
0793     case AFE_ADDA_UL_SRC_MON0:
0794     case AFE_ADDA_UL_SRC_MON1:
0795     case AFE_SIDETONE_MON:
0796     case AFE_SIDETONE_CON0:
0797     case AFE_SIDETONE_COEFF:
0798     case AFE_BUS_MON0:
0799     case AFE_MRGIF_MON0:
0800     case AFE_MRGIF_MON1:
0801     case AFE_MRGIF_MON2:
0802     case AFE_I2S_MON:
0803     case AFE_DAC_MON:
0804     case AFE_VUL2_END:
0805     case AFE_VUL2_CUR:
0806     case AFE_IRQ0_MCU_CNT_MON:
0807     case AFE_IRQ6_MCU_CNT_MON:
0808     case AFE_MOD_DAI_END:
0809     case AFE_MOD_DAI_CUR:
0810     case AFE_VUL_D2_END:
0811     case AFE_VUL_D2_CUR:
0812     case AFE_DL3_CUR:
0813     case AFE_DL3_END:
0814     case AFE_HDMI_OUT_CON0:
0815     case AFE_HDMI_OUT_CUR:
0816     case AFE_HDMI_OUT_END:
0817     case AFE_IRQ3_MCU_CNT_MON:
0818     case AFE_IRQ4_MCU_CNT_MON:
0819     case AFE_IRQ_MCU_STATUS:
0820     case AFE_IRQ_MCU_CLR:
0821     case AFE_IRQ_MCU_MON2:
0822     case AFE_IRQ1_MCU_CNT_MON:
0823     case AFE_IRQ2_MCU_CNT_MON:
0824     case AFE_IRQ1_MCU_EN_CNT_MON:
0825     case AFE_IRQ5_MCU_CNT_MON:
0826     case AFE_IRQ7_MCU_CNT_MON:
0827     case AFE_GAIN1_CUR:
0828     case AFE_GAIN2_CUR:
0829     case AFE_SRAM_DELSEL_CON0:
0830     case AFE_SRAM_DELSEL_CON2:
0831     case AFE_SRAM_DELSEL_CON3:
0832     case AFE_ASRC_2CH_CON12:
0833     case AFE_ASRC_2CH_CON13:
0834     case PCM_INTF_CON2:
0835     case FPGA_CFG0:
0836     case FPGA_CFG1:
0837     case FPGA_CFG2:
0838     case FPGA_CFG3:
0839     case AUDIO_TOP_DBG_MON0:
0840     case AUDIO_TOP_DBG_MON1:
0841     case AFE_IRQ8_MCU_CNT_MON:
0842     case AFE_IRQ11_MCU_CNT_MON:
0843     case AFE_IRQ12_MCU_CNT_MON:
0844     case AFE_CBIP_MON0:
0845     case AFE_CBIP_SLV_MUX_MON0:
0846     case AFE_CBIP_SLV_DECODER_MON0:
0847     case AFE_ADDA6_SRC_DEBUG_MON0:
0848     case AFE_ADD6A_UL_SRC_MON0:
0849     case AFE_ADDA6_UL_SRC_MON1:
0850     case AFE_DL1_CUR_MSB:
0851     case AFE_DL2_CUR_MSB:
0852     case AFE_AWB_CUR_MSB:
0853     case AFE_VUL_CUR_MSB:
0854     case AFE_VUL2_CUR_MSB:
0855     case AFE_MOD_DAI_CUR_MSB:
0856     case AFE_VUL_D2_CUR_MSB:
0857     case AFE_DL3_CUR_MSB:
0858     case AFE_HDMI_OUT_CUR_MSB:
0859     case AFE_AWB2_END:
0860     case AFE_AWB2_CUR:
0861     case AFE_AWB2_CUR_MSB:
0862     case AFE_ADDA_DL_SDM_FIFO_MON:
0863     case AFE_ADDA_DL_SRC_LCH_MON:
0864     case AFE_ADDA_DL_SRC_RCH_MON:
0865     case AFE_ADDA_DL_SDM_OUT_MON:
0866     case AFE_CONNSYS_I2S_MON:
0867     case AFE_ASRC_2CH_CON0:
0868     case AFE_ASRC_2CH_CON2:
0869     case AFE_ASRC_2CH_CON3:
0870     case AFE_ASRC_2CH_CON4:
0871     case AFE_ASRC_2CH_CON5:
0872     case AFE_ASRC_2CH_CON7:
0873     case AFE_ASRC_2CH_CON8:
0874     case AFE_MEMIF_MON12:
0875     case AFE_MEMIF_MON13:
0876     case AFE_MEMIF_MON14:
0877     case AFE_MEMIF_MON15:
0878     case AFE_MEMIF_MON16:
0879     case AFE_MEMIF_MON17:
0880     case AFE_MEMIF_MON18:
0881     case AFE_MEMIF_MON19:
0882     case AFE_MEMIF_MON20:
0883     case AFE_MEMIF_MON21:
0884     case AFE_MEMIF_MON22:
0885     case AFE_MEMIF_MON23:
0886     case AFE_MEMIF_MON24:
0887     case AFE_ADDA_MTKAIF_MON0:
0888     case AFE_ADDA_MTKAIF_MON1:
0889     case AFE_AUD_PAD_TOP:
0890     case AFE_GENERAL1_ASRC_2CH_CON0:
0891     case AFE_GENERAL1_ASRC_2CH_CON2:
0892     case AFE_GENERAL1_ASRC_2CH_CON3:
0893     case AFE_GENERAL1_ASRC_2CH_CON4:
0894     case AFE_GENERAL1_ASRC_2CH_CON5:
0895     case AFE_GENERAL1_ASRC_2CH_CON7:
0896     case AFE_GENERAL1_ASRC_2CH_CON8:
0897     case AFE_GENERAL1_ASRC_2CH_CON12:
0898     case AFE_GENERAL1_ASRC_2CH_CON13:
0899     case AFE_GENERAL2_ASRC_2CH_CON0:
0900     case AFE_GENERAL2_ASRC_2CH_CON2:
0901     case AFE_GENERAL2_ASRC_2CH_CON3:
0902     case AFE_GENERAL2_ASRC_2CH_CON4:
0903     case AFE_GENERAL2_ASRC_2CH_CON5:
0904     case AFE_GENERAL2_ASRC_2CH_CON7:
0905     case AFE_GENERAL2_ASRC_2CH_CON8:
0906     case AFE_GENERAL2_ASRC_2CH_CON12:
0907     case AFE_GENERAL2_ASRC_2CH_CON13:
0908         return true;
0909     default:
0910         return false;
0911     };
0912 }
0913 
0914 static const struct regmap_config mt8183_afe_regmap_config = {
0915     .reg_bits = 32,
0916     .reg_stride = 4,
0917     .val_bits = 32,
0918 
0919     .volatile_reg = mt8183_is_volatile_reg,
0920 
0921     .max_register = AFE_MAX_REGISTER,
0922     .num_reg_defaults_raw = AFE_MAX_REGISTER,
0923 
0924     .cache_type = REGCACHE_FLAT,
0925 };
0926 
0927 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
0928 {
0929     struct mtk_base_afe *afe = dev;
0930     struct mtk_base_afe_irq *irq;
0931     unsigned int status;
0932     unsigned int status_mcu;
0933     unsigned int mcu_en;
0934     int ret;
0935     int i;
0936     irqreturn_t irq_ret = IRQ_HANDLED;
0937 
0938     /* get irq that is sent to MCU */
0939     regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
0940 
0941     ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
0942     /* only care IRQ which is sent to MCU */
0943     status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
0944 
0945     if (ret || status_mcu == 0) {
0946         dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
0947             __func__, ret, status, mcu_en);
0948 
0949         irq_ret = IRQ_NONE;
0950         goto err_irq;
0951     }
0952 
0953     for (i = 0; i < MT8183_MEMIF_NUM; i++) {
0954         struct mtk_base_afe_memif *memif = &afe->memif[i];
0955 
0956         if (!memif->substream)
0957             continue;
0958 
0959         if (memif->irq_usage < 0)
0960             continue;
0961 
0962         irq = &afe->irqs[memif->irq_usage];
0963 
0964         if (status_mcu & (1 << irq->irq_data->irq_en_shift))
0965             snd_pcm_period_elapsed(memif->substream);
0966     }
0967 
0968 err_irq:
0969     /* clear irq */
0970     regmap_write(afe->regmap,
0971              AFE_IRQ_MCU_CLR,
0972              status_mcu);
0973 
0974     return irq_ret;
0975 }
0976 
0977 static int mt8183_afe_runtime_suspend(struct device *dev)
0978 {
0979     struct mtk_base_afe *afe = dev_get_drvdata(dev);
0980     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0981     unsigned int value;
0982     int ret;
0983 
0984     if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
0985         goto skip_regmap;
0986 
0987     /* disable AFE */
0988     regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
0989 
0990     ret = regmap_read_poll_timeout(afe->regmap,
0991                        AFE_DAC_MON,
0992                        value,
0993                        (value & AFE_ON_RETM_MASK_SFT) == 0,
0994                        20,
0995                        1 * 1000 * 1000);
0996     if (ret)
0997         dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
0998 
0999     /* make sure all irq status are cleared, twice intended */
1000     regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1001     regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1002 
1003     /* cache only */
1004     regcache_cache_only(afe->regmap, true);
1005     regcache_mark_dirty(afe->regmap);
1006 
1007 skip_regmap:
1008     return mt8183_afe_disable_clock(afe);
1009 }
1010 
1011 static int mt8183_afe_runtime_resume(struct device *dev)
1012 {
1013     struct mtk_base_afe *afe = dev_get_drvdata(dev);
1014     struct mt8183_afe_private *afe_priv = afe->platform_priv;
1015     int ret;
1016 
1017     ret = mt8183_afe_enable_clock(afe);
1018     if (ret)
1019         return ret;
1020 
1021     if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
1022         goto skip_regmap;
1023 
1024     regcache_cache_only(afe->regmap, false);
1025     regcache_sync(afe->regmap);
1026 
1027     /* enable audio sys DCM for power saving */
1028     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
1029 
1030     /* force cpu use 8_24 format when writing 32bit data */
1031     regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
1032                CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
1033 
1034     /* set all output port to 24bit */
1035     regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
1036     regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
1037 
1038     /* enable AFE */
1039     regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1040 
1041 skip_regmap:
1042     return 0;
1043 }
1044 
1045 static int mt8183_afe_component_probe(struct snd_soc_component *component)
1046 {
1047     return mtk_afe_add_sub_dai_control(component);
1048 }
1049 
1050 static const struct snd_soc_component_driver mt8183_afe_component = {
1051     .name       = AFE_PCM_NAME,
1052     .probe      = mt8183_afe_component_probe,
1053     .pointer    = mtk_afe_pcm_pointer,
1054     .pcm_construct  = mtk_afe_pcm_new,
1055 };
1056 
1057 static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
1058 {
1059     struct mtk_base_afe_dai *dai;
1060 
1061     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1062     if (!dai)
1063         return -ENOMEM;
1064 
1065     list_add(&dai->list, &afe->sub_dais);
1066 
1067     dai->dai_drivers = mt8183_memif_dai_driver;
1068     dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
1069 
1070     dai->dapm_widgets = mt8183_memif_widgets;
1071     dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
1072     dai->dapm_routes = mt8183_memif_routes;
1073     dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
1074     return 0;
1075 }
1076 
1077 typedef int (*dai_register_cb)(struct mtk_base_afe *);
1078 static const dai_register_cb dai_register_cbs[] = {
1079     mt8183_dai_adda_register,
1080     mt8183_dai_i2s_register,
1081     mt8183_dai_pcm_register,
1082     mt8183_dai_tdm_register,
1083     mt8183_dai_hostless_register,
1084     mt8183_dai_memif_register,
1085 };
1086 
1087 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
1088 {
1089     struct mtk_base_afe *afe;
1090     struct mt8183_afe_private *afe_priv;
1091     struct device *dev;
1092     struct reset_control *rstc;
1093     int i, irq_id, ret;
1094 
1095     afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1096     if (!afe)
1097         return -ENOMEM;
1098     platform_set_drvdata(pdev, afe);
1099 
1100     afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1101                       GFP_KERNEL);
1102     if (!afe->platform_priv)
1103         return -ENOMEM;
1104 
1105     afe_priv = afe->platform_priv;
1106     afe->dev = &pdev->dev;
1107     dev = afe->dev;
1108 
1109     /* initial audio related clock */
1110     ret = mt8183_init_clock(afe);
1111     if (ret) {
1112         dev_err(dev, "init clock error\n");
1113         return ret;
1114     }
1115 
1116     pm_runtime_enable(dev);
1117 
1118     /* regmap init */
1119     afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1120     if (IS_ERR(afe->regmap)) {
1121         dev_err(dev, "could not get regmap from parent\n");
1122         ret = PTR_ERR(afe->regmap);
1123         goto err_pm_disable;
1124     }
1125     ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
1126     if (ret) {
1127         dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
1128         goto err_pm_disable;
1129     }
1130 
1131     rstc = devm_reset_control_get(dev, "audiosys");
1132     if (IS_ERR(rstc)) {
1133         ret = PTR_ERR(rstc);
1134         dev_err(dev, "could not get audiosys reset:%d\n", ret);
1135         goto err_pm_disable;
1136     }
1137 
1138     ret = reset_control_reset(rstc);
1139     if (ret) {
1140         dev_err(dev, "failed to trigger audio reset:%d\n", ret);
1141         goto err_pm_disable;
1142     }
1143 
1144     /* enable clock for regcache get default value from hw */
1145     afe_priv->pm_runtime_bypass_reg_ctl = true;
1146     pm_runtime_get_sync(&pdev->dev);
1147 
1148     ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
1149     if (ret) {
1150         dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
1151         goto err_pm_disable;
1152     }
1153 
1154     pm_runtime_put_sync(&pdev->dev);
1155     afe_priv->pm_runtime_bypass_reg_ctl = false;
1156 
1157     regcache_cache_only(afe->regmap, true);
1158     regcache_mark_dirty(afe->regmap);
1159 
1160     /* init memif */
1161     afe->memif_size = MT8183_MEMIF_NUM;
1162     afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1163                   GFP_KERNEL);
1164     if (!afe->memif) {
1165         ret = -ENOMEM;
1166         goto err_pm_disable;
1167     }
1168 
1169     for (i = 0; i < afe->memif_size; i++) {
1170         afe->memif[i].data = &memif_data[i];
1171         afe->memif[i].irq_usage = -1;
1172     }
1173 
1174     afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
1175     afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
1176 
1177     mutex_init(&afe->irq_alloc_lock);
1178 
1179     /* init memif */
1180     /* irq initialize */
1181     afe->irqs_size = MT8183_IRQ_NUM;
1182     afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1183                  GFP_KERNEL);
1184     if (!afe->irqs) {
1185         ret = -ENOMEM;
1186         goto err_pm_disable;
1187     }
1188 
1189     for (i = 0; i < afe->irqs_size; i++)
1190         afe->irqs[i].irq_data = &irq_data[i];
1191 
1192     /* request irq */
1193     irq_id = platform_get_irq(pdev, 0);
1194     if (irq_id < 0) {
1195         ret = irq_id;
1196         goto err_pm_disable;
1197     }
1198 
1199     ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
1200                    IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1201     if (ret) {
1202         dev_err(dev, "could not request_irq for asys-isr\n");
1203         goto err_pm_disable;
1204     }
1205 
1206     /* init sub_dais */
1207     INIT_LIST_HEAD(&afe->sub_dais);
1208 
1209     for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
1210         ret = dai_register_cbs[i](afe);
1211         if (ret) {
1212             dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
1213                  i, ret);
1214             goto err_pm_disable;
1215         }
1216     }
1217 
1218     /* init dai_driver and component_driver */
1219     ret = mtk_afe_combine_sub_dai(afe);
1220     if (ret) {
1221         dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
1222              ret);
1223         goto err_pm_disable;
1224     }
1225 
1226     afe->mtk_afe_hardware = &mt8183_afe_hardware;
1227     afe->memif_fs = mt8183_memif_fs;
1228     afe->irq_fs = mt8183_irq_fs;
1229 
1230     afe->runtime_resume = mt8183_afe_runtime_resume;
1231     afe->runtime_suspend = mt8183_afe_runtime_suspend;
1232 
1233     /* register component */
1234     ret = devm_snd_soc_register_component(&pdev->dev,
1235                           &mt8183_afe_component,
1236                           NULL, 0);
1237     if (ret) {
1238         dev_warn(dev, "err_platform\n");
1239         goto err_pm_disable;
1240     }
1241 
1242     ret = devm_snd_soc_register_component(afe->dev,
1243                           &mt8183_afe_pcm_dai_component,
1244                           afe->dai_drivers,
1245                           afe->num_dai_drivers);
1246     if (ret) {
1247         dev_warn(dev, "err_dai_component\n");
1248         goto err_pm_disable;
1249     }
1250 
1251     return ret;
1252 
1253 err_pm_disable:
1254     pm_runtime_disable(&pdev->dev);
1255     return ret;
1256 }
1257 
1258 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
1259 {
1260     pm_runtime_disable(&pdev->dev);
1261     if (!pm_runtime_status_suspended(&pdev->dev))
1262         mt8183_afe_runtime_suspend(&pdev->dev);
1263 
1264     return 0;
1265 }
1266 
1267 static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
1268     { .compatible = "mediatek,mt8183-audio", },
1269     {},
1270 };
1271 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
1272 
1273 static const struct dev_pm_ops mt8183_afe_pm_ops = {
1274     SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
1275                mt8183_afe_runtime_resume, NULL)
1276 };
1277 
1278 static struct platform_driver mt8183_afe_pcm_driver = {
1279     .driver = {
1280            .name = "mt8183-audio",
1281            .of_match_table = mt8183_afe_pcm_dt_match,
1282            .pm = &mt8183_afe_pm_ops,
1283     },
1284     .probe = mt8183_afe_pcm_dev_probe,
1285     .remove = mt8183_afe_pcm_dev_remove,
1286 };
1287 
1288 module_platform_driver(mt8183_afe_pcm_driver);
1289 
1290 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
1291 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1292 MODULE_LICENSE("GPL v2");
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