mediatek/mt8183/mt8183-afe-common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt8183-afe-common.h  --  Mediatek 8183 audio driver definitions
0004  *
0005  * Copyright (c) 2018 MediaTek Inc.
0006  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007  */
0008
0009 #ifndef _MT_8183_AFE_COMMON_H_
0010 #define _MT_8183_AFE_COMMON_H_
0011
0012 #include <sound/soc.h>
0013 #include <linux/list.h>
0014 #include <linux/regmap.h>
0015 #include "../common/mtk-base-afe.h"
0016
0017 enum {
0018     MT8183_MEMIF_DL1,
0019     MT8183_MEMIF_DL2,
0020     MT8183_MEMIF_DL3,
0021     MT8183_MEMIF_VUL12,
0022     MT8183_MEMIF_VUL2,
0023     MT8183_MEMIF_AWB,
0024     MT8183_MEMIF_AWB2,
0025     MT8183_MEMIF_MOD_DAI,
0026     MT8183_MEMIF_HDMI,
0027     MT8183_MEMIF_NUM,
0028     MT8183_DAI_ADDA = MT8183_MEMIF_NUM,
0029     MT8183_DAI_PCM_1,
0030     MT8183_DAI_PCM_2,
0031     MT8183_DAI_I2S_0,
0032     MT8183_DAI_I2S_1,
0033     MT8183_DAI_I2S_2,
0034     MT8183_DAI_I2S_3,
0035     MT8183_DAI_I2S_5,
0036     MT8183_DAI_TDM,
0037     MT8183_DAI_HOSTLESS_LPBK,
0038     MT8183_DAI_HOSTLESS_SPEECH,
0039     MT8183_DAI_NUM,
0040 };
0041
0042 enum {
0043     MT8183_IRQ_0,
0044     MT8183_IRQ_1,
0045     MT8183_IRQ_2,
0046     MT8183_IRQ_3,
0047     MT8183_IRQ_4,
0048     MT8183_IRQ_5,
0049     MT8183_IRQ_6,
0050     MT8183_IRQ_7,
0051     MT8183_IRQ_8,   /* hw bundle to TDM */
0052     MT8183_IRQ_11,
0053     MT8183_IRQ_12,
0054     MT8183_IRQ_NUM,
0055 };
0056
0057 enum {
0058     MT8183_MTKAIF_PROTOCOL_1 = 0,
0059     MT8183_MTKAIF_PROTOCOL_2,
0060     MT8183_MTKAIF_PROTOCOL_2_CLK_P2,
0061 };
0062
0063 /* MCLK */
0064 enum {
0065     MT8183_I2S0_MCK = 0,
0066     MT8183_I2S1_MCK,
0067     MT8183_I2S2_MCK,
0068     MT8183_I2S3_MCK,
0069     MT8183_I2S4_MCK,
0070     MT8183_I2S4_BCK,
0071     MT8183_I2S5_MCK,
0072     MT8183_MCK_NUM,
0073 };
0074
0075 struct clk;
0076
0077 struct mt8183_afe_private {
0078     struct clk **clk;
0079
0080     int pm_runtime_bypass_reg_ctl;
0081
0082     /* dai */
0083     void *dai_priv[MT8183_DAI_NUM];
0084
0085     /* adda */
0086     int mtkaif_protocol;
0087     int mtkaif_calibration_ok;
0088     int mtkaif_chosen_phase[4];
0089     int mtkaif_phase_cycle[4];
0090     int mtkaif_calibration_num_phase;
0091     int mtkaif_dmic;
0092
0093     /* mck */
0094     int mck_rate[MT8183_MCK_NUM];
0095 };
0096
0097 unsigned int mt8183_general_rate_transform(struct device *dev,
0098                        unsigned int rate);
0099 unsigned int mt8183_rate_transform(struct device *dev,
0100                    unsigned int rate, int aud_blk);
0101
0102 /* dai register */
0103 int mt8183_dai_adda_register(struct mtk_base_afe *afe);
0104 int mt8183_dai_pcm_register(struct mtk_base_afe *afe);
0105 int mt8183_dai_i2s_register(struct mtk_base_afe *afe);
0106 int mt8183_dai_tdm_register(struct mtk_base_afe *afe);
0107 int mt8183_dai_hostless_register(struct mtk_base_afe *afe);
0108 #endif