mediatek/mt8183/mt8183-afe-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt8183-afe-clk.h  --  Mediatek 8183 afe clock ctrl definition
0004  *
0005  * Copyright (c) 2018 MediaTek Inc.
0006  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007  */
0008
0009 #ifndef _MT8183_AFE_CLK_H_
0010 #define _MT8183_AFE_CLK_H_
0011
0012 /* APLL */
0013 #define APLL1_W_NAME "APLL1"
0014 #define APLL2_W_NAME "APLL2"
0015 enum {
0016     MT8183_APLL1 = 0,
0017     MT8183_APLL2,
0018 };
0019
0020 struct mtk_base_afe;
0021
0022 int mt8183_init_clock(struct mtk_base_afe *afe);
0023 int mt8183_afe_enable_clock(struct mtk_base_afe *afe);
0024 int mt8183_afe_disable_clock(struct mtk_base_afe *afe);
0025
0026 int mt8183_apll1_enable(struct mtk_base_afe *afe);
0027 void mt8183_apll1_disable(struct mtk_base_afe *afe);
0028
0029 int mt8183_apll2_enable(struct mtk_base_afe *afe);
0030 void mt8183_apll2_disable(struct mtk_base_afe *afe);
0031
0032 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
0033 int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
0034 int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
0035
0036 int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
0037 void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id);
0038 #endif