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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt8183-afe-clk.c  --  Mediatek 8183 afe clock ctrl
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007 
0008 #include <linux/clk.h>
0009 
0010 #include "mt8183-afe-common.h"
0011 #include "mt8183-afe-clk.h"
0012 #include "mt8183-reg.h"
0013 
0014 enum {
0015     CLK_AFE = 0,
0016     CLK_TML,
0017     CLK_APLL22M,
0018     CLK_APLL24M,
0019     CLK_APLL1_TUNER,
0020     CLK_APLL2_TUNER,
0021     CLK_I2S1_BCLK_SW,
0022     CLK_I2S2_BCLK_SW,
0023     CLK_I2S3_BCLK_SW,
0024     CLK_I2S4_BCLK_SW,
0025     CLK_INFRA_SYS_AUDIO,
0026     CLK_MUX_AUDIO,
0027     CLK_MUX_AUDIOINTBUS,
0028     CLK_TOP_SYSPLL_D2_D4,
0029     /* apll related mux */
0030     CLK_TOP_MUX_AUD_1,
0031     CLK_TOP_APLL1_CK,
0032     CLK_TOP_MUX_AUD_2,
0033     CLK_TOP_APLL2_CK,
0034     CLK_TOP_MUX_AUD_ENG1,
0035     CLK_TOP_APLL1_D8,
0036     CLK_TOP_MUX_AUD_ENG2,
0037     CLK_TOP_APLL2_D8,
0038     CLK_TOP_I2S0_M_SEL,
0039     CLK_TOP_I2S1_M_SEL,
0040     CLK_TOP_I2S2_M_SEL,
0041     CLK_TOP_I2S3_M_SEL,
0042     CLK_TOP_I2S4_M_SEL,
0043     CLK_TOP_I2S5_M_SEL,
0044     CLK_TOP_APLL12_DIV0,
0045     CLK_TOP_APLL12_DIV1,
0046     CLK_TOP_APLL12_DIV2,
0047     CLK_TOP_APLL12_DIV3,
0048     CLK_TOP_APLL12_DIV4,
0049     CLK_TOP_APLL12_DIVB,
0050     CLK_CLK26M,
0051     CLK_NUM
0052 };
0053 
0054 static const char *aud_clks[CLK_NUM] = {
0055     [CLK_AFE] = "aud_afe_clk",
0056     [CLK_TML] = "aud_tml_clk",
0057     [CLK_APLL22M] = "aud_apll22m_clk",
0058     [CLK_APLL24M] = "aud_apll24m_clk",
0059     [CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
0060     [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
0061     [CLK_I2S1_BCLK_SW] = "aud_i2s1_bclk_sw",
0062     [CLK_I2S2_BCLK_SW] = "aud_i2s2_bclk_sw",
0063     [CLK_I2S3_BCLK_SW] = "aud_i2s3_bclk_sw",
0064     [CLK_I2S4_BCLK_SW] = "aud_i2s4_bclk_sw",
0065     [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
0066     [CLK_MUX_AUDIO] = "top_mux_audio",
0067     [CLK_MUX_AUDIOINTBUS] = "top_mux_aud_intbus",
0068     [CLK_TOP_SYSPLL_D2_D4] = "top_syspll_d2_d4",
0069     [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
0070     [CLK_TOP_APLL1_CK] = "top_apll1_ck",
0071     [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
0072     [CLK_TOP_APLL2_CK] = "top_apll2_ck",
0073     [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
0074     [CLK_TOP_APLL1_D8] = "top_apll1_d8",
0075     [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
0076     [CLK_TOP_APLL2_D8] = "top_apll2_d8",
0077     [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
0078     [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
0079     [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
0080     [CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
0081     [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
0082     [CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
0083     [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
0084     [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
0085     [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
0086     [CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
0087     [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
0088     [CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
0089     [CLK_CLK26M] = "top_clk26m_clk",
0090 };
0091 
0092 int mt8183_init_clock(struct mtk_base_afe *afe)
0093 {
0094     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0095     int i;
0096 
0097     afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
0098                      GFP_KERNEL);
0099     if (!afe_priv->clk)
0100         return -ENOMEM;
0101 
0102     for (i = 0; i < CLK_NUM; i++) {
0103         afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
0104         if (IS_ERR(afe_priv->clk[i])) {
0105             dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
0106                 __func__, aud_clks[i],
0107                 PTR_ERR(afe_priv->clk[i]));
0108             return PTR_ERR(afe_priv->clk[i]);
0109         }
0110     }
0111 
0112     return 0;
0113 }
0114 
0115 int mt8183_afe_enable_clock(struct mtk_base_afe *afe)
0116 {
0117     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0118     int ret;
0119 
0120     ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0121     if (ret) {
0122         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0123             __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
0124         goto CLK_INFRA_SYS_AUDIO_ERR;
0125     }
0126 
0127     ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
0128     if (ret) {
0129         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0130             __func__, aud_clks[CLK_MUX_AUDIO], ret);
0131         goto CLK_MUX_AUDIO_ERR;
0132     }
0133 
0134     ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
0135                  afe_priv->clk[CLK_CLK26M]);
0136     if (ret) {
0137         dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
0138             __func__, aud_clks[CLK_MUX_AUDIO],
0139             aud_clks[CLK_CLK26M], ret);
0140         goto CLK_MUX_AUDIO_ERR;
0141     }
0142 
0143     ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0144     if (ret) {
0145         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0146             __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
0147         goto CLK_MUX_AUDIO_INTBUS_ERR;
0148     }
0149 
0150     ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
0151                  afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]);
0152     if (ret) {
0153         dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
0154             __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
0155             aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);
0156         goto CLK_MUX_AUDIO_INTBUS_ERR;
0157     }
0158 
0159     ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
0160     if (ret) {
0161         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0162             __func__, aud_clks[CLK_AFE], ret);
0163         goto CLK_AFE_ERR;
0164     }
0165 
0166     ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
0167     if (ret) {
0168         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0169             __func__, aud_clks[CLK_I2S1_BCLK_SW], ret);
0170         goto CLK_I2S1_BCLK_SW_ERR;
0171     }
0172 
0173     ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
0174     if (ret) {
0175         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0176             __func__, aud_clks[CLK_I2S2_BCLK_SW], ret);
0177         goto CLK_I2S2_BCLK_SW_ERR;
0178     }
0179 
0180     ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
0181     if (ret) {
0182         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0183             __func__, aud_clks[CLK_I2S3_BCLK_SW], ret);
0184         goto CLK_I2S3_BCLK_SW_ERR;
0185     }
0186 
0187     ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
0188     if (ret) {
0189         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0190             __func__, aud_clks[CLK_I2S4_BCLK_SW], ret);
0191         goto CLK_I2S4_BCLK_SW_ERR;
0192     }
0193 
0194     return 0;
0195 
0196 CLK_I2S4_BCLK_SW_ERR:
0197     clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
0198 CLK_I2S3_BCLK_SW_ERR:
0199     clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
0200 CLK_I2S2_BCLK_SW_ERR:
0201     clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
0202 CLK_I2S1_BCLK_SW_ERR:
0203     clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
0204 CLK_AFE_ERR:
0205     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0206 CLK_MUX_AUDIO_INTBUS_ERR:
0207     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
0208 CLK_MUX_AUDIO_ERR:
0209     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0210 CLK_INFRA_SYS_AUDIO_ERR:
0211     return ret;
0212 }
0213 
0214 int mt8183_afe_disable_clock(struct mtk_base_afe *afe)
0215 {
0216     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0217 
0218     clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]);
0219     clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
0220     clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
0221     clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
0222     clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
0223     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
0224     clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
0225     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
0226 
0227     return 0;
0228 }
0229 
0230 /* apll */
0231 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
0232 {
0233     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0234     int ret;
0235 
0236     if (enable) {
0237         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0238         if (ret) {
0239             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0240                 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
0241             goto ERR_ENABLE_CLK_TOP_MUX_AUD_1;
0242         }
0243         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0244                      afe_priv->clk[CLK_TOP_APLL1_CK]);
0245         if (ret) {
0246             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0247                 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
0248                 aud_clks[CLK_TOP_APLL1_CK], ret);
0249             goto ERR_SELECT_CLK_TOP_MUX_AUD_1;
0250         }
0251 
0252         /* 180.6336 / 8 = 22.5792MHz */
0253         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0254         if (ret) {
0255             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0256                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
0257             goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1;
0258         }
0259         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0260                      afe_priv->clk[CLK_TOP_APLL1_D8]);
0261         if (ret) {
0262             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0263                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
0264                 aud_clks[CLK_TOP_APLL1_D8], ret);
0265             goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
0266         }
0267     } else {
0268         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0269                      afe_priv->clk[CLK_CLK26M]);
0270         if (ret) {
0271             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0272                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
0273                 aud_clks[CLK_CLK26M], ret);
0274             goto EXIT;
0275         }
0276         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0277 
0278         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0279                      afe_priv->clk[CLK_CLK26M]);
0280         if (ret) {
0281             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0282                 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
0283                 aud_clks[CLK_CLK26M], ret);
0284             goto EXIT;
0285         }
0286         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0287     }
0288 
0289     return 0;
0290 
0291 ERR_SELECT_CLK_TOP_MUX_AUD_ENG1:
0292     clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
0293                afe_priv->clk[CLK_CLK26M]);
0294     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
0295 ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1:
0296 ERR_SELECT_CLK_TOP_MUX_AUD_1:
0297     clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
0298                afe_priv->clk[CLK_CLK26M]);
0299     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
0300 ERR_ENABLE_CLK_TOP_MUX_AUD_1:
0301 EXIT:
0302     return ret;
0303 }
0304 
0305 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
0306 {
0307     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0308     int ret;
0309 
0310     if (enable) {
0311         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0312         if (ret) {
0313             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0314                 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
0315             goto ERR_ENABLE_CLK_TOP_MUX_AUD_2;
0316         }
0317         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0318                      afe_priv->clk[CLK_TOP_APLL2_CK]);
0319         if (ret) {
0320             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0321                 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
0322                 aud_clks[CLK_TOP_APLL2_CK], ret);
0323             goto ERR_SELECT_CLK_TOP_MUX_AUD_2;
0324         }
0325 
0326         /* 196.608 / 8 = 24.576MHz */
0327         ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0328         if (ret) {
0329             dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0330                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
0331             goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2;
0332         }
0333         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0334                      afe_priv->clk[CLK_TOP_APLL2_D8]);
0335         if (ret) {
0336             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0337                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
0338                 aud_clks[CLK_TOP_APLL2_D8], ret);
0339             goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
0340         }
0341     } else {
0342         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0343                      afe_priv->clk[CLK_CLK26M]);
0344         if (ret) {
0345             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0346                 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
0347                 aud_clks[CLK_CLK26M], ret);
0348             goto EXIT;
0349         }
0350         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0351 
0352         ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0353                      afe_priv->clk[CLK_CLK26M]);
0354         if (ret) {
0355             dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
0356                 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
0357                 aud_clks[CLK_CLK26M], ret);
0358             goto EXIT;
0359         }
0360         clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0361     }
0362 
0363     return 0;
0364 
0365 ERR_SELECT_CLK_TOP_MUX_AUD_ENG2:
0366     clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
0367                afe_priv->clk[CLK_CLK26M]);
0368     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
0369 ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2:
0370 ERR_SELECT_CLK_TOP_MUX_AUD_2:
0371     clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
0372                afe_priv->clk[CLK_CLK26M]);
0373     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
0374 ERR_ENABLE_CLK_TOP_MUX_AUD_2:
0375 EXIT:
0376     return ret;
0377 }
0378 
0379 int mt8183_apll1_enable(struct mtk_base_afe *afe)
0380 {
0381     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0382     int ret;
0383 
0384     /* setting for APLL */
0385     apll1_mux_setting(afe, true);
0386 
0387     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
0388     if (ret) {
0389         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0390             __func__, aud_clks[CLK_APLL22M], ret);
0391         goto ERR_CLK_APLL22M;
0392     }
0393 
0394     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
0395     if (ret) {
0396         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0397             __func__, aud_clks[CLK_APLL1_TUNER], ret);
0398         goto ERR_CLK_APLL1_TUNER;
0399     }
0400 
0401     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
0402                0x0000FFF7, 0x00000832);
0403     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
0404 
0405     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0406                AFE_22M_ON_MASK_SFT,
0407                0x1 << AFE_22M_ON_SFT);
0408 
0409     return 0;
0410 
0411 ERR_CLK_APLL1_TUNER:
0412     clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
0413 ERR_CLK_APLL22M:
0414     return ret;
0415 }
0416 
0417 void mt8183_apll1_disable(struct mtk_base_afe *afe)
0418 {
0419     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0420 
0421     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0422                AFE_22M_ON_MASK_SFT,
0423                0x0 << AFE_22M_ON_SFT);
0424 
0425     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
0426 
0427     clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
0428     clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
0429 
0430     apll1_mux_setting(afe, false);
0431 }
0432 
0433 int mt8183_apll2_enable(struct mtk_base_afe *afe)
0434 {
0435     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0436     int ret;
0437 
0438     /* setting for APLL */
0439     apll2_mux_setting(afe, true);
0440 
0441     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
0442     if (ret) {
0443         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0444             __func__, aud_clks[CLK_APLL24M], ret);
0445         goto ERR_CLK_APLL24M;
0446     }
0447 
0448     ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
0449     if (ret) {
0450         dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
0451             __func__, aud_clks[CLK_APLL2_TUNER], ret);
0452         goto ERR_CLK_APLL2_TUNER;
0453     }
0454 
0455     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
0456                0x0000FFF7, 0x00000634);
0457     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
0458 
0459     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0460                AFE_24M_ON_MASK_SFT,
0461                0x1 << AFE_24M_ON_SFT);
0462 
0463     return 0;
0464 
0465 ERR_CLK_APLL2_TUNER:
0466     clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
0467 ERR_CLK_APLL24M:
0468     return ret;
0469 }
0470 
0471 void mt8183_apll2_disable(struct mtk_base_afe *afe)
0472 {
0473     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0474 
0475     regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
0476                AFE_24M_ON_MASK_SFT,
0477                0x0 << AFE_24M_ON_SFT);
0478 
0479     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
0480 
0481     clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
0482     clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
0483 
0484     apll2_mux_setting(afe, false);
0485 }
0486 
0487 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll)
0488 {
0489     return (apll == MT8183_APLL1) ? 180633600 : 196608000;
0490 }
0491 
0492 int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
0493 {
0494     return ((rate % 8000) == 0) ? MT8183_APLL2 : MT8183_APLL1;
0495 }
0496 
0497 int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
0498 {
0499     if (strcmp(name, APLL1_W_NAME) == 0)
0500         return MT8183_APLL1;
0501     else
0502         return MT8183_APLL2;
0503 }
0504 
0505 /* mck */
0506 struct mt8183_mck_div {
0507     int m_sel_id;
0508     int div_clk_id;
0509 };
0510 
0511 static const struct mt8183_mck_div mck_div[MT8183_MCK_NUM] = {
0512     [MT8183_I2S0_MCK] = {
0513         .m_sel_id = CLK_TOP_I2S0_M_SEL,
0514         .div_clk_id = CLK_TOP_APLL12_DIV0,
0515     },
0516     [MT8183_I2S1_MCK] = {
0517         .m_sel_id = CLK_TOP_I2S1_M_SEL,
0518         .div_clk_id = CLK_TOP_APLL12_DIV1,
0519     },
0520     [MT8183_I2S2_MCK] = {
0521         .m_sel_id = CLK_TOP_I2S2_M_SEL,
0522         .div_clk_id = CLK_TOP_APLL12_DIV2,
0523     },
0524     [MT8183_I2S3_MCK] = {
0525         .m_sel_id = CLK_TOP_I2S3_M_SEL,
0526         .div_clk_id = CLK_TOP_APLL12_DIV3,
0527     },
0528     [MT8183_I2S4_MCK] = {
0529         .m_sel_id = CLK_TOP_I2S4_M_SEL,
0530         .div_clk_id = CLK_TOP_APLL12_DIV4,
0531     },
0532     [MT8183_I2S4_BCK] = {
0533         .m_sel_id = -1,
0534         .div_clk_id = CLK_TOP_APLL12_DIVB,
0535     },
0536     [MT8183_I2S5_MCK] = {
0537         .m_sel_id = -1,
0538         .div_clk_id = -1,
0539     },
0540 };
0541 
0542 int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
0543 {
0544     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0545     int apll = mt8183_get_apll_by_rate(afe, rate);
0546     int apll_clk_id = apll == MT8183_APLL1 ?
0547               CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
0548     int m_sel_id = mck_div[mck_id].m_sel_id;
0549     int div_clk_id = mck_div[mck_id].div_clk_id;
0550     int ret;
0551 
0552     /* i2s5 mck not support */
0553     if (mck_id == MT8183_I2S5_MCK)
0554         return 0;
0555 
0556     /* select apll */
0557     if (m_sel_id >= 0) {
0558         ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
0559         if (ret) {
0560             dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0561                 __func__, aud_clks[m_sel_id], ret);
0562             goto ERR_ENABLE_MCLK;
0563         }
0564         ret = clk_set_parent(afe_priv->clk[m_sel_id],
0565                      afe_priv->clk[apll_clk_id]);
0566         if (ret) {
0567             dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
0568                 __func__, aud_clks[m_sel_id],
0569                 aud_clks[apll_clk_id], ret);
0570             goto ERR_SELECT_MCLK;
0571         }
0572     }
0573 
0574     /* enable div, set rate */
0575     ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
0576     if (ret) {
0577         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0578             __func__, aud_clks[div_clk_id], ret);
0579         goto ERR_ENABLE_MCLK_DIV;
0580     }
0581     ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
0582     if (ret) {
0583         dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
0584             __func__, aud_clks[div_clk_id],
0585             rate, ret);
0586         goto ERR_SET_MCLK_RATE;
0587     }
0588 
0589     return 0;
0590 
0591 ERR_SET_MCLK_RATE:
0592     clk_disable_unprepare(afe_priv->clk[div_clk_id]);
0593 ERR_ENABLE_MCLK_DIV:
0594 ERR_SELECT_MCLK:
0595     if (m_sel_id >= 0)
0596         clk_disable_unprepare(afe_priv->clk[m_sel_id]);
0597 ERR_ENABLE_MCLK:
0598     return ret;
0599 }
0600 
0601 void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id)
0602 {
0603     struct mt8183_afe_private *afe_priv = afe->platform_priv;
0604     int m_sel_id = mck_div[mck_id].m_sel_id;
0605     int div_clk_id = mck_div[mck_id].div_clk_id;
0606 
0607     /* i2s5 mck not support */
0608     if (mck_id == MT8183_I2S5_MCK)
0609         return;
0610 
0611     clk_disable_unprepare(afe_priv->clk[div_clk_id]);
0612     if (m_sel_id >= 0)
0613         clk_disable_unprepare(afe_priv->clk[m_sel_id]);
0614 }
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