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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Mediatek 8173 ALSA SoC AFE platform driver
0004  *
0005  * Copyright (c) 2015 MediaTek Inc.
0006  * Author: Koro Chen <koro.chen@mediatek.com>
0007  *             Sascha Hauer <s.hauer@pengutronix.de>
0008  *             Hidalgo Huang <hidalgo.huang@mediatek.com>
0009  *             Ir Lian <ir.lian@mediatek.com>
0010  */
0011 
0012 #include <linux/delay.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/pm_runtime.h>
0018 #include <sound/soc.h>
0019 #include "mt8173-afe-common.h"
0020 #include "../common/mtk-base-afe.h"
0021 #include "../common/mtk-afe-platform-driver.h"
0022 #include "../common/mtk-afe-fe-dai.h"
0023 
0024 /*****************************************************************************
0025  *                  R E G I S T E R       D E F I N I T I O N
0026  *****************************************************************************/
0027 #define AUDIO_TOP_CON0      0x0000
0028 #define AUDIO_TOP_CON1      0x0004
0029 #define AFE_DAC_CON0        0x0010
0030 #define AFE_DAC_CON1        0x0014
0031 #define AFE_I2S_CON1        0x0034
0032 #define AFE_I2S_CON2        0x0038
0033 #define AFE_CONN_24BIT      0x006c
0034 #define AFE_MEMIF_MSB       0x00cc
0035 
0036 #define AFE_CONN1       0x0024
0037 #define AFE_CONN2       0x0028
0038 #define AFE_CONN3       0x002c
0039 #define AFE_CONN7       0x0460
0040 #define AFE_CONN8       0x0464
0041 #define AFE_HDMI_CONN0      0x0390
0042 
0043 /* Memory interface */
0044 #define AFE_DL1_BASE        0x0040
0045 #define AFE_DL1_CUR     0x0044
0046 #define AFE_DL1_END     0x0048
0047 #define AFE_DL2_BASE        0x0050
0048 #define AFE_DL2_CUR     0x0054
0049 #define AFE_AWB_BASE        0x0070
0050 #define AFE_AWB_CUR     0x007c
0051 #define AFE_VUL_BASE        0x0080
0052 #define AFE_VUL_CUR     0x008c
0053 #define AFE_VUL_END     0x0088
0054 #define AFE_DAI_BASE        0x0090
0055 #define AFE_DAI_CUR     0x009c
0056 #define AFE_MOD_PCM_BASE    0x0330
0057 #define AFE_MOD_PCM_CUR     0x033c
0058 #define AFE_HDMI_OUT_BASE   0x0374
0059 #define AFE_HDMI_OUT_CUR    0x0378
0060 #define AFE_HDMI_OUT_END    0x037c
0061 
0062 #define AFE_ADDA_TOP_CON0   0x0120
0063 #define AFE_ADDA2_TOP_CON0  0x0600
0064 
0065 #define AFE_HDMI_OUT_CON0   0x0370
0066 
0067 #define AFE_IRQ_MCU_CON     0x03a0
0068 #define AFE_IRQ_STATUS      0x03a4
0069 #define AFE_IRQ_CLR     0x03a8
0070 #define AFE_IRQ_CNT1        0x03ac
0071 #define AFE_IRQ_CNT2        0x03b0
0072 #define AFE_IRQ_MCU_EN      0x03b4
0073 #define AFE_IRQ_CNT5        0x03bc
0074 #define AFE_IRQ_CNT7        0x03dc
0075 
0076 #define AFE_TDM_CON1        0x0548
0077 #define AFE_TDM_CON2        0x054c
0078 
0079 #define AFE_IRQ_STATUS_BITS 0xff
0080 
0081 /* AUDIO_TOP_CON0 (0x0000) */
0082 #define AUD_TCON0_PDN_SPDF      (0x1 << 21)
0083 #define AUD_TCON0_PDN_HDMI      (0x1 << 20)
0084 #define AUD_TCON0_PDN_24M       (0x1 << 9)
0085 #define AUD_TCON0_PDN_22M       (0x1 << 8)
0086 #define AUD_TCON0_PDN_AFE       (0x1 << 2)
0087 
0088 /* AFE_I2S_CON1 (0x0034) */
0089 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
0090 #define AFE_I2S_CON1_RATE(x)        (((x) & 0xf) << 8)
0091 #define AFE_I2S_CON1_FORMAT_I2S     (0x1 << 3)
0092 #define AFE_I2S_CON1_EN         (0x1 << 0)
0093 
0094 /* AFE_I2S_CON2 (0x0038) */
0095 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
0096 #define AFE_I2S_CON2_RATE(x)        (((x) & 0xf) << 8)
0097 #define AFE_I2S_CON2_FORMAT_I2S     (0x1 << 3)
0098 #define AFE_I2S_CON2_EN         (0x1 << 0)
0099 
0100 /* AFE_CONN_24BIT (0x006c) */
0101 #define AFE_CONN_24BIT_O04      (0x1 << 4)
0102 #define AFE_CONN_24BIT_O03      (0x1 << 3)
0103 
0104 /* AFE_HDMI_CONN0 (0x0390) */
0105 #define AFE_HDMI_CONN0_O37_I37      (0x7 << 21)
0106 #define AFE_HDMI_CONN0_O36_I36      (0x6 << 18)
0107 #define AFE_HDMI_CONN0_O35_I33      (0x3 << 15)
0108 #define AFE_HDMI_CONN0_O34_I32      (0x2 << 12)
0109 #define AFE_HDMI_CONN0_O33_I35      (0x5 << 9)
0110 #define AFE_HDMI_CONN0_O32_I34      (0x4 << 6)
0111 #define AFE_HDMI_CONN0_O31_I31      (0x1 << 3)
0112 #define AFE_HDMI_CONN0_O30_I30      (0x0 << 0)
0113 
0114 /* AFE_TDM_CON1 (0x0548) */
0115 #define AFE_TDM_CON1_LRCK_WIDTH(x)  (((x) - 1) << 24)
0116 #define AFE_TDM_CON1_32_BCK_CYCLES  (0x2 << 12)
0117 #define AFE_TDM_CON1_WLEN_32BIT     (0x2 << 8)
0118 #define AFE_TDM_CON1_MSB_ALIGNED    (0x1 << 4)
0119 #define AFE_TDM_CON1_1_BCK_DELAY    (0x1 << 3)
0120 #define AFE_TDM_CON1_LRCK_INV       (0x1 << 2)
0121 #define AFE_TDM_CON1_BCK_INV        (0x1 << 1)
0122 #define AFE_TDM_CON1_EN         (0x1 << 0)
0123 
0124 enum afe_tdm_ch_start {
0125     AFE_TDM_CH_START_O30_O31 = 0,
0126     AFE_TDM_CH_START_O32_O33,
0127     AFE_TDM_CH_START_O34_O35,
0128     AFE_TDM_CH_START_O36_O37,
0129     AFE_TDM_CH_ZERO,
0130 };
0131 
0132 static const unsigned int mt8173_afe_backup_list[] = {
0133     AUDIO_TOP_CON0,
0134     AFE_CONN1,
0135     AFE_CONN2,
0136     AFE_CONN7,
0137     AFE_CONN8,
0138     AFE_DAC_CON1,
0139     AFE_DL1_BASE,
0140     AFE_DL1_END,
0141     AFE_VUL_BASE,
0142     AFE_VUL_END,
0143     AFE_HDMI_OUT_BASE,
0144     AFE_HDMI_OUT_END,
0145     AFE_HDMI_CONN0,
0146     AFE_DAC_CON0,
0147 };
0148 
0149 struct mt8173_afe_private {
0150     struct clk *clocks[MT8173_CLK_NUM];
0151 };
0152 
0153 static const struct snd_pcm_hardware mt8173_afe_hardware = {
0154     .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
0155          SNDRV_PCM_INFO_MMAP_VALID),
0156     .buffer_bytes_max = 256 * 1024,
0157     .period_bytes_min = 512,
0158     .period_bytes_max = 128 * 1024,
0159     .periods_min = 2,
0160     .periods_max = 256,
0161     .fifo_size = 0,
0162 };
0163 
0164 struct mt8173_afe_rate {
0165     unsigned int rate;
0166     unsigned int regvalue;
0167 };
0168 
0169 static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
0170     { .rate = 8000, .regvalue = 0 },
0171     { .rate = 11025, .regvalue = 1 },
0172     { .rate = 12000, .regvalue = 2 },
0173     { .rate = 16000, .regvalue = 4 },
0174     { .rate = 22050, .regvalue = 5 },
0175     { .rate = 24000, .regvalue = 6 },
0176     { .rate = 32000, .regvalue = 8 },
0177     { .rate = 44100, .regvalue = 9 },
0178     { .rate = 48000, .regvalue = 10 },
0179     { .rate = 88000, .regvalue = 11 },
0180     { .rate = 96000, .regvalue = 12 },
0181     { .rate = 174000, .regvalue = 13 },
0182     { .rate = 192000, .regvalue = 14 },
0183 };
0184 
0185 static int mt8173_afe_i2s_fs(unsigned int sample_rate)
0186 {
0187     int i;
0188 
0189     for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
0190         if (mt8173_afe_i2s_rates[i].rate == sample_rate)
0191             return mt8173_afe_i2s_rates[i].regvalue;
0192 
0193     return -EINVAL;
0194 }
0195 
0196 static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
0197 {
0198     unsigned int val;
0199     int fs = mt8173_afe_i2s_fs(rate);
0200 
0201     if (fs < 0)
0202         return -EINVAL;
0203 
0204     /* from external ADC */
0205     regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
0206     regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
0207 
0208     /* set input */
0209     val = AFE_I2S_CON2_LOW_JITTER_CLK |
0210           AFE_I2S_CON2_RATE(fs) |
0211           AFE_I2S_CON2_FORMAT_I2S;
0212 
0213     regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
0214 
0215     /* set output */
0216     val = AFE_I2S_CON1_LOW_JITTER_CLK |
0217           AFE_I2S_CON1_RATE(fs) |
0218           AFE_I2S_CON1_FORMAT_I2S;
0219 
0220     regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
0221     return 0;
0222 }
0223 
0224 static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
0225 {
0226     unsigned int val;
0227 
0228     regmap_read(afe->regmap, AFE_I2S_CON2, &val);
0229     if (!!(val & AFE_I2S_CON2_EN) == enable)
0230         return;
0231 
0232     /* input */
0233     regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
0234 
0235     /* output */
0236     regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
0237 }
0238 
0239 static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
0240                        struct clk *m_ck, struct clk *b_ck)
0241 {
0242     int ret;
0243 
0244     if (m_ck) {
0245         ret = clk_prepare_enable(m_ck);
0246         if (ret) {
0247             dev_err(afe->dev, "Failed to enable m_ck\n");
0248             return ret;
0249         }
0250     }
0251 
0252     if (b_ck) {
0253         ret = clk_prepare_enable(b_ck);
0254         if (ret) {
0255             dev_err(afe->dev, "Failed to enable b_ck\n");
0256             return ret;
0257         }
0258     }
0259     return 0;
0260 }
0261 
0262 static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
0263                     struct clk *m_ck, unsigned int mck_rate,
0264                     struct clk *b_ck, unsigned int bck_rate)
0265 {
0266     int ret;
0267 
0268     if (m_ck) {
0269         ret = clk_set_rate(m_ck, mck_rate);
0270         if (ret) {
0271             dev_err(afe->dev, "Failed to set m_ck rate\n");
0272             return ret;
0273         }
0274     }
0275 
0276     if (b_ck) {
0277         ret = clk_set_rate(b_ck, bck_rate);
0278         if (ret) {
0279             dev_err(afe->dev, "Failed to set b_ck rate\n");
0280             return ret;
0281         }
0282     }
0283     return 0;
0284 }
0285 
0286 static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
0287                      struct clk *m_ck, struct clk *b_ck)
0288 {
0289     clk_disable_unprepare(m_ck);
0290     clk_disable_unprepare(b_ck);
0291 }
0292 
0293 static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
0294                   struct snd_soc_dai *dai)
0295 {
0296     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0297 
0298     if (snd_soc_dai_active(dai))
0299         return 0;
0300 
0301     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
0302                AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
0303     return 0;
0304 }
0305 
0306 static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
0307                     struct snd_soc_dai *dai)
0308 {
0309     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0310 
0311     if (snd_soc_dai_active(dai))
0312         return;
0313 
0314     mt8173_afe_set_i2s_enable(afe, false);
0315     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
0316                AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
0317                AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
0318 }
0319 
0320 static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
0321                   struct snd_soc_dai *dai)
0322 {
0323     struct snd_pcm_runtime * const runtime = substream->runtime;
0324     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0325     struct mt8173_afe_private *afe_priv = afe->platform_priv;
0326     int ret;
0327 
0328     mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
0329                  runtime->rate * 256, NULL, 0);
0330     mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
0331                  runtime->rate * 256, NULL, 0);
0332     /* config I2S */
0333     ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
0334     if (ret)
0335         return ret;
0336 
0337     mt8173_afe_set_i2s_enable(afe, true);
0338 
0339     return 0;
0340 }
0341 
0342 static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
0343                    struct snd_soc_dai *dai)
0344 {
0345     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0346     struct mt8173_afe_private *afe_priv = afe->platform_priv;
0347 
0348     if (snd_soc_dai_active(dai))
0349         return 0;
0350 
0351     mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
0352                     afe_priv->clocks[MT8173_CLK_I2S3_B]);
0353     return 0;
0354 }
0355 
0356 static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
0357                      struct snd_soc_dai *dai)
0358 {
0359     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0360     struct mt8173_afe_private *afe_priv = afe->platform_priv;
0361 
0362     if (snd_soc_dai_active(dai))
0363         return;
0364 
0365     mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
0366                      afe_priv->clocks[MT8173_CLK_I2S3_B]);
0367 }
0368 
0369 static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
0370                    struct snd_soc_dai *dai)
0371 {
0372     struct snd_pcm_runtime * const runtime = substream->runtime;
0373     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0374     struct mt8173_afe_private *afe_priv = afe->platform_priv;
0375 
0376     unsigned int val;
0377 
0378     mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
0379                  runtime->rate * 128,
0380                  afe_priv->clocks[MT8173_CLK_I2S3_B],
0381                  runtime->rate * runtime->channels * 32);
0382 
0383     val = AFE_TDM_CON1_BCK_INV |
0384           AFE_TDM_CON1_LRCK_INV |
0385           AFE_TDM_CON1_1_BCK_DELAY |
0386           AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
0387           AFE_TDM_CON1_WLEN_32BIT |
0388           AFE_TDM_CON1_32_BCK_CYCLES |
0389           AFE_TDM_CON1_LRCK_WIDTH(32);
0390     regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
0391 
0392     /* set tdm2 config */
0393     switch (runtime->channels) {
0394     case 1:
0395     case 2:
0396         val = AFE_TDM_CH_START_O30_O31;
0397         val |= (AFE_TDM_CH_ZERO << 4);
0398         val |= (AFE_TDM_CH_ZERO << 8);
0399         val |= (AFE_TDM_CH_ZERO << 12);
0400         break;
0401     case 3:
0402     case 4:
0403         val = AFE_TDM_CH_START_O30_O31;
0404         val |= (AFE_TDM_CH_START_O32_O33 << 4);
0405         val |= (AFE_TDM_CH_ZERO << 8);
0406         val |= (AFE_TDM_CH_ZERO << 12);
0407         break;
0408     case 5:
0409     case 6:
0410         val = AFE_TDM_CH_START_O30_O31;
0411         val |= (AFE_TDM_CH_START_O32_O33 << 4);
0412         val |= (AFE_TDM_CH_START_O34_O35 << 8);
0413         val |= (AFE_TDM_CH_ZERO << 12);
0414         break;
0415     case 7:
0416     case 8:
0417         val = AFE_TDM_CH_START_O30_O31;
0418         val |= (AFE_TDM_CH_START_O32_O33 << 4);
0419         val |= (AFE_TDM_CH_START_O34_O35 << 8);
0420         val |= (AFE_TDM_CH_START_O36_O37 << 12);
0421         break;
0422     default:
0423         val = 0;
0424     }
0425     regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
0426 
0427     regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
0428                0x000000f0, runtime->channels << 4);
0429     return 0;
0430 }
0431 
0432 static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
0433                    struct snd_soc_dai *dai)
0434 {
0435     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0436 
0437     dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
0438 
0439     switch (cmd) {
0440     case SNDRV_PCM_TRIGGER_START:
0441     case SNDRV_PCM_TRIGGER_RESUME:
0442         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
0443                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
0444 
0445         /* set connections:  O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
0446         regmap_write(afe->regmap, AFE_HDMI_CONN0,
0447                  AFE_HDMI_CONN0_O30_I30 |
0448                  AFE_HDMI_CONN0_O31_I31 |
0449                  AFE_HDMI_CONN0_O32_I34 |
0450                  AFE_HDMI_CONN0_O33_I35 |
0451                  AFE_HDMI_CONN0_O34_I32 |
0452                  AFE_HDMI_CONN0_O35_I33 |
0453                  AFE_HDMI_CONN0_O36_I36 |
0454                  AFE_HDMI_CONN0_O37_I37);
0455 
0456         /* enable Out control */
0457         regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
0458 
0459         /* enable tdm */
0460         regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
0461 
0462         return 0;
0463     case SNDRV_PCM_TRIGGER_STOP:
0464     case SNDRV_PCM_TRIGGER_SUSPEND:
0465         /* disable tdm */
0466         regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
0467 
0468         /* disable Out control */
0469         regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
0470 
0471         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
0472                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
0473                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
0474         return 0;
0475     default:
0476         return -EINVAL;
0477     }
0478 }
0479 
0480 static int mt8173_memif_fs(struct snd_pcm_substream *substream,
0481                unsigned int rate)
0482 {
0483     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0484     struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0485     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0486     struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id];
0487     int fs;
0488 
0489     if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
0490         memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
0491         switch (rate) {
0492         case 8000:
0493             fs = 0;
0494             break;
0495         case 16000:
0496             fs = 1;
0497             break;
0498         case 32000:
0499             fs = 2;
0500             break;
0501         default:
0502             return -EINVAL;
0503         }
0504     } else {
0505         fs = mt8173_afe_i2s_fs(rate);
0506     }
0507     return fs;
0508 }
0509 
0510 static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
0511 {
0512     return mt8173_afe_i2s_fs(rate);
0513 }
0514 
0515 /* BE DAIs */
0516 static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
0517     .startup    = mt8173_afe_i2s_startup,
0518     .shutdown   = mt8173_afe_i2s_shutdown,
0519     .prepare    = mt8173_afe_i2s_prepare,
0520 };
0521 
0522 static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
0523     .startup    = mt8173_afe_hdmi_startup,
0524     .shutdown   = mt8173_afe_hdmi_shutdown,
0525     .prepare    = mt8173_afe_hdmi_prepare,
0526     .trigger    = mt8173_afe_hdmi_trigger,
0527 };
0528 
0529 static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
0530     /* FE DAIs: memory intefaces to CPU */
0531     {
0532         .name = "DL1", /* downlink 1 */
0533         .id = MT8173_AFE_MEMIF_DL1,
0534         .playback = {
0535             .stream_name = "DL1",
0536             .channels_min = 1,
0537             .channels_max = 2,
0538             .rates = SNDRV_PCM_RATE_8000_48000,
0539             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0540         },
0541         .ops = &mtk_afe_fe_ops,
0542     }, {
0543         .name = "VUL", /* voice uplink */
0544         .id = MT8173_AFE_MEMIF_VUL,
0545         .capture = {
0546             .stream_name = "VUL",
0547             .channels_min = 1,
0548             .channels_max = 2,
0549             .rates = SNDRV_PCM_RATE_8000_48000,
0550             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0551         },
0552         .ops = &mtk_afe_fe_ops,
0553     }, {
0554     /* BE DAIs */
0555         .name = "I2S",
0556         .id = MT8173_AFE_IO_I2S,
0557         .playback = {
0558             .stream_name = "I2S Playback",
0559             .channels_min = 1,
0560             .channels_max = 2,
0561             .rates = SNDRV_PCM_RATE_8000_48000,
0562             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0563         },
0564         .capture = {
0565             .stream_name = "I2S Capture",
0566             .channels_min = 1,
0567             .channels_max = 2,
0568             .rates = SNDRV_PCM_RATE_8000_48000,
0569             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0570         },
0571         .ops = &mt8173_afe_i2s_ops,
0572         .symmetric_rate = 1,
0573     },
0574 };
0575 
0576 static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
0577     /* FE DAIs */
0578     {
0579         .name = "HDMI",
0580         .id = MT8173_AFE_MEMIF_HDMI,
0581         .playback = {
0582             .stream_name = "HDMI",
0583             .channels_min = 2,
0584             .channels_max = 8,
0585             .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
0586                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
0587                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
0588                 SNDRV_PCM_RATE_192000,
0589             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0590         },
0591         .ops = &mtk_afe_fe_ops,
0592     }, {
0593     /* BE DAIs */
0594         .name = "HDMIO",
0595         .id = MT8173_AFE_IO_HDMI,
0596         .playback = {
0597             .stream_name = "HDMIO Playback",
0598             .channels_min = 2,
0599             .channels_max = 8,
0600             .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
0601                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
0602                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
0603                 SNDRV_PCM_RATE_192000,
0604             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0605         },
0606         .ops = &mt8173_afe_hdmi_ops,
0607     },
0608 };
0609 
0610 static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
0611     SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
0612 };
0613 
0614 static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
0615     SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
0616 };
0617 
0618 static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
0619     SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
0620     SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
0621 };
0622 
0623 static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
0624     SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
0625     SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
0626 };
0627 
0628 static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
0629     /* inter-connections */
0630     SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
0631     SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
0632     SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
0633     SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
0634     SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
0635     SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
0636 
0637     SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
0638                mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
0639     SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
0640                mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
0641     SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
0642                mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
0643     SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
0644                mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
0645 };
0646 
0647 static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
0648     {"I05", NULL, "DL1"},
0649     {"I06", NULL, "DL1"},
0650     {"I2S Playback", NULL, "O03"},
0651     {"I2S Playback", NULL, "O04"},
0652     {"VUL", NULL, "O09"},
0653     {"VUL", NULL, "O10"},
0654     {"I03", NULL, "I2S Capture"},
0655     {"I04", NULL, "I2S Capture"},
0656     {"I17", NULL, "I2S Capture"},
0657     {"I18", NULL, "I2S Capture"},
0658     { "O03", "I05 Switch", "I05" },
0659     { "O04", "I06 Switch", "I06" },
0660     { "O09", "I17 Switch", "I17" },
0661     { "O09", "I03 Switch", "I03" },
0662     { "O10", "I18 Switch", "I18" },
0663     { "O10", "I04 Switch", "I04" },
0664 };
0665 
0666 static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
0667     {"HDMIO Playback", NULL, "HDMI"},
0668 };
0669 
0670 static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
0671     .name = "mt8173-afe-pcm-dai",
0672     .dapm_widgets = mt8173_afe_pcm_widgets,
0673     .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
0674     .dapm_routes = mt8173_afe_pcm_routes,
0675     .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
0676     .suspend = mtk_afe_suspend,
0677     .resume = mtk_afe_resume,
0678 };
0679 
0680 static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
0681     .name = "mt8173-afe-hdmi-dai",
0682     .dapm_routes = mt8173_afe_hdmi_routes,
0683     .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
0684     .suspend = mtk_afe_suspend,
0685     .resume = mtk_afe_resume,
0686 };
0687 
0688 static const char *aud_clks[MT8173_CLK_NUM] = {
0689     [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
0690     [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
0691     [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
0692     [MT8173_CLK_I2S0_M] =  "i2s0_m",
0693     [MT8173_CLK_I2S1_M] =  "i2s1_m",
0694     [MT8173_CLK_I2S2_M] =  "i2s2_m",
0695     [MT8173_CLK_I2S3_M] =  "i2s3_m",
0696     [MT8173_CLK_I2S3_B] =  "i2s3_b",
0697     [MT8173_CLK_BCK0] =  "bck0",
0698     [MT8173_CLK_BCK1] =  "bck1",
0699 };
0700 
0701 static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
0702     {
0703         .name = "DL1",
0704         .id = MT8173_AFE_MEMIF_DL1,
0705         .reg_ofs_base = AFE_DL1_BASE,
0706         .reg_ofs_cur = AFE_DL1_CUR,
0707         .fs_reg = AFE_DAC_CON1,
0708         .fs_shift = 0,
0709         .fs_maskbit = 0xf,
0710         .mono_reg = AFE_DAC_CON1,
0711         .mono_shift = 21,
0712         .hd_reg = -1,
0713         .enable_reg = AFE_DAC_CON0,
0714         .enable_shift = 1,
0715         .msb_reg = AFE_MEMIF_MSB,
0716         .msb_shift = 0,
0717         .agent_disable_reg = -1,
0718     }, {
0719         .name = "DL2",
0720         .id = MT8173_AFE_MEMIF_DL2,
0721         .reg_ofs_base = AFE_DL2_BASE,
0722         .reg_ofs_cur = AFE_DL2_CUR,
0723         .fs_reg = AFE_DAC_CON1,
0724         .fs_shift = 4,
0725         .fs_maskbit = 0xf,
0726         .mono_reg = AFE_DAC_CON1,
0727         .mono_shift = 22,
0728         .hd_reg = -1,
0729         .enable_reg = AFE_DAC_CON0,
0730         .enable_shift = 2,
0731         .msb_reg = AFE_MEMIF_MSB,
0732         .msb_shift = 1,
0733         .agent_disable_reg = -1,
0734     }, {
0735         .name = "VUL",
0736         .id = MT8173_AFE_MEMIF_VUL,
0737         .reg_ofs_base = AFE_VUL_BASE,
0738         .reg_ofs_cur = AFE_VUL_CUR,
0739         .fs_reg = AFE_DAC_CON1,
0740         .fs_shift = 16,
0741         .fs_maskbit = 0xf,
0742         .mono_reg = AFE_DAC_CON1,
0743         .mono_shift = 27,
0744         .hd_reg = -1,
0745         .enable_reg = AFE_DAC_CON0,
0746         .enable_shift = 3,
0747         .msb_reg = AFE_MEMIF_MSB,
0748         .msb_shift = 6,
0749         .agent_disable_reg = -1,
0750     }, {
0751         .name = "DAI",
0752         .id = MT8173_AFE_MEMIF_DAI,
0753         .reg_ofs_base = AFE_DAI_BASE,
0754         .reg_ofs_cur = AFE_DAI_CUR,
0755         .fs_reg = AFE_DAC_CON0,
0756         .fs_shift = 24,
0757         .fs_maskbit = 0x3,
0758         .mono_reg = -1,
0759         .mono_shift = -1,
0760         .hd_reg = -1,
0761         .enable_reg = AFE_DAC_CON0,
0762         .enable_shift = 4,
0763         .msb_reg = AFE_MEMIF_MSB,
0764         .msb_shift = 5,
0765         .agent_disable_reg = -1,
0766     }, {
0767         .name = "AWB",
0768         .id = MT8173_AFE_MEMIF_AWB,
0769         .reg_ofs_base = AFE_AWB_BASE,
0770         .reg_ofs_cur = AFE_AWB_CUR,
0771         .fs_reg = AFE_DAC_CON1,
0772         .fs_shift = 12,
0773         .fs_maskbit = 0xf,
0774         .mono_reg = AFE_DAC_CON1,
0775         .mono_shift = 24,
0776         .hd_reg = -1,
0777         .enable_reg = AFE_DAC_CON0,
0778         .enable_shift = 6,
0779         .msb_reg = AFE_MEMIF_MSB,
0780         .msb_shift = 3,
0781         .agent_disable_reg = -1,
0782     }, {
0783         .name = "MOD_DAI",
0784         .id = MT8173_AFE_MEMIF_MOD_DAI,
0785         .reg_ofs_base = AFE_MOD_PCM_BASE,
0786         .reg_ofs_cur = AFE_MOD_PCM_CUR,
0787         .fs_reg = AFE_DAC_CON1,
0788         .fs_shift = 30,
0789         .fs_maskbit = 0x3,
0790         .mono_reg = AFE_DAC_CON1,
0791         .mono_shift = 30,
0792         .hd_reg = -1,
0793         .enable_reg = AFE_DAC_CON0,
0794         .enable_shift = 7,
0795         .msb_reg = AFE_MEMIF_MSB,
0796         .msb_shift = 4,
0797         .agent_disable_reg = -1,
0798     }, {
0799         .name = "HDMI",
0800         .id = MT8173_AFE_MEMIF_HDMI,
0801         .reg_ofs_base = AFE_HDMI_OUT_BASE,
0802         .reg_ofs_cur = AFE_HDMI_OUT_CUR,
0803         .fs_reg = -1,
0804         .fs_shift = -1,
0805         .fs_maskbit = -1,
0806         .mono_reg = -1,
0807         .mono_shift = -1,
0808         .hd_reg = -1,
0809         .enable_reg = -1,
0810         .msb_reg = AFE_MEMIF_MSB,
0811         .msb_shift = 8,
0812         .agent_disable_reg = -1,
0813     },
0814 };
0815 
0816 static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
0817     {
0818         .id = MT8173_AFE_IRQ_DL1,
0819         .irq_cnt_reg = AFE_IRQ_CNT1,
0820         .irq_cnt_shift = 0,
0821         .irq_cnt_maskbit = 0x3ffff,
0822         .irq_en_reg = AFE_IRQ_MCU_CON,
0823         .irq_en_shift = 0,
0824         .irq_fs_reg = AFE_IRQ_MCU_CON,
0825         .irq_fs_shift = 4,
0826         .irq_fs_maskbit = 0xf,
0827         .irq_clr_reg = AFE_IRQ_CLR,
0828         .irq_clr_shift = 0,
0829     }, {
0830         .id = MT8173_AFE_IRQ_DL2,
0831         .irq_cnt_reg = AFE_IRQ_CNT1,
0832         .irq_cnt_shift = 20,
0833         .irq_cnt_maskbit = 0x3ffff,
0834         .irq_en_reg = AFE_IRQ_MCU_CON,
0835         .irq_en_shift = 2,
0836         .irq_fs_reg = AFE_IRQ_MCU_CON,
0837         .irq_fs_shift = 16,
0838         .irq_fs_maskbit = 0xf,
0839         .irq_clr_reg = AFE_IRQ_CLR,
0840         .irq_clr_shift = 2,
0841 
0842     }, {
0843         .id = MT8173_AFE_IRQ_VUL,
0844         .irq_cnt_reg = AFE_IRQ_CNT2,
0845         .irq_cnt_shift = 0,
0846         .irq_cnt_maskbit = 0x3ffff,
0847         .irq_en_reg = AFE_IRQ_MCU_CON,
0848         .irq_en_shift = 1,
0849         .irq_fs_reg = AFE_IRQ_MCU_CON,
0850         .irq_fs_shift = 8,
0851         .irq_fs_maskbit = 0xf,
0852         .irq_clr_reg = AFE_IRQ_CLR,
0853         .irq_clr_shift = 1,
0854     }, {
0855         .id = MT8173_AFE_IRQ_DAI,
0856         .irq_cnt_reg = AFE_IRQ_CNT2,
0857         .irq_cnt_shift = 20,
0858         .irq_cnt_maskbit = 0x3ffff,
0859         .irq_en_reg = AFE_IRQ_MCU_CON,
0860         .irq_en_shift = 3,
0861         .irq_fs_reg = AFE_IRQ_MCU_CON,
0862         .irq_fs_shift = 20,
0863         .irq_fs_maskbit = 0xf,
0864         .irq_clr_reg = AFE_IRQ_CLR,
0865         .irq_clr_shift = 3,
0866     }, {
0867         .id = MT8173_AFE_IRQ_AWB,
0868         .irq_cnt_reg = AFE_IRQ_CNT7,
0869         .irq_cnt_shift = 0,
0870         .irq_cnt_maskbit = 0x3ffff,
0871         .irq_en_reg = AFE_IRQ_MCU_CON,
0872         .irq_en_shift = 14,
0873         .irq_fs_reg = AFE_IRQ_MCU_CON,
0874         .irq_fs_shift = 24,
0875         .irq_fs_maskbit = 0xf,
0876         .irq_clr_reg = AFE_IRQ_CLR,
0877         .irq_clr_shift = 6,
0878     }, {
0879         .id = MT8173_AFE_IRQ_DAI,
0880         .irq_cnt_reg = AFE_IRQ_CNT2,
0881         .irq_cnt_shift = 20,
0882         .irq_cnt_maskbit = 0x3ffff,
0883         .irq_en_reg = AFE_IRQ_MCU_CON,
0884         .irq_en_shift = 3,
0885         .irq_fs_reg = AFE_IRQ_MCU_CON,
0886         .irq_fs_shift = 20,
0887         .irq_fs_maskbit = 0xf,
0888         .irq_clr_reg = AFE_IRQ_CLR,
0889         .irq_clr_shift = 3,
0890     }, {
0891         .id = MT8173_AFE_IRQ_HDMI,
0892         .irq_cnt_reg = AFE_IRQ_CNT5,
0893         .irq_cnt_shift = 0,
0894         .irq_cnt_maskbit = 0x3ffff,
0895         .irq_en_reg = AFE_IRQ_MCU_CON,
0896         .irq_en_shift = 12,
0897         .irq_fs_reg = -1,
0898         .irq_fs_maskbit = -1,
0899         .irq_clr_reg = AFE_IRQ_CLR,
0900         .irq_clr_shift = 4,
0901     },
0902 };
0903 
0904 static const struct regmap_config mt8173_afe_regmap_config = {
0905     .reg_bits = 32,
0906     .reg_stride = 4,
0907     .val_bits = 32,
0908     .max_register = AFE_ADDA2_TOP_CON0,
0909     .cache_type = REGCACHE_NONE,
0910 };
0911 
0912 static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
0913 {
0914     struct mtk_base_afe *afe = dev_id;
0915     unsigned int reg_value;
0916     int i, ret;
0917 
0918     ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
0919     if (ret) {
0920         dev_err(afe->dev, "%s irq status err\n", __func__);
0921         reg_value = AFE_IRQ_STATUS_BITS;
0922         goto err_irq;
0923     }
0924 
0925     for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
0926         struct mtk_base_afe_memif *memif = &afe->memif[i];
0927         struct mtk_base_afe_irq *irq_p;
0928 
0929         if (memif->irq_usage < 0)
0930             continue;
0931 
0932         irq_p = &afe->irqs[memif->irq_usage];
0933 
0934         if (!(reg_value & (1 << irq_p->irq_data->irq_clr_shift)))
0935             continue;
0936 
0937         snd_pcm_period_elapsed(memif->substream);
0938     }
0939 
0940 err_irq:
0941     /* clear irq */
0942     regmap_write(afe->regmap, AFE_IRQ_CLR,
0943              reg_value & AFE_IRQ_STATUS_BITS);
0944 
0945     return IRQ_HANDLED;
0946 }
0947 
0948 static int mt8173_afe_runtime_suspend(struct device *dev)
0949 {
0950     struct mtk_base_afe *afe = dev_get_drvdata(dev);
0951     struct mt8173_afe_private *afe_priv = afe->platform_priv;
0952 
0953     /* disable AFE */
0954     regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
0955 
0956     /* disable AFE clk */
0957     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
0958                AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
0959 
0960     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
0961     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
0962     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
0963     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
0964     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
0965     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
0966     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
0967     return 0;
0968 }
0969 
0970 static int mt8173_afe_runtime_resume(struct device *dev)
0971 {
0972     struct mtk_base_afe *afe = dev_get_drvdata(dev);
0973     struct mt8173_afe_private *afe_priv = afe->platform_priv;
0974     int ret;
0975 
0976     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
0977     if (ret)
0978         return ret;
0979 
0980     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
0981     if (ret)
0982         goto err_infra;
0983 
0984     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
0985     if (ret)
0986         goto err_top_aud_bus;
0987 
0988     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
0989     if (ret)
0990         goto err_top_aud;
0991 
0992     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
0993     if (ret)
0994         goto err_bck0;
0995     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
0996     if (ret)
0997         goto err_i2s1_m;
0998     ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
0999     if (ret)
1000         goto err_i2s2_m;
1001 
1002     /* enable AFE clk */
1003     regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1004 
1005     /* set O3/O4 16bits */
1006     regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1007                AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1008 
1009     /* unmask all IRQs */
1010     regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1011 
1012     /* enable AFE */
1013     regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1014     return 0;
1015 
1016 err_i2s1_m:
1017     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1018 err_i2s2_m:
1019     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1020 err_bck0:
1021     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1022 err_top_aud:
1023     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1024 err_top_aud_bus:
1025     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1026 err_infra:
1027     clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1028     return ret;
1029 }
1030 
1031 static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
1032 {
1033     size_t i;
1034     struct mt8173_afe_private *afe_priv = afe->platform_priv;
1035 
1036     for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1037         afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1038         if (IS_ERR(afe_priv->clocks[i])) {
1039             dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1040                 __func__, aud_clks[i]);
1041             return PTR_ERR(afe_priv->clocks[i]);
1042         }
1043     }
1044     clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
1045     clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
1046     return 0;
1047 }
1048 
1049 static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1050 {
1051     int ret, i;
1052     int irq_id;
1053     struct mtk_base_afe *afe;
1054     struct mt8173_afe_private *afe_priv;
1055     struct snd_soc_component *comp_pcm, *comp_hdmi;
1056 
1057     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1058     if (ret)
1059         return ret;
1060 
1061     afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1062     if (!afe)
1063         return -ENOMEM;
1064 
1065     afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1066                       GFP_KERNEL);
1067     afe_priv = afe->platform_priv;
1068     if (!afe_priv)
1069         return -ENOMEM;
1070 
1071     afe->dev = &pdev->dev;
1072 
1073     irq_id = platform_get_irq(pdev, 0);
1074     if (irq_id <= 0)
1075         return irq_id < 0 ? irq_id : -ENXIO;
1076     ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
1077                    0, "Afe_ISR_Handle", (void *)afe);
1078     if (ret) {
1079         dev_err(afe->dev, "could not request_irq\n");
1080         return ret;
1081     }
1082 
1083     afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
1084     if (IS_ERR(afe->base_addr))
1085         return PTR_ERR(afe->base_addr);
1086 
1087     afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1088         &mt8173_afe_regmap_config);
1089     if (IS_ERR(afe->regmap))
1090         return PTR_ERR(afe->regmap);
1091 
1092     /* initial audio related clock */
1093     ret = mt8173_afe_init_audio_clk(afe);
1094     if (ret) {
1095         dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n");
1096         return ret;
1097     }
1098 
1099     /* memif % irq initialize*/
1100     afe->memif_size = MT8173_AFE_MEMIF_NUM;
1101     afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
1102                   sizeof(*afe->memif), GFP_KERNEL);
1103     if (!afe->memif)
1104         return -ENOMEM;
1105 
1106     afe->irqs_size = MT8173_AFE_IRQ_NUM;
1107     afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
1108                  sizeof(*afe->irqs), GFP_KERNEL);
1109     if (!afe->irqs)
1110         return -ENOMEM;
1111 
1112     for (i = 0; i < afe->irqs_size; i++) {
1113         afe->memif[i].data = &memif_data[i];
1114         afe->irqs[i].irq_data = &irq_data[i];
1115         afe->irqs[i].irq_occupyed = true;
1116         afe->memif[i].irq_usage = i;
1117         afe->memif[i].const_irq = 1;
1118     }
1119 
1120     afe->mtk_afe_hardware = &mt8173_afe_hardware;
1121     afe->memif_fs = mt8173_memif_fs;
1122     afe->irq_fs = mt8173_irq_fs;
1123 
1124     platform_set_drvdata(pdev, afe);
1125 
1126     pm_runtime_enable(&pdev->dev);
1127     if (!pm_runtime_enabled(&pdev->dev)) {
1128         ret = mt8173_afe_runtime_resume(&pdev->dev);
1129         if (ret)
1130             goto err_pm_disable;
1131     }
1132 
1133     afe->reg_back_up_list = mt8173_afe_backup_list;
1134     afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
1135     afe->runtime_resume = mt8173_afe_runtime_resume;
1136     afe->runtime_suspend = mt8173_afe_runtime_suspend;
1137 
1138     ret = devm_snd_soc_register_component(&pdev->dev,
1139                      &mtk_afe_pcm_platform,
1140                      NULL, 0);
1141     if (ret)
1142         goto err_pm_disable;
1143 
1144     comp_pcm = devm_kzalloc(&pdev->dev, sizeof(*comp_pcm), GFP_KERNEL);
1145     if (!comp_pcm) {
1146         ret = -ENOMEM;
1147         goto err_pm_disable;
1148     }
1149 
1150     ret = snd_soc_component_initialize(comp_pcm,
1151                        &mt8173_afe_pcm_dai_component,
1152                        &pdev->dev);
1153     if (ret)
1154         goto err_pm_disable;
1155 
1156 #ifdef CONFIG_DEBUG_FS
1157     comp_pcm->debugfs_prefix = "pcm";
1158 #endif
1159 
1160     ret = snd_soc_add_component(comp_pcm,
1161                     mt8173_afe_pcm_dais,
1162                     ARRAY_SIZE(mt8173_afe_pcm_dais));
1163     if (ret)
1164         goto err_pm_disable;
1165 
1166     comp_hdmi = devm_kzalloc(&pdev->dev, sizeof(*comp_hdmi), GFP_KERNEL);
1167     if (!comp_hdmi) {
1168         ret = -ENOMEM;
1169         goto err_pm_disable;
1170     }
1171 
1172     ret = snd_soc_component_initialize(comp_hdmi,
1173                        &mt8173_afe_hdmi_dai_component,
1174                        &pdev->dev);
1175     if (ret)
1176         goto err_pm_disable;
1177 
1178 #ifdef CONFIG_DEBUG_FS
1179     comp_hdmi->debugfs_prefix = "hdmi";
1180 #endif
1181 
1182     ret = snd_soc_add_component(comp_hdmi,
1183                     mt8173_afe_hdmi_dais,
1184                     ARRAY_SIZE(mt8173_afe_hdmi_dais));
1185     if (ret)
1186         goto err_cleanup_components;
1187 
1188     dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n");
1189     return 0;
1190 
1191 err_cleanup_components:
1192     snd_soc_unregister_component(&pdev->dev);
1193 err_pm_disable:
1194     pm_runtime_disable(&pdev->dev);
1195     return ret;
1196 }
1197 
1198 static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
1199 {
1200     snd_soc_unregister_component(&pdev->dev);
1201 
1202     pm_runtime_disable(&pdev->dev);
1203     if (!pm_runtime_status_suspended(&pdev->dev))
1204         mt8173_afe_runtime_suspend(&pdev->dev);
1205     return 0;
1206 }
1207 
1208 static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
1209     { .compatible = "mediatek,mt8173-afe-pcm", },
1210     { }
1211 };
1212 MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
1213 
1214 static const struct dev_pm_ops mt8173_afe_pm_ops = {
1215     SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
1216                mt8173_afe_runtime_resume, NULL)
1217 };
1218 
1219 static struct platform_driver mt8173_afe_pcm_driver = {
1220     .driver = {
1221            .name = "mt8173-afe-pcm",
1222            .of_match_table = mt8173_afe_pcm_dt_match,
1223            .pm = &mt8173_afe_pm_ops,
1224     },
1225     .probe = mt8173_afe_pcm_dev_probe,
1226     .remove = mt8173_afe_pcm_dev_remove,
1227 };
1228 
1229 module_platform_driver(mt8173_afe_pcm_driver);
1230 
1231 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1232 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1233 MODULE_LICENSE("GPL v2");
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