mediatek/mt6797/mt6797-dai-adda.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // MediaTek ALSA SoC Audio DAI ADDA Control
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007
0008 #include <linux/regmap.h>
0009 #include <linux/delay.h>
0010 #include "mt6797-afe-common.h"
0011 #include "mt6797-interconnection.h"
0012 #include "mt6797-reg.h"
0013
0014 enum {
0015     MTK_AFE_ADDA_DL_RATE_8K = 0,
0016     MTK_AFE_ADDA_DL_RATE_11K = 1,
0017     MTK_AFE_ADDA_DL_RATE_12K = 2,
0018     MTK_AFE_ADDA_DL_RATE_16K = 3,
0019     MTK_AFE_ADDA_DL_RATE_22K = 4,
0020     MTK_AFE_ADDA_DL_RATE_24K = 5,
0021     MTK_AFE_ADDA_DL_RATE_32K = 6,
0022     MTK_AFE_ADDA_DL_RATE_44K = 7,
0023     MTK_AFE_ADDA_DL_RATE_48K = 8,
0024     MTK_AFE_ADDA_DL_RATE_96K = 9,
0025     MTK_AFE_ADDA_DL_RATE_192K = 10,
0026 };
0027
0028 enum {
0029     MTK_AFE_ADDA_UL_RATE_8K = 0,
0030     MTK_AFE_ADDA_UL_RATE_16K = 1,
0031     MTK_AFE_ADDA_UL_RATE_32K = 2,
0032     MTK_AFE_ADDA_UL_RATE_48K = 3,
0033     MTK_AFE_ADDA_UL_RATE_96K = 4,
0034     MTK_AFE_ADDA_UL_RATE_192K = 5,
0035     MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
0036 };
0037
0038 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
0039                        unsigned int rate)
0040 {
0041     switch (rate) {
0042     case 8000:
0043         return MTK_AFE_ADDA_DL_RATE_8K;
0044     case 11025:
0045         return MTK_AFE_ADDA_DL_RATE_11K;
0046     case 12000:
0047         return MTK_AFE_ADDA_DL_RATE_12K;
0048     case 16000:
0049         return MTK_AFE_ADDA_DL_RATE_16K;
0050     case 22050:
0051         return MTK_AFE_ADDA_DL_RATE_22K;
0052     case 24000:
0053         return MTK_AFE_ADDA_DL_RATE_24K;
0054     case 32000:
0055         return MTK_AFE_ADDA_DL_RATE_32K;
0056     case 44100:
0057         return MTK_AFE_ADDA_DL_RATE_44K;
0058     case 48000:
0059         return MTK_AFE_ADDA_DL_RATE_48K;
0060     case 96000:
0061         return MTK_AFE_ADDA_DL_RATE_96K;
0062     case 192000:
0063         return MTK_AFE_ADDA_DL_RATE_192K;
0064     default:
0065         dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0066              __func__, rate);
0067         return MTK_AFE_ADDA_DL_RATE_48K;
0068     }
0069 }
0070
0071 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
0072                        unsigned int rate)
0073 {
0074     switch (rate) {
0075     case 8000:
0076         return MTK_AFE_ADDA_UL_RATE_8K;
0077     case 16000:
0078         return MTK_AFE_ADDA_UL_RATE_16K;
0079     case 32000:
0080         return MTK_AFE_ADDA_UL_RATE_32K;
0081     case 48000:
0082         return MTK_AFE_ADDA_UL_RATE_48K;
0083     case 96000:
0084         return MTK_AFE_ADDA_UL_RATE_96K;
0085     case 192000:
0086         return MTK_AFE_ADDA_UL_RATE_192K;
0087     default:
0088         dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
0089              __func__, rate);
0090         return MTK_AFE_ADDA_UL_RATE_48K;
0091     }
0092 }
0093
0094 /* dai component */
0095 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
0096     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
0097     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
0098     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
0099     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
0100                     I_ADDA_UL_CH2, 1, 0),
0101     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
0102                     I_ADDA_UL_CH1, 1, 0),
0103     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
0104                     I_PCM_1_CAP_CH1, 1, 0),
0105     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
0106                     I_PCM_2_CAP_CH1, 1, 0),
0107 };
0108
0109 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
0110     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
0111     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
0112     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
0113     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
0114     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
0115     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
0116     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
0117                     I_ADDA_UL_CH2, 1, 0),
0118     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
0119                     I_ADDA_UL_CH1, 1, 0),
0120     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
0121                     I_PCM_1_CAP_CH1, 1, 0),
0122     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
0123                     I_PCM_2_CAP_CH1, 1, 0),
0124     SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
0125                     I_PCM_1_CAP_CH2, 1, 0),
0126     SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
0127                     I_PCM_2_CAP_CH2, 1, 0),
0128 };
0129
0130 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
0131                  struct snd_kcontrol *kcontrol,
0132                  int event)
0133 {
0134     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0135     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
0136
0137     dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
0138         __func__, w->name, event);
0139
0140     switch (event) {
0141     case SND_SOC_DAPM_POST_PMD:
0142         /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
0143         usleep_range(125, 135);
0144         break;
0145     default:
0146         break;
0147     }
0148
0149     return 0;
0150 }
0151
0152 enum {
0153     SUPPLY_SEQ_AUD_TOP_PDN,
0154     SUPPLY_SEQ_ADDA_AFE_ON,
0155     SUPPLY_SEQ_ADDA_DL_ON,
0156     SUPPLY_SEQ_ADDA_UL_ON,
0157 };
0158
0159 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
0160     /* adda */
0161     SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
0162                mtk_adda_dl_ch1_mix,
0163                ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
0164     SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
0165                mtk_adda_dl_ch2_mix,
0166                ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
0167
0168     SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
0169                   AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
0170                   NULL, 0),
0171
0172     SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
0173                   AFE_ADDA_DL_SRC2_CON0,
0174                   DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
0175                   NULL, 0),
0176
0177     SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
0178                   AFE_ADDA_UL_SRC_CON0,
0179                   UL_SRC_ON_TMP_CTL_SFT, 0,
0180                   mtk_adda_ul_event,
0181                   SND_SOC_DAPM_POST_PMD),
0182
0183     SND_SOC_DAPM_SUPPLY_S("aud_dac_clk", SUPPLY_SEQ_AUD_TOP_PDN,
0184                   AUDIO_TOP_CON0, PDN_DAC_SFT, 1,
0185                   NULL, 0),
0186     SND_SOC_DAPM_SUPPLY_S("aud_dac_predis_clk", SUPPLY_SEQ_AUD_TOP_PDN,
0187                   AUDIO_TOP_CON0, PDN_DAC_PREDIS_SFT, 1,
0188                   NULL, 0),
0189
0190     SND_SOC_DAPM_SUPPLY_S("aud_adc_clk", SUPPLY_SEQ_AUD_TOP_PDN,
0191                   AUDIO_TOP_CON0, PDN_ADC_SFT, 1,
0192                   NULL, 0),
0193
0194     SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
0195 };
0196
0197 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
0198     /* playback */
0199     {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
0200     {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
0201     {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
0202
0203     {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
0204     {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
0205     {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
0206
0207     {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
0208     {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
0209     {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
0210
0211     {"ADDA Playback", NULL, "ADDA_DL_CH1"},
0212     {"ADDA Playback", NULL, "ADDA_DL_CH2"},
0213
0214     /* adda enable */
0215     {"ADDA Playback", NULL, "ADDA Enable"},
0216     {"ADDA Playback", NULL, "ADDA Playback Enable"},
0217     {"ADDA Capture", NULL, "ADDA Enable"},
0218     {"ADDA Capture", NULL, "ADDA Capture Enable"},
0219
0220     /* clk */
0221     {"ADDA Playback", NULL, "mtkaif_26m_clk"},
0222     {"ADDA Playback", NULL, "aud_dac_clk"},
0223     {"ADDA Playback", NULL, "aud_dac_predis_clk"},
0224
0225     {"ADDA Capture", NULL, "mtkaif_26m_clk"},
0226     {"ADDA Capture", NULL, "aud_adc_clk"},
0227 };
0228
0229 /* dai ops */
0230 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
0231                   struct snd_pcm_hw_params *params,
0232                   struct snd_soc_dai *dai)
0233 {
0234     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0235     unsigned int rate = params_rate(params);
0236
0237     dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
0238         __func__, dai->id, substream->stream, rate);
0239
0240     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0241         unsigned int dl_src2_con0 = 0;
0242         unsigned int dl_src2_con1 = 0;
0243
0244         /* clean predistortion */
0245         regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
0246         regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
0247
0248         /* set input sampling rate */
0249         dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
0250
0251         /* set output mode */
0252         switch (rate) {
0253         case 192000:
0254             dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
0255             dl_src2_con0 |= 1 << 14;
0256             break;
0257         case 96000:
0258             dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
0259             dl_src2_con0 |= 1 << 14;
0260             break;
0261         default:
0262             dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
0263             break;
0264         }
0265
0266         /* turn off mute function */
0267         dl_src2_con0 |= (0x03 << 11);
0268
0269         /* set voice input data if input sample rate is 8k or 16k */
0270         if (rate == 8000 || rate == 16000)
0271             dl_src2_con0 |= 0x01 << 5;
0272
0273         if (rate < 96000) {
0274             /* SA suggest apply -0.3db to audio/speech path */
0275             dl_src2_con1 = 0xf74f0000;
0276         } else {
0277             /* SA suggest apply -0.3db to audio/speech path
0278              * with DL gain set to half,
0279              * 0xFFFF = 0dB -> 0x8000 = 0dB when 96k, 192k
0280              */
0281             dl_src2_con1 = 0x7ba70000;
0282         }
0283
0284         /* turn on down-link gain */
0285         dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
0286
0287         regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
0288         regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
0289     } else {
0290         unsigned int voice_mode = 0;
0291         unsigned int ul_src_con0 = 0;   /* default value */
0292
0293         /* Using Internal ADC */
0294         regmap_update_bits(afe->regmap,
0295                    AFE_ADDA_TOP_CON0,
0296                    0x1 << 0,
0297                    0x0 << 0);
0298
0299         voice_mode = adda_ul_rate_transform(afe, rate);
0300
0301         ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
0302
0303         /* up8x txif sat on */
0304         regmap_write(afe->regmap, AFE_ADDA_NEWIF_CFG0, 0x03F87201);
0305
0306         if (rate >= 96000) {    /* hires */
0307             /* use hires format [1 0 23] */
0308             regmap_update_bits(afe->regmap,
0309                        AFE_ADDA_NEWIF_CFG0,
0310                        0x1 << 5,
0311                        0x1 << 5);
0312
0313             regmap_update_bits(afe->regmap,
0314                        AFE_ADDA_NEWIF_CFG2,
0315                        0xf << 28,
0316                        voice_mode << 28);
0317         } else {    /* normal 8~48k */
0318             /* use fixed 260k anc path */
0319             regmap_update_bits(afe->regmap,
0320                        AFE_ADDA_NEWIF_CFG2,
0321                        0xf << 28,
0322                        8 << 28);
0323
0324             /* ul_use_cic_out */
0325             ul_src_con0 |= 0x1 << 20;
0326         }
0327
0328         regmap_update_bits(afe->regmap,
0329                    AFE_ADDA_NEWIF_CFG2,
0330                    0xf << 28,
0331                    8 << 28);
0332
0333         regmap_update_bits(afe->regmap,
0334                    AFE_ADDA_UL_SRC_CON0,
0335                    0xfffffffe,
0336                    ul_src_con0);
0337     }
0338
0339     return 0;
0340 }
0341
0342 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
0343     .hw_params = mtk_dai_adda_hw_params,
0344 };
0345
0346 /* dai driver */
0347 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
0348                  SNDRV_PCM_RATE_96000 |\
0349                  SNDRV_PCM_RATE_192000)
0350
0351 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
0352                 SNDRV_PCM_RATE_16000 |\
0353                 SNDRV_PCM_RATE_32000 |\
0354                 SNDRV_PCM_RATE_48000 |\
0355                 SNDRV_PCM_RATE_96000 |\
0356                 SNDRV_PCM_RATE_192000)
0357
0358 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0359               SNDRV_PCM_FMTBIT_S24_LE |\
0360               SNDRV_PCM_FMTBIT_S32_LE)
0361
0362 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
0363     {
0364         .name = "ADDA",
0365         .id = MT6797_DAI_ADDA,
0366         .playback = {
0367             .stream_name = "ADDA Playback",
0368             .channels_min = 1,
0369             .channels_max = 2,
0370             .rates = MTK_ADDA_PLAYBACK_RATES,
0371             .formats = MTK_ADDA_FORMATS,
0372         },
0373         .capture = {
0374             .stream_name = "ADDA Capture",
0375             .channels_min = 1,
0376             .channels_max = 2,
0377             .rates = MTK_ADDA_CAPTURE_RATES,
0378             .formats = MTK_ADDA_FORMATS,
0379         },
0380         .ops = &mtk_dai_adda_ops,
0381     },
0382 };
0383
0384 int mt6797_dai_adda_register(struct mtk_base_afe *afe)
0385 {
0386     struct mtk_base_afe_dai *dai;
0387
0388     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
0389     if (!dai)
0390         return -ENOMEM;
0391
0392     list_add(&dai->list, &afe->sub_dais);
0393
0394     dai->dai_drivers = mtk_dai_adda_driver;
0395     dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
0396
0397     dai->dapm_widgets = mtk_dai_adda_widgets;
0398     dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
0399     dai->dapm_routes = mtk_dai_adda_routes;
0400     dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
0401     return 0;
0402 }