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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Mediatek ALSA SoC AFE platform driver for 6797
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007 
0008 #include <linux/delay.h>
0009 #include <linux/module.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/pm_runtime.h>
0014 
0015 #include "mt6797-afe-common.h"
0016 #include "mt6797-afe-clk.h"
0017 #include "mt6797-interconnection.h"
0018 #include "mt6797-reg.h"
0019 #include "../common/mtk-afe-platform-driver.h"
0020 #include "../common/mtk-afe-fe-dai.h"
0021 
0022 enum {
0023     MTK_AFE_RATE_8K = 0,
0024     MTK_AFE_RATE_11K = 1,
0025     MTK_AFE_RATE_12K = 2,
0026     MTK_AFE_RATE_384K = 3,
0027     MTK_AFE_RATE_16K = 4,
0028     MTK_AFE_RATE_22K = 5,
0029     MTK_AFE_RATE_24K = 6,
0030     MTK_AFE_RATE_130K = 7,
0031     MTK_AFE_RATE_32K = 8,
0032     MTK_AFE_RATE_44K = 9,
0033     MTK_AFE_RATE_48K = 10,
0034     MTK_AFE_RATE_88K = 11,
0035     MTK_AFE_RATE_96K = 12,
0036     MTK_AFE_RATE_174K = 13,
0037     MTK_AFE_RATE_192K = 14,
0038     MTK_AFE_RATE_260K = 15,
0039 };
0040 
0041 enum {
0042     MTK_AFE_DAI_MEMIF_RATE_8K = 0,
0043     MTK_AFE_DAI_MEMIF_RATE_16K = 1,
0044     MTK_AFE_DAI_MEMIF_RATE_32K = 2,
0045 };
0046 
0047 enum {
0048     MTK_AFE_PCM_RATE_8K = 0,
0049     MTK_AFE_PCM_RATE_16K = 1,
0050     MTK_AFE_PCM_RATE_32K = 2,
0051     MTK_AFE_PCM_RATE_48K = 3,
0052 };
0053 
0054 unsigned int mt6797_general_rate_transform(struct device *dev,
0055                        unsigned int rate)
0056 {
0057     switch (rate) {
0058     case 8000:
0059         return MTK_AFE_RATE_8K;
0060     case 11025:
0061         return MTK_AFE_RATE_11K;
0062     case 12000:
0063         return MTK_AFE_RATE_12K;
0064     case 16000:
0065         return MTK_AFE_RATE_16K;
0066     case 22050:
0067         return MTK_AFE_RATE_22K;
0068     case 24000:
0069         return MTK_AFE_RATE_24K;
0070     case 32000:
0071         return MTK_AFE_RATE_32K;
0072     case 44100:
0073         return MTK_AFE_RATE_44K;
0074     case 48000:
0075         return MTK_AFE_RATE_48K;
0076     case 88200:
0077         return MTK_AFE_RATE_88K;
0078     case 96000:
0079         return MTK_AFE_RATE_96K;
0080     case 130000:
0081         return MTK_AFE_RATE_130K;
0082     case 176400:
0083         return MTK_AFE_RATE_174K;
0084     case 192000:
0085         return MTK_AFE_RATE_192K;
0086     case 260000:
0087         return MTK_AFE_RATE_260K;
0088     default:
0089         dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
0090              __func__, rate, MTK_AFE_RATE_48K);
0091         return MTK_AFE_RATE_48K;
0092     }
0093 }
0094 
0095 static unsigned int dai_memif_rate_transform(struct device *dev,
0096                          unsigned int rate)
0097 {
0098     switch (rate) {
0099     case 8000:
0100         return MTK_AFE_DAI_MEMIF_RATE_8K;
0101     case 16000:
0102         return MTK_AFE_DAI_MEMIF_RATE_16K;
0103     case 32000:
0104         return MTK_AFE_DAI_MEMIF_RATE_32K;
0105     default:
0106         dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
0107              __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
0108         return MTK_AFE_DAI_MEMIF_RATE_16K;
0109     }
0110 }
0111 
0112 unsigned int mt6797_rate_transform(struct device *dev,
0113                    unsigned int rate, int aud_blk)
0114 {
0115     switch (aud_blk) {
0116     case MT6797_MEMIF_DAI:
0117     case MT6797_MEMIF_MOD_DAI:
0118         return dai_memif_rate_transform(dev, rate);
0119     default:
0120         return mt6797_general_rate_transform(dev, rate);
0121     }
0122 }
0123 
0124 static const struct snd_pcm_hardware mt6797_afe_hardware = {
0125     .info = SNDRV_PCM_INFO_MMAP |
0126         SNDRV_PCM_INFO_INTERLEAVED |
0127         SNDRV_PCM_INFO_MMAP_VALID,
0128     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0129            SNDRV_PCM_FMTBIT_S24_LE |
0130            SNDRV_PCM_FMTBIT_S32_LE,
0131     .period_bytes_min = 256,
0132     .period_bytes_max = 4 * 48 * 1024,
0133     .periods_min = 2,
0134     .periods_max = 256,
0135     .buffer_bytes_max = 8 * 48 * 1024,
0136     .fifo_size = 0,
0137 };
0138 
0139 static int mt6797_memif_fs(struct snd_pcm_substream *substream,
0140                unsigned int rate)
0141 {
0142     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0143     struct snd_soc_component *component =
0144         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0145     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0146     int id = asoc_rtd_to_cpu(rtd, 0)->id;
0147 
0148     return mt6797_rate_transform(afe->dev, rate, id);
0149 }
0150 
0151 static int mt6797_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
0152 {
0153     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0154     struct snd_soc_component *component =
0155         snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
0156     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0157 
0158     return mt6797_general_rate_transform(afe->dev, rate);
0159 }
0160 
0161 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
0162                SNDRV_PCM_RATE_88200 |\
0163                SNDRV_PCM_RATE_96000 |\
0164                SNDRV_PCM_RATE_176400 |\
0165                SNDRV_PCM_RATE_192000)
0166 
0167 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
0168                SNDRV_PCM_RATE_16000 |\
0169                SNDRV_PCM_RATE_32000)
0170 
0171 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0172              SNDRV_PCM_FMTBIT_S24_LE |\
0173              SNDRV_PCM_FMTBIT_S32_LE)
0174 
0175 static struct snd_soc_dai_driver mt6797_memif_dai_driver[] = {
0176     /* FE DAIs: memory intefaces to CPU */
0177     {
0178         .name = "DL1",
0179         .id = MT6797_MEMIF_DL1,
0180         .playback = {
0181             .stream_name = "DL1",
0182             .channels_min = 1,
0183             .channels_max = 2,
0184             .rates = MTK_PCM_RATES,
0185             .formats = MTK_PCM_FORMATS,
0186         },
0187         .ops = &mtk_afe_fe_ops,
0188     },
0189     {
0190         .name = "DL2",
0191         .id = MT6797_MEMIF_DL2,
0192         .playback = {
0193             .stream_name = "DL2",
0194             .channels_min = 1,
0195             .channels_max = 2,
0196             .rates = MTK_PCM_RATES,
0197             .formats = MTK_PCM_FORMATS,
0198         },
0199         .ops = &mtk_afe_fe_ops,
0200     },
0201     {
0202         .name = "DL3",
0203         .id = MT6797_MEMIF_DL3,
0204         .playback = {
0205             .stream_name = "DL3",
0206             .channels_min = 1,
0207             .channels_max = 2,
0208             .rates = MTK_PCM_RATES,
0209             .formats = MTK_PCM_FORMATS,
0210         },
0211         .ops = &mtk_afe_fe_ops,
0212     },
0213     {
0214         .name = "UL1",
0215         .id = MT6797_MEMIF_VUL12,
0216         .capture = {
0217             .stream_name = "UL1",
0218             .channels_min = 1,
0219             .channels_max = 2,
0220             .rates = MTK_PCM_RATES,
0221             .formats = MTK_PCM_FORMATS,
0222         },
0223         .ops = &mtk_afe_fe_ops,
0224     },
0225     {
0226         .name = "UL2",
0227         .id = MT6797_MEMIF_AWB,
0228         .capture = {
0229             .stream_name = "UL2",
0230             .channels_min = 1,
0231             .channels_max = 2,
0232             .rates = MTK_PCM_RATES,
0233             .formats = MTK_PCM_FORMATS,
0234         },
0235         .ops = &mtk_afe_fe_ops,
0236     },
0237     {
0238         .name = "UL3",
0239         .id = MT6797_MEMIF_VUL,
0240         .capture = {
0241             .stream_name = "UL3",
0242             .channels_min = 1,
0243             .channels_max = 2,
0244             .rates = MTK_PCM_RATES,
0245             .formats = MTK_PCM_FORMATS,
0246         },
0247         .ops = &mtk_afe_fe_ops,
0248     },
0249     {
0250         .name = "UL_MONO_1",
0251         .id = MT6797_MEMIF_MOD_DAI,
0252         .capture = {
0253             .stream_name = "UL_MONO_1",
0254             .channels_min = 1,
0255             .channels_max = 1,
0256             .rates = MTK_PCM_DAI_RATES,
0257             .formats = MTK_PCM_FORMATS,
0258         },
0259         .ops = &mtk_afe_fe_ops,
0260     },
0261     {
0262         .name = "UL_MONO_2",
0263         .id = MT6797_MEMIF_DAI,
0264         .capture = {
0265             .stream_name = "UL_MONO_2",
0266             .channels_min = 1,
0267             .channels_max = 1,
0268             .rates = MTK_PCM_DAI_RATES,
0269             .formats = MTK_PCM_FORMATS,
0270         },
0271         .ops = &mtk_afe_fe_ops,
0272     },
0273 };
0274 
0275 /* dma widget & routes*/
0276 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
0277     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
0278                     I_ADDA_UL_CH1, 1, 0),
0279 };
0280 
0281 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
0282     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
0283                     I_ADDA_UL_CH2, 1, 0),
0284 };
0285 
0286 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
0287     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
0288                     I_ADDA_UL_CH1, 1, 0),
0289     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
0290                     I_DL1_CH1, 1, 0),
0291     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
0292                     I_DL2_CH1, 1, 0),
0293     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
0294                     I_DL3_CH1, 1, 0),
0295 };
0296 
0297 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
0298     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
0299                     I_ADDA_UL_CH2, 1, 0),
0300     SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
0301                     I_DL1_CH2, 1, 0),
0302     SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
0303                     I_DL2_CH2, 1, 0),
0304     SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
0305                     I_DL3_CH2, 1, 0),
0306 };
0307 
0308 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
0309     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,
0310                     I_ADDA_UL_CH1, 1, 0),
0311 };
0312 
0313 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
0314     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,
0315                     I_ADDA_UL_CH2, 1, 0),
0316 };
0317 
0318 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
0319     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
0320                     I_ADDA_UL_CH1, 1, 0),
0321     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
0322                     I_ADDA_UL_CH2, 1, 0),
0323 };
0324 
0325 static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {
0326     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,
0327                     I_ADDA_UL_CH1, 1, 0),
0328     SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN11,
0329                     I_ADDA_UL_CH2, 1, 0),
0330 };
0331 
0332 static const struct snd_soc_dapm_widget mt6797_memif_widgets[] = {
0333     /* memif */
0334     SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
0335                memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
0336     SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
0337                memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
0338 
0339     SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
0340                memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
0341     SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
0342                memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
0343 
0344     SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
0345                memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
0346     SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
0347                memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
0348 
0349     SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
0350                memif_ul_mono_1_mix,
0351                ARRAY_SIZE(memif_ul_mono_1_mix)),
0352 
0353     SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,
0354                memif_ul_mono_2_mix,
0355                ARRAY_SIZE(memif_ul_mono_2_mix)),
0356 };
0357 
0358 static const struct snd_soc_dapm_route mt6797_memif_routes[] = {
0359     /* capture */
0360     {"UL1", NULL, "UL1_CH1"},
0361     {"UL1", NULL, "UL1_CH2"},
0362     {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0363     {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0364 
0365     {"UL2", NULL, "UL2_CH1"},
0366     {"UL2", NULL, "UL2_CH2"},
0367     {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0368     {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0369 
0370     {"UL3", NULL, "UL3_CH1"},
0371     {"UL3", NULL, "UL3_CH2"},
0372     {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0373     {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
0374 
0375     {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
0376     {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0377     {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
0378 
0379     {"UL_MONO_2", NULL, "UL_MONO_2_CH1"},
0380     {"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
0381     {"UL_MONO_2_CH1", "ADDA_UL_CH2", "ADDA Capture"},
0382 };
0383 
0384 static const struct snd_soc_component_driver mt6797_afe_pcm_dai_component = {
0385     .name = "mt6797-afe-pcm-dai",
0386 };
0387 
0388 static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
0389     [MT6797_MEMIF_DL1] = {
0390         .name = "DL1",
0391         .id = MT6797_MEMIF_DL1,
0392         .reg_ofs_base = AFE_DL1_BASE,
0393         .reg_ofs_cur = AFE_DL1_CUR,
0394         .fs_reg = AFE_DAC_CON1,
0395         .fs_shift = DL1_MODE_SFT,
0396         .fs_maskbit = DL1_MODE_MASK,
0397         .mono_reg = AFE_DAC_CON1,
0398         .mono_shift = DL1_DATA_SFT,
0399         .enable_reg = AFE_DAC_CON0,
0400         .enable_shift = DL1_ON_SFT,
0401         .hd_reg = AFE_MEMIF_HD_MODE,
0402         .hd_shift = DL1_HD_SFT,
0403         .agent_disable_reg = -1,
0404         .msb_reg = -1,
0405     },
0406     [MT6797_MEMIF_DL2] = {
0407         .name = "DL2",
0408         .id = MT6797_MEMIF_DL2,
0409         .reg_ofs_base = AFE_DL2_BASE,
0410         .reg_ofs_cur = AFE_DL2_CUR,
0411         .fs_reg = AFE_DAC_CON1,
0412         .fs_shift = DL2_MODE_SFT,
0413         .fs_maskbit = DL2_MODE_MASK,
0414         .mono_reg = AFE_DAC_CON1,
0415         .mono_shift = DL2_DATA_SFT,
0416         .enable_reg = AFE_DAC_CON0,
0417         .enable_shift = DL2_ON_SFT,
0418         .hd_reg = AFE_MEMIF_HD_MODE,
0419         .hd_shift = DL2_HD_SFT,
0420         .agent_disable_reg = -1,
0421         .msb_reg = -1,
0422     },
0423     [MT6797_MEMIF_DL3] = {
0424         .name = "DL3",
0425         .id = MT6797_MEMIF_DL3,
0426         .reg_ofs_base = AFE_DL3_BASE,
0427         .reg_ofs_cur = AFE_DL3_CUR,
0428         .fs_reg = AFE_DAC_CON0,
0429         .fs_shift = DL3_MODE_SFT,
0430         .fs_maskbit = DL3_MODE_MASK,
0431         .mono_reg = AFE_DAC_CON1,
0432         .mono_shift = DL3_DATA_SFT,
0433         .enable_reg = AFE_DAC_CON0,
0434         .enable_shift = DL3_ON_SFT,
0435         .hd_reg = AFE_MEMIF_HD_MODE,
0436         .hd_shift = DL3_HD_SFT,
0437         .agent_disable_reg = -1,
0438         .msb_reg = -1,
0439     },
0440     [MT6797_MEMIF_VUL] = {
0441         .name = "VUL",
0442         .id = MT6797_MEMIF_VUL,
0443         .reg_ofs_base = AFE_VUL_BASE,
0444         .reg_ofs_cur = AFE_VUL_CUR,
0445         .fs_reg = AFE_DAC_CON1,
0446         .fs_shift = VUL_MODE_SFT,
0447         .fs_maskbit = VUL_MODE_MASK,
0448         .mono_reg = AFE_DAC_CON1,
0449         .mono_shift = VUL_DATA_SFT,
0450         .enable_reg = AFE_DAC_CON0,
0451         .enable_shift = VUL_ON_SFT,
0452         .hd_reg = AFE_MEMIF_HD_MODE,
0453         .hd_shift = VUL_HD_SFT,
0454         .agent_disable_reg = -1,
0455         .msb_reg = -1,
0456     },
0457     [MT6797_MEMIF_AWB] = {
0458         .name = "AWB",
0459         .id = MT6797_MEMIF_AWB,
0460         .reg_ofs_base = AFE_AWB_BASE,
0461         .reg_ofs_cur = AFE_AWB_CUR,
0462         .fs_reg = AFE_DAC_CON1,
0463         .fs_shift = AWB_MODE_SFT,
0464         .fs_maskbit = AWB_MODE_MASK,
0465         .mono_reg = AFE_DAC_CON1,
0466         .mono_shift = AWB_DATA_SFT,
0467         .enable_reg = AFE_DAC_CON0,
0468         .enable_shift = AWB_ON_SFT,
0469         .hd_reg = AFE_MEMIF_HD_MODE,
0470         .hd_shift = AWB_HD_SFT,
0471         .agent_disable_reg = -1,
0472         .msb_reg = -1,
0473     },
0474     [MT6797_MEMIF_VUL12] = {
0475         .name = "VUL12",
0476         .id = MT6797_MEMIF_VUL12,
0477         .reg_ofs_base = AFE_VUL_D2_BASE,
0478         .reg_ofs_cur = AFE_VUL_D2_CUR,
0479         .fs_reg = AFE_DAC_CON0,
0480         .fs_shift = VUL_DATA2_MODE_SFT,
0481         .fs_maskbit = VUL_DATA2_MODE_MASK,
0482         .mono_reg = AFE_DAC_CON0,
0483         .mono_shift = VUL_DATA2_DATA_SFT,
0484         .enable_reg = AFE_DAC_CON0,
0485         .enable_shift = VUL_DATA2_ON_SFT,
0486         .hd_reg = AFE_MEMIF_HD_MODE,
0487         .hd_shift = VUL_DATA2_HD_SFT,
0488         .agent_disable_reg = -1,
0489         .msb_reg = -1,
0490     },
0491     [MT6797_MEMIF_DAI] = {
0492         .name = "DAI",
0493         .id = MT6797_MEMIF_DAI,
0494         .reg_ofs_base = AFE_DAI_BASE,
0495         .reg_ofs_cur = AFE_DAI_CUR,
0496         .fs_reg = AFE_DAC_CON0,
0497         .fs_shift = DAI_MODE_SFT,
0498         .fs_maskbit = DAI_MODE_MASK,
0499         .mono_reg = -1,
0500         .mono_shift = 0,
0501         .enable_reg = AFE_DAC_CON0,
0502         .enable_shift = DAI_ON_SFT,
0503         .hd_reg = AFE_MEMIF_HD_MODE,
0504         .hd_shift = DAI_HD_SFT,
0505         .agent_disable_reg = -1,
0506         .msb_reg = -1,
0507     },
0508     [MT6797_MEMIF_MOD_DAI] = {
0509         .name = "MOD_DAI",
0510         .id = MT6797_MEMIF_MOD_DAI,
0511         .reg_ofs_base = AFE_MOD_DAI_BASE,
0512         .reg_ofs_cur = AFE_MOD_DAI_CUR,
0513         .fs_reg = AFE_DAC_CON1,
0514         .fs_shift = MOD_DAI_MODE_SFT,
0515         .fs_maskbit = MOD_DAI_MODE_MASK,
0516         .mono_reg = -1,
0517         .mono_shift = 0,
0518         .enable_reg = AFE_DAC_CON0,
0519         .enable_shift = MOD_DAI_ON_SFT,
0520         .hd_reg = AFE_MEMIF_HD_MODE,
0521         .hd_shift = MOD_DAI_HD_SFT,
0522         .agent_disable_reg = -1,
0523         .msb_reg = -1,
0524     },
0525 };
0526 
0527 static const struct mtk_base_irq_data irq_data[MT6797_IRQ_NUM] = {
0528     [MT6797_IRQ_1] = {
0529         .id = MT6797_IRQ_1,
0530         .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
0531         .irq_cnt_shift = AFE_IRQ_MCU_CNT1_SFT,
0532         .irq_cnt_maskbit = AFE_IRQ_MCU_CNT1_MASK,
0533         .irq_fs_reg = AFE_IRQ_MCU_CON,
0534         .irq_fs_shift = IRQ1_MCU_MODE_SFT,
0535         .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
0536         .irq_en_reg = AFE_IRQ_MCU_CON,
0537         .irq_en_shift = IRQ1_MCU_ON_SFT,
0538         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0539         .irq_clr_shift = IRQ1_MCU_CLR_SFT,
0540     },
0541     [MT6797_IRQ_2] = {
0542         .id = MT6797_IRQ_2,
0543         .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
0544         .irq_cnt_shift = AFE_IRQ_MCU_CNT2_SFT,
0545         .irq_cnt_maskbit = AFE_IRQ_MCU_CNT2_MASK,
0546         .irq_fs_reg = AFE_IRQ_MCU_CON,
0547         .irq_fs_shift = IRQ2_MCU_MODE_SFT,
0548         .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
0549         .irq_en_reg = AFE_IRQ_MCU_CON,
0550         .irq_en_shift = IRQ2_MCU_ON_SFT,
0551         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0552         .irq_clr_shift = IRQ2_MCU_CLR_SFT,
0553     },
0554     [MT6797_IRQ_3] = {
0555         .id = MT6797_IRQ_3,
0556         .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
0557         .irq_cnt_shift = AFE_IRQ_MCU_CNT3_SFT,
0558         .irq_cnt_maskbit = AFE_IRQ_MCU_CNT3_MASK,
0559         .irq_fs_reg = AFE_IRQ_MCU_CON,
0560         .irq_fs_shift = IRQ3_MCU_MODE_SFT,
0561         .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
0562         .irq_en_reg = AFE_IRQ_MCU_CON,
0563         .irq_en_shift = IRQ3_MCU_ON_SFT,
0564         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0565         .irq_clr_shift = IRQ3_MCU_CLR_SFT,
0566     },
0567     [MT6797_IRQ_4] = {
0568         .id = MT6797_IRQ_4,
0569         .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
0570         .irq_cnt_shift = AFE_IRQ_MCU_CNT4_SFT,
0571         .irq_cnt_maskbit = AFE_IRQ_MCU_CNT4_MASK,
0572         .irq_fs_reg = AFE_IRQ_MCU_CON,
0573         .irq_fs_shift = IRQ4_MCU_MODE_SFT,
0574         .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
0575         .irq_en_reg = AFE_IRQ_MCU_CON,
0576         .irq_en_shift = IRQ4_MCU_ON_SFT,
0577         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0578         .irq_clr_shift = IRQ4_MCU_CLR_SFT,
0579     },
0580     [MT6797_IRQ_7] = {
0581         .id = MT6797_IRQ_7,
0582         .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
0583         .irq_cnt_shift = AFE_IRQ_MCU_CNT7_SFT,
0584         .irq_cnt_maskbit = AFE_IRQ_MCU_CNT7_MASK,
0585         .irq_fs_reg = AFE_IRQ_MCU_CON,
0586         .irq_fs_shift = IRQ7_MCU_MODE_SFT,
0587         .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
0588         .irq_en_reg = AFE_IRQ_MCU_CON,
0589         .irq_en_shift = IRQ7_MCU_ON_SFT,
0590         .irq_clr_reg = AFE_IRQ_MCU_CLR,
0591         .irq_clr_shift = IRQ7_MCU_CLR_SFT,
0592     },
0593 };
0594 
0595 static const struct regmap_config mt6797_afe_regmap_config = {
0596     .reg_bits = 32,
0597     .reg_stride = 4,
0598     .val_bits = 32,
0599     .max_register = AFE_MAX_REGISTER,
0600 };
0601 
0602 static irqreturn_t mt6797_afe_irq_handler(int irq_id, void *dev)
0603 {
0604     struct mtk_base_afe *afe = dev;
0605     struct mtk_base_afe_irq *irq;
0606     unsigned int status;
0607     unsigned int mcu_en;
0608     int ret;
0609     int i;
0610     irqreturn_t irq_ret = IRQ_HANDLED;
0611 
0612     /* get irq that is sent to MCU */
0613     regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
0614 
0615     ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
0616     if (ret || (status & mcu_en) == 0) {
0617         dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
0618             __func__, ret, status, mcu_en);
0619 
0620         /* only clear IRQ which is sent to MCU */
0621         status = mcu_en & AFE_IRQ_STATUS_BITS;
0622 
0623         irq_ret = IRQ_NONE;
0624         goto err_irq;
0625     }
0626 
0627     for (i = 0; i < MT6797_MEMIF_NUM; i++) {
0628         struct mtk_base_afe_memif *memif = &afe->memif[i];
0629 
0630         if (!memif->substream)
0631             continue;
0632 
0633         irq = &afe->irqs[memif->irq_usage];
0634 
0635         if (status & (1 << irq->irq_data->irq_en_shift))
0636             snd_pcm_period_elapsed(memif->substream);
0637     }
0638 
0639 err_irq:
0640     /* clear irq */
0641     regmap_write(afe->regmap,
0642              AFE_IRQ_MCU_CLR,
0643              status & AFE_IRQ_STATUS_BITS);
0644 
0645     return irq_ret;
0646 }
0647 
0648 static int mt6797_afe_runtime_suspend(struct device *dev)
0649 {
0650     struct mtk_base_afe *afe = dev_get_drvdata(dev);
0651     unsigned int afe_on_retm;
0652     int retry = 0;
0653 
0654     /* disable AFE */
0655     regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
0656     do {
0657         regmap_read(afe->regmap, AFE_DAC_CON0, &afe_on_retm);
0658         if ((afe_on_retm & AFE_ON_RETM_MASK_SFT) == 0)
0659             break;
0660 
0661         udelay(10);
0662     } while (++retry < 100000);
0663 
0664     if (retry)
0665         dev_warn(afe->dev, "%s(), retry %d\n", __func__, retry);
0666 
0667     /* make sure all irq status are cleared */
0668     regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
0669 
0670     return mt6797_afe_disable_clock(afe);
0671 }
0672 
0673 static int mt6797_afe_runtime_resume(struct device *dev)
0674 {
0675     struct mtk_base_afe *afe = dev_get_drvdata(dev);
0676     int ret;
0677 
0678     ret = mt6797_afe_enable_clock(afe);
0679     if (ret)
0680         return ret;
0681 
0682     /* irq signal to mcu only */
0683     regmap_write(afe->regmap, AFE_IRQ_MCU_EN, AFE_IRQ_MCU_EN_MASK_SFT);
0684 
0685     /* force all memif use normal mode */
0686     regmap_update_bits(afe->regmap, AFE_MEMIF_HDALIGN,
0687                0x7ff << 16, 0x7ff << 16);
0688     /* force cpu use normal mode when access sram data */
0689     regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
0690                CPU_COMPACT_MODE_MASK_SFT, 0);
0691     /* force cpu use 8_24 format when writing 32bit data */
0692     regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
0693                CPU_HD_ALIGN_MASK_SFT, 0);
0694 
0695     /* set all output port to 24bit */
0696     regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
0697                0x3fffffff, 0x3fffffff);
0698 
0699     /* enable AFE */
0700     regmap_update_bits(afe->regmap, AFE_DAC_CON0,
0701                AFE_ON_MASK_SFT,
0702                0x1 << AFE_ON_SFT);
0703 
0704     return 0;
0705 }
0706 
0707 static int mt6797_afe_component_probe(struct snd_soc_component *component)
0708 {
0709     return mtk_afe_add_sub_dai_control(component);
0710 }
0711 
0712 static const struct snd_soc_component_driver mt6797_afe_component = {
0713     .name       = AFE_PCM_NAME,
0714     .probe      = mt6797_afe_component_probe,
0715     .pointer    = mtk_afe_pcm_pointer,
0716     .pcm_construct  = mtk_afe_pcm_new,
0717 };
0718 
0719 static int mt6797_dai_memif_register(struct mtk_base_afe *afe)
0720 {
0721     struct mtk_base_afe_dai *dai;
0722 
0723     dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
0724     if (!dai)
0725         return -ENOMEM;
0726 
0727     list_add(&dai->list, &afe->sub_dais);
0728 
0729     dai->dai_drivers = mt6797_memif_dai_driver;
0730     dai->num_dai_drivers = ARRAY_SIZE(mt6797_memif_dai_driver);
0731 
0732     dai->dapm_widgets = mt6797_memif_widgets;
0733     dai->num_dapm_widgets = ARRAY_SIZE(mt6797_memif_widgets);
0734     dai->dapm_routes = mt6797_memif_routes;
0735     dai->num_dapm_routes = ARRAY_SIZE(mt6797_memif_routes);
0736     return 0;
0737 }
0738 
0739 typedef int (*dai_register_cb)(struct mtk_base_afe *);
0740 static const dai_register_cb dai_register_cbs[] = {
0741     mt6797_dai_adda_register,
0742     mt6797_dai_pcm_register,
0743     mt6797_dai_hostless_register,
0744     mt6797_dai_memif_register,
0745 };
0746 
0747 static int mt6797_afe_pcm_dev_probe(struct platform_device *pdev)
0748 {
0749     struct mtk_base_afe *afe;
0750     struct mt6797_afe_private *afe_priv;
0751     struct device *dev;
0752     int i, irq_id, ret;
0753 
0754     afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
0755     if (!afe)
0756         return -ENOMEM;
0757 
0758     afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
0759                       GFP_KERNEL);
0760     if (!afe->platform_priv)
0761         return -ENOMEM;
0762 
0763     afe_priv = afe->platform_priv;
0764     afe->dev = &pdev->dev;
0765     dev = afe->dev;
0766 
0767     /* initial audio related clock */
0768     ret = mt6797_init_clock(afe);
0769     if (ret) {
0770         dev_err(dev, "init clock error\n");
0771         return ret;
0772     }
0773 
0774     /* regmap init */
0775     afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
0776     if (IS_ERR(afe->base_addr))
0777         return PTR_ERR(afe->base_addr);
0778 
0779     afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
0780                         &mt6797_afe_regmap_config);
0781     if (IS_ERR(afe->regmap))
0782         return PTR_ERR(afe->regmap);
0783 
0784     /* init memif */
0785     afe->memif_size = MT6797_MEMIF_NUM;
0786     afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
0787                   GFP_KERNEL);
0788     if (!afe->memif)
0789         return -ENOMEM;
0790 
0791     for (i = 0; i < afe->memif_size; i++) {
0792         afe->memif[i].data = &memif_data[i];
0793         afe->memif[i].irq_usage = -1;
0794     }
0795 
0796     mutex_init(&afe->irq_alloc_lock);
0797 
0798     /* irq initialize */
0799     afe->irqs_size = MT6797_IRQ_NUM;
0800     afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
0801                  GFP_KERNEL);
0802     if (!afe->irqs)
0803         return -ENOMEM;
0804 
0805     for (i = 0; i < afe->irqs_size; i++)
0806         afe->irqs[i].irq_data = &irq_data[i];
0807 
0808     /* request irq */
0809     irq_id = platform_get_irq(pdev, 0);
0810     if (irq_id < 0)
0811         return irq_id;
0812 
0813     ret = devm_request_irq(dev, irq_id, mt6797_afe_irq_handler,
0814                    IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
0815     if (ret) {
0816         dev_err(dev, "could not request_irq for asys-isr\n");
0817         return ret;
0818     }
0819 
0820     /* init sub_dais */
0821     INIT_LIST_HEAD(&afe->sub_dais);
0822 
0823     for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
0824         ret = dai_register_cbs[i](afe);
0825         if (ret) {
0826             dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
0827                  i, ret);
0828             return ret;
0829         }
0830     }
0831 
0832     /* init dai_driver and component_driver */
0833     ret = mtk_afe_combine_sub_dai(afe);
0834     if (ret) {
0835         dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
0836              ret);
0837         return ret;
0838     }
0839 
0840     afe->mtk_afe_hardware = &mt6797_afe_hardware;
0841     afe->memif_fs = mt6797_memif_fs;
0842     afe->irq_fs = mt6797_irq_fs;
0843 
0844     afe->runtime_resume = mt6797_afe_runtime_resume;
0845     afe->runtime_suspend = mt6797_afe_runtime_suspend;
0846 
0847     platform_set_drvdata(pdev, afe);
0848 
0849     pm_runtime_enable(dev);
0850     if (!pm_runtime_enabled(dev))
0851         goto err_pm_disable;
0852     pm_runtime_get_sync(&pdev->dev);
0853 
0854     /* register component */
0855     ret = devm_snd_soc_register_component(dev, &mt6797_afe_component,
0856                           NULL, 0);
0857     if (ret) {
0858         dev_warn(dev, "err_platform\n");
0859         goto err_pm_disable;
0860     }
0861 
0862     ret = devm_snd_soc_register_component(afe->dev,
0863                      &mt6797_afe_pcm_dai_component,
0864                      afe->dai_drivers,
0865                      afe->num_dai_drivers);
0866     if (ret) {
0867         dev_warn(dev, "err_dai_component\n");
0868         goto err_pm_disable;
0869     }
0870 
0871     return 0;
0872 
0873 err_pm_disable:
0874     pm_runtime_disable(dev);
0875 
0876     return ret;
0877 }
0878 
0879 static int mt6797_afe_pcm_dev_remove(struct platform_device *pdev)
0880 {
0881     pm_runtime_disable(&pdev->dev);
0882     if (!pm_runtime_status_suspended(&pdev->dev))
0883         mt6797_afe_runtime_suspend(&pdev->dev);
0884     pm_runtime_put_sync(&pdev->dev);
0885 
0886     return 0;
0887 }
0888 
0889 static const struct of_device_id mt6797_afe_pcm_dt_match[] = {
0890     { .compatible = "mediatek,mt6797-audio", },
0891     {},
0892 };
0893 MODULE_DEVICE_TABLE(of, mt6797_afe_pcm_dt_match);
0894 
0895 static const struct dev_pm_ops mt6797_afe_pm_ops = {
0896     SET_RUNTIME_PM_OPS(mt6797_afe_runtime_suspend,
0897                mt6797_afe_runtime_resume, NULL)
0898 };
0899 
0900 static struct platform_driver mt6797_afe_pcm_driver = {
0901     .driver = {
0902            .name = "mt6797-audio",
0903            .of_match_table = mt6797_afe_pcm_dt_match,
0904            .pm = &mt6797_afe_pm_ops,
0905     },
0906     .probe = mt6797_afe_pcm_dev_probe,
0907     .remove = mt6797_afe_pcm_dev_remove,
0908 };
0909 
0910 module_platform_driver(mt6797_afe_pcm_driver);
0911 
0912 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 6797");
0913 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
0914 MODULE_LICENSE("GPL v2");
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