mediatek/mt6797/mt6797-afe-clk.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt6797-afe-clk.c  --  Mediatek 6797 afe clock ctrl
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007
0008 #include <linux/clk.h>
0009
0010 #include "mt6797-afe-common.h"
0011 #include "mt6797-afe-clk.h"
0012
0013 enum {
0014     CLK_INFRA_SYS_AUD,
0015     CLK_INFRA_SYS_AUD_26M,
0016     CLK_TOP_MUX_AUD,
0017     CLK_TOP_MUX_AUD_BUS,
0018     CLK_TOP_SYSPLL3_D4,
0019     CLK_TOP_SYSPLL1_D4,
0020     CLK_CLK26M,
0021     CLK_NUM
0022 };
0023
0024 static const char *aud_clks[CLK_NUM] = {
0025     [CLK_INFRA_SYS_AUD] = "infra_sys_audio_clk",
0026     [CLK_INFRA_SYS_AUD_26M] = "infra_sys_audio_26m",
0027     [CLK_TOP_MUX_AUD] = "top_mux_audio",
0028     [CLK_TOP_MUX_AUD_BUS] = "top_mux_aud_intbus",
0029     [CLK_TOP_SYSPLL3_D4] = "top_sys_pll3_d4",
0030     [CLK_TOP_SYSPLL1_D4] = "top_sys_pll1_d4",
0031     [CLK_CLK26M] = "top_clk26m_clk",
0032 };
0033
0034 int mt6797_init_clock(struct mtk_base_afe *afe)
0035 {
0036     struct mt6797_afe_private *afe_priv = afe->platform_priv;
0037     int i;
0038
0039     afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
0040                      GFP_KERNEL);
0041     if (!afe_priv->clk)
0042         return -ENOMEM;
0043
0044     for (i = 0; i < CLK_NUM; i++) {
0045         afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
0046         if (IS_ERR(afe_priv->clk[i])) {
0047             dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
0048                 __func__, aud_clks[i],
0049                 PTR_ERR(afe_priv->clk[i]));
0050             return PTR_ERR(afe_priv->clk[i]);
0051         }
0052     }
0053
0054     return 0;
0055 }
0056
0057 int mt6797_afe_enable_clock(struct mtk_base_afe *afe)
0058 {
0059     struct mt6797_afe_private *afe_priv = afe->platform_priv;
0060     int ret;
0061
0062     ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);
0063     if (ret) {
0064         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0065             __func__, aud_clks[CLK_INFRA_SYS_AUD], ret);
0066         goto CLK_INFRA_SYS_AUDIO_ERR;
0067     }
0068
0069     ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
0070     if (ret) {
0071         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0072             __func__, aud_clks[CLK_INFRA_SYS_AUD_26M], ret);
0073         goto CLK_INFRA_SYS_AUD_26M_ERR;
0074     }
0075
0076     ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);
0077     if (ret) {
0078         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0079             __func__, aud_clks[CLK_TOP_MUX_AUD], ret);
0080         goto CLK_MUX_AUDIO_ERR;
0081     }
0082
0083     ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],
0084                  afe_priv->clk[CLK_CLK26M]);
0085     if (ret) {
0086         dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
0087             __func__, aud_clks[CLK_TOP_MUX_AUD],
0088             aud_clks[CLK_CLK26M], ret);
0089         goto CLK_MUX_AUDIO_ERR;
0090     }
0091
0092     ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
0093     if (ret) {
0094         dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
0095             __func__, aud_clks[CLK_TOP_MUX_AUD_BUS], ret);
0096         goto CLK_MUX_AUDIO_INTBUS_ERR;
0097     }
0098
0099     return ret;
0100
0101 CLK_MUX_AUDIO_INTBUS_ERR:
0102     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
0103 CLK_MUX_AUDIO_ERR:
0104     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
0105 CLK_INFRA_SYS_AUD_26M_ERR:
0106     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
0107 CLK_INFRA_SYS_AUDIO_ERR:
0108     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
0109
0110     return 0;
0111 }
0112
0113 int mt6797_afe_disable_clock(struct mtk_base_afe *afe)
0114 {
0115     struct mt6797_afe_private *afe_priv = afe->platform_priv;
0116
0117     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
0118     clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
0119     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
0120     clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
0121
0122     return 0;
0123 }