mediatek/mt2701/mt2701-reg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt2701-reg.h  --  Mediatek 2701 audio driver reg definition
0004  *
0005  * Copyright (c) 2016 MediaTek Inc.
0006  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
0007  */
0008
0009 #ifndef _MT2701_REG_H_
0010 #define _MT2701_REG_H_
0011
0012 #define AUDIO_TOP_CON0 0x0000
0013 #define AUDIO_TOP_CON4 0x0010
0014 #define AUDIO_TOP_CON5 0x0014
0015 #define AFE_DAIBT_CON0 0x001c
0016 #define AFE_MRGIF_CON 0x003c
0017 #define ASMI_TIMING_CON1 0x0100
0018 #define ASMO_TIMING_CON1 0x0104
0019 #define PWR1_ASM_CON1 0x0108
0020 #define ASYS_TOP_CON 0x0600
0021 #define ASYS_I2SIN1_CON 0x0604
0022 #define ASYS_I2SIN2_CON 0x0608
0023 #define ASYS_I2SIN3_CON 0x060c
0024 #define ASYS_I2SIN4_CON 0x0610
0025 #define ASYS_I2SIN5_CON 0x0614
0026 #define ASYS_I2SO1_CON 0x061C
0027 #define ASYS_I2SO2_CON 0x0620
0028 #define ASYS_I2SO3_CON 0x0624
0029 #define ASYS_I2SO4_CON 0x0628
0030 #define ASYS_I2SO5_CON 0x062c
0031 #define PWR2_TOP_CON 0x0634
0032 #define AFE_CONN0 0x06c0
0033 #define AFE_CONN1 0x06c4
0034 #define AFE_CONN2 0x06c8
0035 #define AFE_CONN3 0x06cc
0036 #define AFE_CONN14 0x06f8
0037 #define AFE_CONN15 0x06fc
0038 #define AFE_CONN16 0x0700
0039 #define AFE_CONN17 0x0704
0040 #define AFE_CONN18 0x0708
0041 #define AFE_CONN19 0x070c
0042 #define AFE_CONN20 0x0710
0043 #define AFE_CONN21 0x0714
0044 #define AFE_CONN22 0x0718
0045 #define AFE_CONN23 0x071c
0046 #define AFE_CONN24 0x0720
0047 #define AFE_CONN41 0x0764
0048 #define ASYS_IRQ1_CON 0x0780
0049 #define ASYS_IRQ2_CON 0x0784
0050 #define ASYS_IRQ3_CON 0x0788
0051 #define ASYS_IRQ_CLR 0x07c0
0052 #define ASYS_IRQ_STATUS 0x07c4
0053 #define PWR2_ASM_CON1 0x1070
0054 #define AFE_DAC_CON0 0x1200
0055 #define AFE_DAC_CON1 0x1204
0056 #define AFE_DAC_CON2 0x1208
0057 #define AFE_DAC_CON3 0x120c
0058 #define AFE_DAC_CON4 0x1210
0059 #define AFE_MEMIF_HD_CON1 0x121c
0060 #define AFE_MEMIF_PBUF_SIZE 0x1238
0061 #define AFE_MEMIF_HD_CON0 0x123c
0062 #define AFE_DL1_BASE 0x1240
0063 #define AFE_DL1_CUR 0x1244
0064 #define AFE_DL2_BASE 0x1250
0065 #define AFE_DL2_CUR 0x1254
0066 #define AFE_DL3_BASE 0x1260
0067 #define AFE_DL3_CUR 0x1264
0068 #define AFE_DL4_BASE 0x1270
0069 #define AFE_DL4_CUR 0x1274
0070 #define AFE_DL5_BASE 0x1280
0071 #define AFE_DL5_CUR 0x1284
0072 #define AFE_DLMCH_BASE 0x12a0
0073 #define AFE_DLMCH_CUR 0x12a4
0074 #define AFE_ARB1_BASE 0x12b0
0075 #define AFE_ARB1_CUR 0x12b4
0076 #define AFE_VUL_BASE 0x1300
0077 #define AFE_VUL_CUR 0x130c
0078 #define AFE_UL2_BASE 0x1310
0079 #define AFE_UL2_END 0x1318
0080 #define AFE_UL2_CUR 0x131c
0081 #define AFE_UL3_BASE 0x1320
0082 #define AFE_UL3_END 0x1328
0083 #define AFE_UL3_CUR 0x132c
0084 #define AFE_UL4_BASE 0x1330
0085 #define AFE_UL4_END 0x1338
0086 #define AFE_UL4_CUR 0x133c
0087 #define AFE_UL5_BASE 0x1340
0088 #define AFE_UL5_END 0x1348
0089 #define AFE_UL5_CUR 0x134c
0090 #define AFE_DAI_BASE 0x1370
0091 #define AFE_DAI_CUR 0x137c
0092
0093 /* AFE_DAIBT_CON0 (0x001c) */
0094 #define AFE_DAIBT_CON0_DAIBT_EN     (0x1 << 0)
0095 #define AFE_DAIBT_CON0_BT_FUNC_EN   (0x1 << 1)
0096 #define AFE_DAIBT_CON0_BT_FUNC_RDY  (0x1 << 3)
0097 #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN  (0x1 << 9)
0098 #define AFE_DAIBT_CON0_MRG_USE      (0x1 << 12)
0099
0100 /* PWR1_ASM_CON1 (0x0108) */
0101 #define PWR1_ASM_CON1_INIT_VAL      (0x492)
0102
0103 /* AFE_MRGIF_CON (0x003c) */
0104 #define AFE_MRGIF_CON_MRG_EN        (0x1 << 0)
0105 #define AFE_MRGIF_CON_MRG_I2S_EN    (0x1 << 16)
0106 #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
0107 #define AFE_MRGIF_CON_I2S_MODE_32K  (0x4 << 20)
0108
0109 /* ASYS_TOP_CON (0x0600) */
0110 #define ASYS_TOP_CON_ASYS_TIMING_ON     (0x3 << 0)
0111
0112 /* PWR2_ASM_CON1 (0x1070) */
0113 #define PWR2_ASM_CON1_INIT_VAL      (0x492492)
0114
0115 /* AFE_DAC_CON0 (0x1200) */
0116 #define AFE_DAC_CON0_AFE_ON     (0x1 << 0)
0117
0118 /* AFE_MEMIF_PBUF_SIZE (0x1238) */
0119 #define AFE_MEMIF_PBUF_SIZE_DLM_MASK        (0x1 << 29)
0120 #define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29)
0121 #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29)
0122 #define DLMCH_BIT_WIDTH_MASK            (0x1 << 28)
0123 #define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK     (0xf << 24)
0124 #define AFE_MEMIF_PBUF_SIZE_DLM_CH(x)       ((x) << 24)
0125 #define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK   (0x3 << 12)
0126 #define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES     (0x1 << 12)
0127
0128 /* I2S in/out register bit control */
0129 #define ASYS_I2S_CON_FS         (0x1f << 8)
0130 #define ASYS_I2S_CON_FS_SET(x)      ((x) << 8)
0131 #define ASYS_I2S_CON_RESET      (0x1 << 30)
0132 #define ASYS_I2S_CON_I2S_EN     (0x1 << 0)
0133 #define ASYS_I2S_CON_ONE_HEART_MODE (0x1 << 16)
0134 #define ASYS_I2S_CON_I2S_COUPLE_MODE    (0x1 << 17)
0135 /* 0:EIAJ 1:I2S */
0136 #define ASYS_I2S_CON_I2S_MODE       (0x1 << 3)
0137 #define ASYS_I2S_CON_WIDE_MODE      (0x1 << 1)
0138 #define ASYS_I2S_CON_WIDE_MODE_SET(x)   ((x) << 1)
0139 #define ASYS_I2S_IN_PHASE_FIX       (0x1 << 31)
0140
0141 #endif