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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Mediatek ALSA SoC AFE platform driver for 2701
0004  *
0005  * Copyright (c) 2016 MediaTek Inc.
0006  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
0007  *     Ir Lian <ir.lian@mediatek.com>
0008  *     Ryder Lee <ryder.lee@mediatek.com>
0009  */
0010 
0011 #include <linux/delay.h>
0012 #include <linux/module.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_device.h>
0017 #include <linux/pm_runtime.h>
0018 
0019 #include "mt2701-afe-common.h"
0020 #include "mt2701-afe-clock-ctrl.h"
0021 #include "../common/mtk-afe-platform-driver.h"
0022 #include "../common/mtk-afe-fe-dai.h"
0023 
0024 static const struct snd_pcm_hardware mt2701_afe_hardware = {
0025     .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
0026         | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
0027     .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
0028            | SNDRV_PCM_FMTBIT_S32_LE,
0029     .period_bytes_min = 1024,
0030     .period_bytes_max = 1024 * 256,
0031     .periods_min = 4,
0032     .periods_max = 1024,
0033     .buffer_bytes_max = 1024 * 1024,
0034     .fifo_size = 0,
0035 };
0036 
0037 struct mt2701_afe_rate {
0038     unsigned int rate;
0039     unsigned int regvalue;
0040 };
0041 
0042 static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
0043     { .rate = 8000, .regvalue = 0 },
0044     { .rate = 12000, .regvalue = 1 },
0045     { .rate = 16000, .regvalue = 2 },
0046     { .rate = 24000, .regvalue = 3 },
0047     { .rate = 32000, .regvalue = 4 },
0048     { .rate = 48000, .regvalue = 5 },
0049     { .rate = 96000, .regvalue = 6 },
0050     { .rate = 192000, .regvalue = 7 },
0051     { .rate = 384000, .regvalue = 8 },
0052     { .rate = 7350, .regvalue = 16 },
0053     { .rate = 11025, .regvalue = 17 },
0054     { .rate = 14700, .regvalue = 18 },
0055     { .rate = 22050, .regvalue = 19 },
0056     { .rate = 29400, .regvalue = 20 },
0057     { .rate = 44100, .regvalue = 21 },
0058     { .rate = 88200, .regvalue = 22 },
0059     { .rate = 176400, .regvalue = 23 },
0060     { .rate = 352800, .regvalue = 24 },
0061 };
0062 
0063 static const unsigned int mt2701_afe_backup_list[] = {
0064     AUDIO_TOP_CON0,
0065     AUDIO_TOP_CON4,
0066     AUDIO_TOP_CON5,
0067     ASYS_TOP_CON,
0068     AFE_CONN0,
0069     AFE_CONN1,
0070     AFE_CONN2,
0071     AFE_CONN3,
0072     AFE_CONN15,
0073     AFE_CONN16,
0074     AFE_CONN17,
0075     AFE_CONN18,
0076     AFE_CONN19,
0077     AFE_CONN20,
0078     AFE_CONN21,
0079     AFE_CONN22,
0080     AFE_DAC_CON0,
0081     AFE_MEMIF_PBUF_SIZE,
0082 };
0083 
0084 static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
0085 {
0086     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0087     int val = num - MT2701_IO_I2S;
0088 
0089     if (val < 0 || val >= afe_priv->soc->i2s_num) {
0090         dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
0091             __func__, num, val);
0092         return -EINVAL;
0093     }
0094     return val;
0095 }
0096 
0097 static int mt2701_afe_i2s_fs(unsigned int sample_rate)
0098 {
0099     int i;
0100 
0101     for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
0102         if (mt2701_afe_i2s_rates[i].rate == sample_rate)
0103             return mt2701_afe_i2s_rates[i].regvalue;
0104 
0105     return -EINVAL;
0106 }
0107 
0108 static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
0109                   struct snd_soc_dai *dai)
0110 {
0111     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0112     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0113     int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
0114     bool mode = afe_priv->soc->has_one_heart_mode;
0115 
0116     if (i2s_num < 0)
0117         return i2s_num;
0118 
0119     return mt2701_afe_enable_mclk(afe, mode ? 1 : i2s_num);
0120 }
0121 
0122 static int mt2701_afe_i2s_path_disable(struct mtk_base_afe *afe,
0123                        struct mt2701_i2s_path *i2s_path,
0124                        int stream_dir)
0125 {
0126     const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
0127 
0128     if (--i2s_path->on[stream_dir] < 0)
0129         i2s_path->on[stream_dir] = 0;
0130 
0131     if (i2s_path->on[stream_dir])
0132         return 0;
0133 
0134     /* disable i2s */
0135     regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
0136                ASYS_I2S_CON_I2S_EN, 0);
0137 
0138     mt2701_afe_disable_i2s(afe, i2s_path, stream_dir);
0139 
0140     return 0;
0141 }
0142 
0143 static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
0144                     struct snd_soc_dai *dai)
0145 {
0146     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0147     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0148     int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
0149     struct mt2701_i2s_path *i2s_path;
0150     bool mode = afe_priv->soc->has_one_heart_mode;
0151 
0152     if (i2s_num < 0)
0153         return;
0154 
0155     i2s_path = &afe_priv->i2s_path[i2s_num];
0156 
0157     if (i2s_path->occupied[substream->stream])
0158         i2s_path->occupied[substream->stream] = 0;
0159     else
0160         goto exit;
0161 
0162     mt2701_afe_i2s_path_disable(afe, i2s_path, substream->stream);
0163 
0164     /* need to disable i2s-out path when disable i2s-in */
0165     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0166         mt2701_afe_i2s_path_disable(afe, i2s_path, !substream->stream);
0167 
0168 exit:
0169     /* disable mclk */
0170     mt2701_afe_disable_mclk(afe, mode ? 1 : i2s_num);
0171 }
0172 
0173 static int mt2701_i2s_path_enable(struct mtk_base_afe *afe,
0174                   struct mt2701_i2s_path *i2s_path,
0175                   int stream_dir, int rate)
0176 {
0177     const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
0178     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0179     int reg, fs, w_len = 1; /* now we support bck 64bits only */
0180     unsigned int mask, val;
0181 
0182     /* no need to enable if already done */
0183     if (++i2s_path->on[stream_dir] != 1)
0184         return 0;
0185 
0186     fs = mt2701_afe_i2s_fs(rate);
0187 
0188     mask = ASYS_I2S_CON_FS |
0189            ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
0190            ASYS_I2S_CON_I2S_MODE |
0191            ASYS_I2S_CON_WIDE_MODE;
0192 
0193     val = ASYS_I2S_CON_FS_SET(fs) |
0194           ASYS_I2S_CON_I2S_MODE |
0195           ASYS_I2S_CON_WIDE_MODE_SET(w_len);
0196 
0197     if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
0198         mask |= ASYS_I2S_IN_PHASE_FIX;
0199         val |= ASYS_I2S_IN_PHASE_FIX;
0200         reg = ASMI_TIMING_CON1;
0201     } else {
0202         if (afe_priv->soc->has_one_heart_mode) {
0203             mask |= ASYS_I2S_CON_ONE_HEART_MODE;
0204             val |= ASYS_I2S_CON_ONE_HEART_MODE;
0205         }
0206         reg = ASMO_TIMING_CON1;
0207     }
0208 
0209     regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
0210 
0211     regmap_update_bits(afe->regmap, reg,
0212                i2s_data->i2s_asrc_fs_mask
0213                << i2s_data->i2s_asrc_fs_shift,
0214                fs << i2s_data->i2s_asrc_fs_shift);
0215 
0216     /* enable i2s */
0217     mt2701_afe_enable_i2s(afe, i2s_path, stream_dir);
0218 
0219     /* reset i2s hw status before enable */
0220     regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
0221                ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
0222     udelay(1);
0223     regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
0224                ASYS_I2S_CON_RESET, 0);
0225     udelay(1);
0226     regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
0227                ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
0228     return 0;
0229 }
0230 
0231 static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
0232                   struct snd_soc_dai *dai)
0233 {
0234     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0235     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0236     int ret, i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
0237     struct mt2701_i2s_path *i2s_path;
0238     bool mode = afe_priv->soc->has_one_heart_mode;
0239 
0240     if (i2s_num < 0)
0241         return i2s_num;
0242 
0243     i2s_path = &afe_priv->i2s_path[i2s_num];
0244 
0245     if (i2s_path->occupied[substream->stream])
0246         return -EBUSY;
0247 
0248     ret = mt2701_mclk_configuration(afe, mode ? 1 : i2s_num);
0249     if (ret)
0250         return ret;
0251 
0252     i2s_path->occupied[substream->stream] = 1;
0253 
0254     /* need to enable i2s-out path when enable i2s-in */
0255     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0256         mt2701_i2s_path_enable(afe, i2s_path, !substream->stream,
0257                        substream->runtime->rate);
0258 
0259     mt2701_i2s_path_enable(afe, i2s_path, substream->stream,
0260                    substream->runtime->rate);
0261 
0262     return 0;
0263 }
0264 
0265 static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0266                      unsigned int freq, int dir)
0267 {
0268     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0269     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0270     int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
0271     bool mode = afe_priv->soc->has_one_heart_mode;
0272 
0273     if (i2s_num < 0)
0274         return i2s_num;
0275 
0276     /* mclk */
0277     if (dir == SND_SOC_CLOCK_IN) {
0278         dev_warn(dai->dev, "The SoCs doesn't support mclk input\n");
0279         return -EINVAL;
0280     }
0281 
0282     afe_priv->i2s_path[mode ? 1 : i2s_num].mclk_rate = freq;
0283 
0284     return 0;
0285 }
0286 
0287 static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
0288                 struct snd_soc_dai *dai)
0289 {
0290     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0291     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0292     int ret;
0293 
0294     ret = mt2701_enable_btmrg_clk(afe);
0295     if (ret)
0296         return ret;
0297 
0298     afe_priv->mrg_enable[substream->stream] = 1;
0299 
0300     return 0;
0301 }
0302 
0303 static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
0304                   struct snd_pcm_hw_params *params,
0305                   struct snd_soc_dai *dai)
0306 {
0307     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0308     int stream_fs;
0309     u32 val, msk;
0310 
0311     stream_fs = params_rate(params);
0312 
0313     if (stream_fs != 8000 && stream_fs != 16000) {
0314         dev_err(afe->dev, "unsupported rate %d\n", stream_fs);
0315         return -EINVAL;
0316     }
0317 
0318     regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
0319                AFE_MRGIF_CON_I2S_MODE_MASK,
0320                AFE_MRGIF_CON_I2S_MODE_32K);
0321 
0322     val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
0323           | AFE_DAIBT_CON0_MRG_USE;
0324     msk = val;
0325 
0326     if (stream_fs == 16000)
0327         val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
0328 
0329     msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
0330 
0331     regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
0332 
0333     regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
0334                AFE_DAIBT_CON0_DAIBT_EN,
0335                AFE_DAIBT_CON0_DAIBT_EN);
0336     regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
0337                AFE_MRGIF_CON_MRG_I2S_EN,
0338                AFE_MRGIF_CON_MRG_I2S_EN);
0339     regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
0340                AFE_MRGIF_CON_MRG_EN,
0341                AFE_MRGIF_CON_MRG_EN);
0342     return 0;
0343 }
0344 
0345 static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
0346                   struct snd_soc_dai *dai)
0347 {
0348     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0349     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0350 
0351     /* if the other direction stream is not occupied */
0352     if (!afe_priv->mrg_enable[!substream->stream]) {
0353         regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
0354                    AFE_DAIBT_CON0_DAIBT_EN, 0);
0355         regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
0356                    AFE_MRGIF_CON_MRG_EN, 0);
0357         regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
0358                    AFE_MRGIF_CON_MRG_I2S_EN, 0);
0359         mt2701_disable_btmrg_clk(afe);
0360     }
0361 
0362     afe_priv->mrg_enable[substream->stream] = 0;
0363 }
0364 
0365 static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
0366                     struct snd_soc_dai *dai)
0367 {
0368     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0369     struct mtk_base_afe_memif *memif_tmp;
0370     int stream_dir = substream->stream;
0371 
0372     /* can't run single DL & DLM at the same time */
0373     if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
0374         memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
0375         if (memif_tmp->substream) {
0376             dev_warn(afe->dev, "memif is not available");
0377             return -EBUSY;
0378         }
0379     }
0380 
0381     return mtk_afe_fe_startup(substream, dai);
0382 }
0383 
0384 static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
0385                       struct snd_pcm_hw_params *params,
0386                       struct snd_soc_dai *dai)
0387 {
0388     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0389     int stream_dir = substream->stream;
0390 
0391     /* single DL use PAIR_INTERLEAVE */
0392     if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
0393         regmap_update_bits(afe->regmap,
0394                    AFE_MEMIF_PBUF_SIZE,
0395                    AFE_MEMIF_PBUF_SIZE_DLM_MASK,
0396                    AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
0397 
0398     return mtk_afe_fe_hw_params(substream, params, dai);
0399 }
0400 
0401 static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
0402                  struct snd_soc_dai *dai)
0403 {
0404     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0405     struct mtk_base_afe_memif *memif_tmp;
0406     const struct mtk_base_memif_data *memif_data;
0407     int i;
0408 
0409     for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
0410         memif_tmp = &afe->memif[i];
0411         if (memif_tmp->substream)
0412             return -EBUSY;
0413     }
0414 
0415     /* enable agent for all signal DL (due to hw design) */
0416     for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
0417         memif_data = afe->memif[i].data;
0418         regmap_update_bits(afe->regmap,
0419                    memif_data->agent_disable_reg,
0420                    1 << memif_data->agent_disable_shift,
0421                    0 << memif_data->agent_disable_shift);
0422     }
0423 
0424     return mtk_afe_fe_startup(substream, dai);
0425 }
0426 
0427 static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
0428                    struct snd_soc_dai *dai)
0429 {
0430     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0431     const struct mtk_base_memif_data *memif_data;
0432     int i;
0433 
0434     for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
0435         memif_data = afe->memif[i].data;
0436         regmap_update_bits(afe->regmap,
0437                    memif_data->agent_disable_reg,
0438                    1 << memif_data->agent_disable_shift,
0439                    1 << memif_data->agent_disable_shift);
0440     }
0441 
0442     return mtk_afe_fe_shutdown(substream, dai);
0443 }
0444 
0445 static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
0446                    struct snd_pcm_hw_params *params,
0447                    struct snd_soc_dai *dai)
0448 {
0449     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0450     int channels = params_channels(params);
0451 
0452     regmap_update_bits(afe->regmap,
0453                AFE_MEMIF_PBUF_SIZE,
0454                AFE_MEMIF_PBUF_SIZE_DLM_MASK,
0455                AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
0456     regmap_update_bits(afe->regmap,
0457                AFE_MEMIF_PBUF_SIZE,
0458                AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
0459                AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
0460     regmap_update_bits(afe->regmap,
0461                AFE_MEMIF_PBUF_SIZE,
0462                AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
0463                AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
0464 
0465     return mtk_afe_fe_hw_params(substream, params, dai);
0466 }
0467 
0468 static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
0469                  int cmd, struct snd_soc_dai *dai)
0470 {
0471     struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
0472     struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
0473 
0474     switch (cmd) {
0475     case SNDRV_PCM_TRIGGER_START:
0476     case SNDRV_PCM_TRIGGER_RESUME:
0477         regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
0478                    1 << memif_tmp->data->enable_shift,
0479                    1 << memif_tmp->data->enable_shift);
0480         mtk_afe_fe_trigger(substream, cmd, dai);
0481         return 0;
0482     case SNDRV_PCM_TRIGGER_STOP:
0483     case SNDRV_PCM_TRIGGER_SUSPEND:
0484         mtk_afe_fe_trigger(substream, cmd, dai);
0485         regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
0486                    1 << memif_tmp->data->enable_shift, 0);
0487 
0488         return 0;
0489     default:
0490         return -EINVAL;
0491     }
0492 }
0493 
0494 static int mt2701_memif_fs(struct snd_pcm_substream *substream,
0495                unsigned int rate)
0496 {
0497     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0498     int fs;
0499 
0500     if (asoc_rtd_to_cpu(rtd, 0)->id != MT2701_MEMIF_ULBT)
0501         fs = mt2701_afe_i2s_fs(rate);
0502     else
0503         fs = (rate == 16000 ? 1 : 0);
0504 
0505     return fs;
0506 }
0507 
0508 static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
0509 {
0510     return mt2701_afe_i2s_fs(rate);
0511 }
0512 
0513 /* FE DAIs */
0514 static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
0515     .startup    = mt2701_simple_fe_startup,
0516     .shutdown   = mtk_afe_fe_shutdown,
0517     .hw_params  = mt2701_simple_fe_hw_params,
0518     .hw_free    = mtk_afe_fe_hw_free,
0519     .prepare    = mtk_afe_fe_prepare,
0520     .trigger    = mtk_afe_fe_trigger,
0521 };
0522 
0523 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
0524     .startup    = mt2701_dlm_fe_startup,
0525     .shutdown   = mt2701_dlm_fe_shutdown,
0526     .hw_params  = mt2701_dlm_fe_hw_params,
0527     .hw_free    = mtk_afe_fe_hw_free,
0528     .prepare    = mtk_afe_fe_prepare,
0529     .trigger    = mt2701_dlm_fe_trigger,
0530 };
0531 
0532 /* I2S BE DAIs */
0533 static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
0534     .startup    = mt2701_afe_i2s_startup,
0535     .shutdown   = mt2701_afe_i2s_shutdown,
0536     .prepare    = mt2701_afe_i2s_prepare,
0537     .set_sysclk = mt2701_afe_i2s_set_sysclk,
0538 };
0539 
0540 /* MRG BE DAIs */
0541 static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
0542     .startup = mt2701_btmrg_startup,
0543     .shutdown = mt2701_btmrg_shutdown,
0544     .hw_params = mt2701_btmrg_hw_params,
0545 };
0546 
0547 static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
0548     /* FE DAIs: memory intefaces to CPU */
0549     {
0550         .name = "PCMO0",
0551         .id = MT2701_MEMIF_DL1,
0552         .playback = {
0553             .stream_name = "DL1",
0554             .channels_min = 1,
0555             .channels_max = 2,
0556             .rates = SNDRV_PCM_RATE_8000_192000,
0557             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0558                 | SNDRV_PCM_FMTBIT_S24_LE
0559                 | SNDRV_PCM_FMTBIT_S32_LE)
0560         },
0561         .ops = &mt2701_single_memif_dai_ops,
0562     },
0563     {
0564         .name = "PCM_multi",
0565         .id = MT2701_MEMIF_DLM,
0566         .playback = {
0567             .stream_name = "DLM",
0568             .channels_min = 1,
0569             .channels_max = 8,
0570             .rates = SNDRV_PCM_RATE_8000_192000,
0571             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0572                 | SNDRV_PCM_FMTBIT_S24_LE
0573                 | SNDRV_PCM_FMTBIT_S32_LE)
0574 
0575         },
0576         .ops = &mt2701_dlm_memif_dai_ops,
0577     },
0578     {
0579         .name = "PCM0",
0580         .id = MT2701_MEMIF_UL1,
0581         .capture = {
0582             .stream_name = "UL1",
0583             .channels_min = 1,
0584             .channels_max = 2,
0585             .rates = SNDRV_PCM_RATE_8000_48000,
0586             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0587                 | SNDRV_PCM_FMTBIT_S24_LE
0588                 | SNDRV_PCM_FMTBIT_S32_LE)
0589         },
0590         .ops = &mt2701_single_memif_dai_ops,
0591     },
0592     {
0593         .name = "PCM1",
0594         .id = MT2701_MEMIF_UL2,
0595         .capture = {
0596             .stream_name = "UL2",
0597             .channels_min = 1,
0598             .channels_max = 2,
0599             .rates = SNDRV_PCM_RATE_8000_192000,
0600             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0601                 | SNDRV_PCM_FMTBIT_S24_LE
0602                 | SNDRV_PCM_FMTBIT_S32_LE)
0603 
0604         },
0605         .ops = &mt2701_single_memif_dai_ops,
0606     },
0607     {
0608         .name = "PCM_BT_DL",
0609         .id = MT2701_MEMIF_DLBT,
0610         .playback = {
0611             .stream_name = "DLBT",
0612             .channels_min = 1,
0613             .channels_max = 1,
0614             .rates = (SNDRV_PCM_RATE_8000
0615                 | SNDRV_PCM_RATE_16000),
0616             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0617         },
0618         .ops = &mt2701_single_memif_dai_ops,
0619     },
0620     {
0621         .name = "PCM_BT_UL",
0622         .id = MT2701_MEMIF_ULBT,
0623         .capture = {
0624             .stream_name = "ULBT",
0625             .channels_min = 1,
0626             .channels_max = 1,
0627             .rates = (SNDRV_PCM_RATE_8000
0628                 | SNDRV_PCM_RATE_16000),
0629             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0630         },
0631         .ops = &mt2701_single_memif_dai_ops,
0632     },
0633     /* BE DAIs */
0634     {
0635         .name = "I2S0",
0636         .id = MT2701_IO_I2S,
0637         .playback = {
0638             .stream_name = "I2S0 Playback",
0639             .channels_min = 1,
0640             .channels_max = 2,
0641             .rates = SNDRV_PCM_RATE_8000_192000,
0642             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0643                 | SNDRV_PCM_FMTBIT_S24_LE
0644                 | SNDRV_PCM_FMTBIT_S32_LE)
0645 
0646         },
0647         .capture = {
0648             .stream_name = "I2S0 Capture",
0649             .channels_min = 1,
0650             .channels_max = 2,
0651             .rates = SNDRV_PCM_RATE_8000_192000,
0652             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0653                 | SNDRV_PCM_FMTBIT_S24_LE
0654                 | SNDRV_PCM_FMTBIT_S32_LE)
0655 
0656         },
0657         .ops = &mt2701_afe_i2s_ops,
0658         .symmetric_rate = 1,
0659     },
0660     {
0661         .name = "I2S1",
0662         .id = MT2701_IO_2ND_I2S,
0663         .playback = {
0664             .stream_name = "I2S1 Playback",
0665             .channels_min = 1,
0666             .channels_max = 2,
0667             .rates = SNDRV_PCM_RATE_8000_192000,
0668             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0669                 | SNDRV_PCM_FMTBIT_S24_LE
0670                 | SNDRV_PCM_FMTBIT_S32_LE)
0671             },
0672         .capture = {
0673             .stream_name = "I2S1 Capture",
0674             .channels_min = 1,
0675             .channels_max = 2,
0676             .rates = SNDRV_PCM_RATE_8000_192000,
0677             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0678                 | SNDRV_PCM_FMTBIT_S24_LE
0679                 | SNDRV_PCM_FMTBIT_S32_LE)
0680             },
0681         .ops = &mt2701_afe_i2s_ops,
0682         .symmetric_rate = 1,
0683     },
0684     {
0685         .name = "I2S2",
0686         .id = MT2701_IO_3RD_I2S,
0687         .playback = {
0688             .stream_name = "I2S2 Playback",
0689             .channels_min = 1,
0690             .channels_max = 2,
0691             .rates = SNDRV_PCM_RATE_8000_192000,
0692             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0693                 | SNDRV_PCM_FMTBIT_S24_LE
0694                 | SNDRV_PCM_FMTBIT_S32_LE)
0695             },
0696         .capture = {
0697             .stream_name = "I2S2 Capture",
0698             .channels_min = 1,
0699             .channels_max = 2,
0700             .rates = SNDRV_PCM_RATE_8000_192000,
0701             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0702                 | SNDRV_PCM_FMTBIT_S24_LE
0703                 | SNDRV_PCM_FMTBIT_S32_LE)
0704             },
0705         .ops = &mt2701_afe_i2s_ops,
0706         .symmetric_rate = 1,
0707     },
0708     {
0709         .name = "I2S3",
0710         .id = MT2701_IO_4TH_I2S,
0711         .playback = {
0712             .stream_name = "I2S3 Playback",
0713             .channels_min = 1,
0714             .channels_max = 2,
0715             .rates = SNDRV_PCM_RATE_8000_192000,
0716             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0717                 | SNDRV_PCM_FMTBIT_S24_LE
0718                 | SNDRV_PCM_FMTBIT_S32_LE)
0719             },
0720         .capture = {
0721             .stream_name = "I2S3 Capture",
0722             .channels_min = 1,
0723             .channels_max = 2,
0724             .rates = SNDRV_PCM_RATE_8000_192000,
0725             .formats = (SNDRV_PCM_FMTBIT_S16_LE
0726                 | SNDRV_PCM_FMTBIT_S24_LE
0727                 | SNDRV_PCM_FMTBIT_S32_LE)
0728             },
0729         .ops = &mt2701_afe_i2s_ops,
0730         .symmetric_rate = 1,
0731     },
0732     {
0733         .name = "MRG BT",
0734         .id = MT2701_IO_MRG,
0735         .playback = {
0736             .stream_name = "BT Playback",
0737             .channels_min = 1,
0738             .channels_max = 1,
0739             .rates = (SNDRV_PCM_RATE_8000
0740                 | SNDRV_PCM_RATE_16000),
0741             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0742         },
0743         .capture = {
0744             .stream_name = "BT Capture",
0745             .channels_min = 1,
0746             .channels_max = 1,
0747             .rates = (SNDRV_PCM_RATE_8000
0748                 | SNDRV_PCM_RATE_16000),
0749             .formats = SNDRV_PCM_FMTBIT_S16_LE,
0750         },
0751         .ops = &mt2701_btmrg_ops,
0752         .symmetric_rate = 1,
0753     }
0754 };
0755 
0756 static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
0757     SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
0758 };
0759 
0760 static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
0761     SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
0762 };
0763 
0764 static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
0765     SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
0766 };
0767 
0768 static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
0769     SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
0770 };
0771 
0772 static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
0773     SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
0774 };
0775 
0776 static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
0777     SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
0778 };
0779 
0780 static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
0781     SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
0782 };
0783 
0784 static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
0785     SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
0786 };
0787 
0788 static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
0789     SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
0790 };
0791 
0792 static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
0793     SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
0794 };
0795 
0796 static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
0797     SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
0798 };
0799 
0800 static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
0801     SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
0802 };
0803 
0804 static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
0805     SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
0806 };
0807 
0808 static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
0809     SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
0810 };
0811 
0812 static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
0813     SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
0814 };
0815 
0816 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
0817     SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
0818                     ASYS_I2SO1_CON, 26, 1, 0),
0819 };
0820 
0821 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
0822     SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
0823                     ASYS_I2SO2_CON, 26, 1, 0),
0824 };
0825 
0826 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
0827     SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
0828                     PWR2_TOP_CON, 17, 1, 0),
0829 };
0830 
0831 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
0832     SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
0833                     PWR2_TOP_CON, 18, 1, 0),
0834 };
0835 
0836 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
0837     /* inter-connections */
0838     SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
0839     SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
0840     SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
0841                ARRAY_SIZE(mt2701_afe_i02_mix)),
0842     SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
0843     SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
0844     SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
0845     SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
0846     SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
0847     SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
0848     SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
0849     SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
0850     SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
0851     SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
0852     SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
0853 
0854     SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
0855                ARRAY_SIZE(mt2701_afe_o00_mix)),
0856     SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
0857                ARRAY_SIZE(mt2701_afe_o01_mix)),
0858     SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
0859                ARRAY_SIZE(mt2701_afe_o02_mix)),
0860     SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
0861                ARRAY_SIZE(mt2701_afe_o03_mix)),
0862     SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
0863                ARRAY_SIZE(mt2701_afe_o14_mix)),
0864     SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
0865                ARRAY_SIZE(mt2701_afe_o15_mix)),
0866     SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
0867                ARRAY_SIZE(mt2701_afe_o16_mix)),
0868     SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
0869                ARRAY_SIZE(mt2701_afe_o17_mix)),
0870     SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
0871                ARRAY_SIZE(mt2701_afe_o18_mix)),
0872     SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
0873                ARRAY_SIZE(mt2701_afe_o19_mix)),
0874     SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
0875                ARRAY_SIZE(mt2701_afe_o20_mix)),
0876     SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
0877                ARRAY_SIZE(mt2701_afe_o21_mix)),
0878     SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
0879                ARRAY_SIZE(mt2701_afe_o22_mix)),
0880     SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
0881                ARRAY_SIZE(mt2701_afe_o31_mix)),
0882 
0883     SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
0884                mt2701_afe_multi_ch_out_i2s0,
0885                ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
0886     SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
0887                mt2701_afe_multi_ch_out_i2s1,
0888                ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
0889     SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
0890                mt2701_afe_multi_ch_out_i2s2,
0891                ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
0892     SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
0893                mt2701_afe_multi_ch_out_i2s3,
0894                ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
0895 };
0896 
0897 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
0898     {"I12", NULL, "DL1"},
0899     {"I13", NULL, "DL1"},
0900     {"I35", NULL, "DLBT"},
0901 
0902     {"I2S0 Playback", NULL, "O15"},
0903     {"I2S0 Playback", NULL, "O16"},
0904     {"I2S1 Playback", NULL, "O17"},
0905     {"I2S1 Playback", NULL, "O18"},
0906     {"I2S2 Playback", NULL, "O19"},
0907     {"I2S2 Playback", NULL, "O20"},
0908     {"I2S3 Playback", NULL, "O21"},
0909     {"I2S3 Playback", NULL, "O22"},
0910     {"BT Playback", NULL, "O31"},
0911 
0912     {"UL1", NULL, "O00"},
0913     {"UL1", NULL, "O01"},
0914     {"UL2", NULL, "O02"},
0915     {"UL2", NULL, "O03"},
0916     {"ULBT", NULL, "O14"},
0917 
0918     {"I00", NULL, "I2S0 Capture"},
0919     {"I01", NULL, "I2S0 Capture"},
0920     {"I02", NULL, "I2S1 Capture"},
0921     {"I03", NULL, "I2S1 Capture"},
0922     /* I02,03 link to UL2, also need to open I2S0 */
0923     {"I02", "I2S0 Switch", "I2S0 Capture"},
0924 
0925     {"I26", NULL, "BT Capture"},
0926 
0927     {"I12I13", "Multich I2S0 Out Switch", "DLM"},
0928     {"I14I15", "Multich I2S1 Out Switch", "DLM"},
0929     {"I16I17", "Multich I2S2 Out Switch", "DLM"},
0930     {"I18I19", "Multich I2S3 Out Switch", "DLM"},
0931 
0932     { "I12", NULL, "I12I13" },
0933     { "I13", NULL, "I12I13" },
0934     { "I14", NULL, "I14I15" },
0935     { "I15", NULL, "I14I15" },
0936     { "I16", NULL, "I16I17" },
0937     { "I17", NULL, "I16I17" },
0938     { "I18", NULL, "I18I19" },
0939     { "I19", NULL, "I18I19" },
0940 
0941     { "O00", "I00 Switch", "I00" },
0942     { "O01", "I01 Switch", "I01" },
0943     { "O02", "I02 Switch", "I02" },
0944     { "O03", "I03 Switch", "I03" },
0945     { "O14", "I26 Switch", "I26" },
0946     { "O15", "I12 Switch", "I12" },
0947     { "O16", "I13 Switch", "I13" },
0948     { "O17", "I14 Switch", "I14" },
0949     { "O18", "I15 Switch", "I15" },
0950     { "O19", "I16 Switch", "I16" },
0951     { "O20", "I17 Switch", "I17" },
0952     { "O21", "I18 Switch", "I18" },
0953     { "O22", "I19 Switch", "I19" },
0954     { "O31", "I35 Switch", "I35" },
0955 };
0956 
0957 static int mt2701_afe_pcm_probe(struct snd_soc_component *component)
0958 {
0959     struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
0960 
0961     snd_soc_component_init_regmap(component, afe->regmap);
0962 
0963     return 0;
0964 }
0965 
0966 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
0967     .probe = mt2701_afe_pcm_probe,
0968     .name = "mt2701-afe-pcm-dai",
0969     .dapm_widgets = mt2701_afe_pcm_widgets,
0970     .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
0971     .dapm_routes = mt2701_afe_pcm_routes,
0972     .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
0973     .suspend = mtk_afe_suspend,
0974     .resume = mtk_afe_resume,
0975 };
0976 
0977 static const struct mtk_base_memif_data memif_data_array[MT2701_MEMIF_NUM] = {
0978     {
0979         .name = "DL1",
0980         .id = MT2701_MEMIF_DL1,
0981         .reg_ofs_base = AFE_DL1_BASE,
0982         .reg_ofs_cur = AFE_DL1_CUR,
0983         .fs_reg = AFE_DAC_CON1,
0984         .fs_shift = 0,
0985         .fs_maskbit = 0x1f,
0986         .mono_reg = AFE_DAC_CON3,
0987         .mono_shift = 16,
0988         .enable_reg = AFE_DAC_CON0,
0989         .enable_shift = 1,
0990         .hd_reg = AFE_MEMIF_HD_CON0,
0991         .hd_shift = 0,
0992         .agent_disable_reg = AUDIO_TOP_CON5,
0993         .agent_disable_shift = 6,
0994         .msb_reg = -1,
0995     },
0996     {
0997         .name = "DL2",
0998         .id = MT2701_MEMIF_DL2,
0999         .reg_ofs_base = AFE_DL2_BASE,
1000         .reg_ofs_cur = AFE_DL2_CUR,
1001         .fs_reg = AFE_DAC_CON1,
1002         .fs_shift = 5,
1003         .fs_maskbit = 0x1f,
1004         .mono_reg = AFE_DAC_CON3,
1005         .mono_shift = 17,
1006         .enable_reg = AFE_DAC_CON0,
1007         .enable_shift = 2,
1008         .hd_reg = AFE_MEMIF_HD_CON0,
1009         .hd_shift = 2,
1010         .agent_disable_reg = AUDIO_TOP_CON5,
1011         .agent_disable_shift = 7,
1012         .msb_reg = -1,
1013     },
1014     {
1015         .name = "DL3",
1016         .id = MT2701_MEMIF_DL3,
1017         .reg_ofs_base = AFE_DL3_BASE,
1018         .reg_ofs_cur = AFE_DL3_CUR,
1019         .fs_reg = AFE_DAC_CON1,
1020         .fs_shift = 10,
1021         .fs_maskbit = 0x1f,
1022         .mono_reg = AFE_DAC_CON3,
1023         .mono_shift = 18,
1024         .enable_reg = AFE_DAC_CON0,
1025         .enable_shift = 3,
1026         .hd_reg = AFE_MEMIF_HD_CON0,
1027         .hd_shift = 4,
1028         .agent_disable_reg = AUDIO_TOP_CON5,
1029         .agent_disable_shift = 8,
1030         .msb_reg = -1,
1031     },
1032     {
1033         .name = "DL4",
1034         .id = MT2701_MEMIF_DL4,
1035         .reg_ofs_base = AFE_DL4_BASE,
1036         .reg_ofs_cur = AFE_DL4_CUR,
1037         .fs_reg = AFE_DAC_CON1,
1038         .fs_shift = 15,
1039         .fs_maskbit = 0x1f,
1040         .mono_reg = AFE_DAC_CON3,
1041         .mono_shift = 19,
1042         .enable_reg = AFE_DAC_CON0,
1043         .enable_shift = 4,
1044         .hd_reg = AFE_MEMIF_HD_CON0,
1045         .hd_shift = 6,
1046         .agent_disable_reg = AUDIO_TOP_CON5,
1047         .agent_disable_shift = 9,
1048         .msb_reg = -1,
1049     },
1050     {
1051         .name = "DL5",
1052         .id = MT2701_MEMIF_DL5,
1053         .reg_ofs_base = AFE_DL5_BASE,
1054         .reg_ofs_cur = AFE_DL5_CUR,
1055         .fs_reg = AFE_DAC_CON1,
1056         .fs_shift = 20,
1057         .fs_maskbit = 0x1f,
1058         .mono_reg = AFE_DAC_CON3,
1059         .mono_shift = 20,
1060         .enable_reg = AFE_DAC_CON0,
1061         .enable_shift = 5,
1062         .hd_reg = AFE_MEMIF_HD_CON0,
1063         .hd_shift = 8,
1064         .agent_disable_reg = AUDIO_TOP_CON5,
1065         .agent_disable_shift = 10,
1066         .msb_reg = -1,
1067     },
1068     {
1069         .name = "DLM",
1070         .id = MT2701_MEMIF_DLM,
1071         .reg_ofs_base = AFE_DLMCH_BASE,
1072         .reg_ofs_cur = AFE_DLMCH_CUR,
1073         .fs_reg = AFE_DAC_CON1,
1074         .fs_shift = 0,
1075         .fs_maskbit = 0x1f,
1076         .mono_reg = -1,
1077         .mono_shift = -1,
1078         .enable_reg = AFE_DAC_CON0,
1079         .enable_shift = 7,
1080         .hd_reg = AFE_MEMIF_PBUF_SIZE,
1081         .hd_shift = 28,
1082         .agent_disable_reg = AUDIO_TOP_CON5,
1083         .agent_disable_shift = 12,
1084         .msb_reg = -1,
1085     },
1086     {
1087         .name = "UL1",
1088         .id = MT2701_MEMIF_UL1,
1089         .reg_ofs_base = AFE_VUL_BASE,
1090         .reg_ofs_cur = AFE_VUL_CUR,
1091         .fs_reg = AFE_DAC_CON2,
1092         .fs_shift = 0,
1093         .fs_maskbit = 0x1f,
1094         .mono_reg = AFE_DAC_CON4,
1095         .mono_shift = 0,
1096         .enable_reg = AFE_DAC_CON0,
1097         .enable_shift = 10,
1098         .hd_reg = AFE_MEMIF_HD_CON1,
1099         .hd_shift = 0,
1100         .agent_disable_reg = AUDIO_TOP_CON5,
1101         .agent_disable_shift = 0,
1102         .msb_reg = -1,
1103     },
1104     {
1105         .name = "UL2",
1106         .id = MT2701_MEMIF_UL2,
1107         .reg_ofs_base = AFE_UL2_BASE,
1108         .reg_ofs_cur = AFE_UL2_CUR,
1109         .fs_reg = AFE_DAC_CON2,
1110         .fs_shift = 5,
1111         .fs_maskbit = 0x1f,
1112         .mono_reg = AFE_DAC_CON4,
1113         .mono_shift = 2,
1114         .enable_reg = AFE_DAC_CON0,
1115         .enable_shift = 11,
1116         .hd_reg = AFE_MEMIF_HD_CON1,
1117         .hd_shift = 2,
1118         .agent_disable_reg = AUDIO_TOP_CON5,
1119         .agent_disable_shift = 1,
1120         .msb_reg = -1,
1121     },
1122     {
1123         .name = "UL3",
1124         .id = MT2701_MEMIF_UL3,
1125         .reg_ofs_base = AFE_UL3_BASE,
1126         .reg_ofs_cur = AFE_UL3_CUR,
1127         .fs_reg = AFE_DAC_CON2,
1128         .fs_shift = 10,
1129         .fs_maskbit = 0x1f,
1130         .mono_reg = AFE_DAC_CON4,
1131         .mono_shift = 4,
1132         .enable_reg = AFE_DAC_CON0,
1133         .enable_shift = 12,
1134         .hd_reg = AFE_MEMIF_HD_CON0,
1135         .hd_shift = 0,
1136         .agent_disable_reg = AUDIO_TOP_CON5,
1137         .agent_disable_shift = 2,
1138         .msb_reg = -1,
1139     },
1140     {
1141         .name = "UL4",
1142         .id = MT2701_MEMIF_UL4,
1143         .reg_ofs_base = AFE_UL4_BASE,
1144         .reg_ofs_cur = AFE_UL4_CUR,
1145         .fs_reg = AFE_DAC_CON2,
1146         .fs_shift = 15,
1147         .fs_maskbit = 0x1f,
1148         .mono_reg = AFE_DAC_CON4,
1149         .mono_shift = 6,
1150         .enable_reg = AFE_DAC_CON0,
1151         .enable_shift = 13,
1152         .hd_reg = AFE_MEMIF_HD_CON0,
1153         .hd_shift = 6,
1154         .agent_disable_reg = AUDIO_TOP_CON5,
1155         .agent_disable_shift = 3,
1156         .msb_reg = -1,
1157     },
1158     {
1159         .name = "UL5",
1160         .id = MT2701_MEMIF_UL5,
1161         .reg_ofs_base = AFE_UL5_BASE,
1162         .reg_ofs_cur = AFE_UL5_CUR,
1163         .fs_reg = AFE_DAC_CON2,
1164         .fs_shift = 20,
1165         .mono_reg = AFE_DAC_CON4,
1166         .mono_shift = 8,
1167         .fs_maskbit = 0x1f,
1168         .enable_reg = AFE_DAC_CON0,
1169         .enable_shift = 14,
1170         .hd_reg = AFE_MEMIF_HD_CON0,
1171         .hd_shift = 8,
1172         .agent_disable_reg = AUDIO_TOP_CON5,
1173         .agent_disable_shift = 4,
1174         .msb_reg = -1,
1175     },
1176     {
1177         .name = "DLBT",
1178         .id = MT2701_MEMIF_DLBT,
1179         .reg_ofs_base = AFE_ARB1_BASE,
1180         .reg_ofs_cur = AFE_ARB1_CUR,
1181         .fs_reg = AFE_DAC_CON3,
1182         .fs_shift = 10,
1183         .fs_maskbit = 0x1f,
1184         .mono_reg = AFE_DAC_CON3,
1185         .mono_shift = 22,
1186         .enable_reg = AFE_DAC_CON0,
1187         .enable_shift = 8,
1188         .hd_reg = AFE_MEMIF_HD_CON0,
1189         .hd_shift = 14,
1190         .agent_disable_reg = AUDIO_TOP_CON5,
1191         .agent_disable_shift = 13,
1192         .msb_reg = -1,
1193     },
1194     {
1195         .name = "ULBT",
1196         .id = MT2701_MEMIF_ULBT,
1197         .reg_ofs_base = AFE_DAI_BASE,
1198         .reg_ofs_cur = AFE_DAI_CUR,
1199         .fs_reg = AFE_DAC_CON2,
1200         .fs_shift = 30,
1201         .fs_maskbit = 0x1,
1202         .mono_reg = -1,
1203         .mono_shift = -1,
1204         .enable_reg = AFE_DAC_CON0,
1205         .enable_shift = 17,
1206         .hd_reg = AFE_MEMIF_HD_CON1,
1207         .hd_shift = 20,
1208         .agent_disable_reg = AUDIO_TOP_CON5,
1209         .agent_disable_shift = 16,
1210         .msb_reg = -1,
1211     },
1212 };
1213 
1214 static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
1215     {
1216         .id = MT2701_IRQ_ASYS_IRQ1,
1217         .irq_cnt_reg = ASYS_IRQ1_CON,
1218         .irq_cnt_shift = 0,
1219         .irq_cnt_maskbit = 0xffffff,
1220         .irq_fs_reg = ASYS_IRQ1_CON,
1221         .irq_fs_shift = 24,
1222         .irq_fs_maskbit = 0x1f,
1223         .irq_en_reg = ASYS_IRQ1_CON,
1224         .irq_en_shift = 31,
1225         .irq_clr_reg = ASYS_IRQ_CLR,
1226         .irq_clr_shift = 0,
1227     },
1228     {
1229         .id = MT2701_IRQ_ASYS_IRQ2,
1230         .irq_cnt_reg = ASYS_IRQ2_CON,
1231         .irq_cnt_shift = 0,
1232         .irq_cnt_maskbit = 0xffffff,
1233         .irq_fs_reg = ASYS_IRQ2_CON,
1234         .irq_fs_shift = 24,
1235         .irq_fs_maskbit = 0x1f,
1236         .irq_en_reg = ASYS_IRQ2_CON,
1237         .irq_en_shift = 31,
1238         .irq_clr_reg = ASYS_IRQ_CLR,
1239         .irq_clr_shift = 1,
1240     },
1241     {
1242         .id = MT2701_IRQ_ASYS_IRQ3,
1243         .irq_cnt_reg = ASYS_IRQ3_CON,
1244         .irq_cnt_shift = 0,
1245         .irq_cnt_maskbit = 0xffffff,
1246         .irq_fs_reg = ASYS_IRQ3_CON,
1247         .irq_fs_shift = 24,
1248         .irq_fs_maskbit = 0x1f,
1249         .irq_en_reg = ASYS_IRQ3_CON,
1250         .irq_en_shift = 31,
1251         .irq_clr_reg = ASYS_IRQ_CLR,
1252         .irq_clr_shift = 2,
1253     }
1254 };
1255 
1256 static const struct mt2701_i2s_data mt2701_i2s_data[][2] = {
1257     {
1258         { ASYS_I2SO1_CON, 0, 0x1f },
1259         { ASYS_I2SIN1_CON, 0, 0x1f },
1260     },
1261     {
1262         { ASYS_I2SO2_CON, 5, 0x1f },
1263         { ASYS_I2SIN2_CON, 5, 0x1f },
1264     },
1265     {
1266         { ASYS_I2SO3_CON, 10, 0x1f },
1267         { ASYS_I2SIN3_CON, 10, 0x1f },
1268     },
1269     {
1270         { ASYS_I2SO4_CON, 15, 0x1f },
1271         { ASYS_I2SIN4_CON, 15, 0x1f },
1272     },
1273     /* TODO - extend control registers supported by newer SoCs */
1274 };
1275 
1276 static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1277 {
1278     int id;
1279     struct mtk_base_afe *afe = dev;
1280     struct mtk_base_afe_memif *memif;
1281     struct mtk_base_afe_irq *irq;
1282     u32 status;
1283 
1284     regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
1285     regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
1286 
1287     for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
1288         memif = &afe->memif[id];
1289         if (memif->irq_usage < 0)
1290             continue;
1291 
1292         irq = &afe->irqs[memif->irq_usage];
1293         if (status & 1 << irq->irq_data->irq_clr_shift)
1294             snd_pcm_period_elapsed(memif->substream);
1295     }
1296 
1297     return IRQ_HANDLED;
1298 }
1299 
1300 static int mt2701_afe_runtime_suspend(struct device *dev)
1301 {
1302     struct mtk_base_afe *afe = dev_get_drvdata(dev);
1303 
1304     return mt2701_afe_disable_clock(afe);
1305 }
1306 
1307 static int mt2701_afe_runtime_resume(struct device *dev)
1308 {
1309     struct mtk_base_afe *afe = dev_get_drvdata(dev);
1310 
1311     return mt2701_afe_enable_clock(afe);
1312 }
1313 
1314 static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1315 {
1316     struct mtk_base_afe *afe;
1317     struct mt2701_afe_private *afe_priv;
1318     struct device *dev;
1319     int i, irq_id, ret;
1320 
1321     afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1322     if (!afe)
1323         return -ENOMEM;
1324 
1325     afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1326                       GFP_KERNEL);
1327     if (!afe->platform_priv)
1328         return -ENOMEM;
1329 
1330     afe_priv = afe->platform_priv;
1331     afe_priv->soc = of_device_get_match_data(&pdev->dev);
1332     afe->dev = &pdev->dev;
1333     dev = afe->dev;
1334 
1335     afe_priv->i2s_path = devm_kcalloc(dev,
1336                       afe_priv->soc->i2s_num,
1337                       sizeof(struct mt2701_i2s_path),
1338                       GFP_KERNEL);
1339     if (!afe_priv->i2s_path)
1340         return -ENOMEM;
1341 
1342     irq_id = platform_get_irq_byname(pdev, "asys");
1343     if (irq_id < 0)
1344         return irq_id;
1345 
1346     ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
1347                    IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1348     if (ret) {
1349         dev_err(dev, "could not request_irq for asys-isr\n");
1350         return ret;
1351     }
1352 
1353     afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1354     if (IS_ERR(afe->regmap)) {
1355         dev_err(dev, "could not get regmap from parent\n");
1356         return PTR_ERR(afe->regmap);
1357     }
1358 
1359     mutex_init(&afe->irq_alloc_lock);
1360 
1361     /* memif initialize */
1362     afe->memif_size = MT2701_MEMIF_NUM;
1363     afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1364                   GFP_KERNEL);
1365     if (!afe->memif)
1366         return -ENOMEM;
1367 
1368     for (i = 0; i < afe->memif_size; i++) {
1369         afe->memif[i].data = &memif_data_array[i];
1370         afe->memif[i].irq_usage = -1;
1371     }
1372 
1373     /* irq initialize */
1374     afe->irqs_size = MT2701_IRQ_ASYS_END;
1375     afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1376                  GFP_KERNEL);
1377     if (!afe->irqs)
1378         return -ENOMEM;
1379 
1380     for (i = 0; i < afe->irqs_size; i++)
1381         afe->irqs[i].irq_data = &irq_data[i];
1382 
1383     /* I2S initialize */
1384     for (i = 0; i < afe_priv->soc->i2s_num; i++) {
1385         afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_PLAYBACK] =
1386             &mt2701_i2s_data[i][SNDRV_PCM_STREAM_PLAYBACK];
1387         afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_CAPTURE] =
1388             &mt2701_i2s_data[i][SNDRV_PCM_STREAM_CAPTURE];
1389     }
1390 
1391     afe->mtk_afe_hardware = &mt2701_afe_hardware;
1392     afe->memif_fs = mt2701_memif_fs;
1393     afe->irq_fs = mt2701_irq_fs;
1394     afe->reg_back_up_list = mt2701_afe_backup_list;
1395     afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1396     afe->runtime_resume = mt2701_afe_runtime_resume;
1397     afe->runtime_suspend = mt2701_afe_runtime_suspend;
1398 
1399     /* initial audio related clock */
1400     ret = mt2701_init_clock(afe);
1401     if (ret) {
1402         dev_err(dev, "init clock error\n");
1403         return ret;
1404     }
1405 
1406     platform_set_drvdata(pdev, afe);
1407 
1408     pm_runtime_enable(dev);
1409     if (!pm_runtime_enabled(dev)) {
1410         ret = mt2701_afe_runtime_resume(dev);
1411         if (ret)
1412             goto err_pm_disable;
1413     }
1414     pm_runtime_get_sync(dev);
1415 
1416     ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
1417                           NULL, 0);
1418     if (ret) {
1419         dev_warn(dev, "err_platform\n");
1420         goto err_platform;
1421     }
1422 
1423     ret = devm_snd_soc_register_component(&pdev->dev,
1424                      &mt2701_afe_pcm_dai_component,
1425                      mt2701_afe_pcm_dais,
1426                      ARRAY_SIZE(mt2701_afe_pcm_dais));
1427     if (ret) {
1428         dev_warn(dev, "err_dai_component\n");
1429         goto err_platform;
1430     }
1431 
1432     return 0;
1433 
1434 err_platform:
1435     pm_runtime_put_sync(dev);
1436 err_pm_disable:
1437     pm_runtime_disable(dev);
1438 
1439     return ret;
1440 }
1441 
1442 static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
1443 {
1444     pm_runtime_put_sync(&pdev->dev);
1445     pm_runtime_disable(&pdev->dev);
1446     if (!pm_runtime_status_suspended(&pdev->dev))
1447         mt2701_afe_runtime_suspend(&pdev->dev);
1448 
1449     return 0;
1450 }
1451 
1452 static const struct mt2701_soc_variants mt2701_soc_v1 = {
1453     .i2s_num = 4,
1454 };
1455 
1456 static const struct mt2701_soc_variants mt2701_soc_v2 = {
1457     .has_one_heart_mode = true,
1458     .i2s_num = 4,
1459 };
1460 
1461 static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
1462     { .compatible = "mediatek,mt2701-audio", .data = &mt2701_soc_v1 },
1463     { .compatible = "mediatek,mt7622-audio", .data = &mt2701_soc_v2 },
1464     {},
1465 };
1466 MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
1467 
1468 static const struct dev_pm_ops mt2701_afe_pm_ops = {
1469     SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
1470                mt2701_afe_runtime_resume, NULL)
1471 };
1472 
1473 static struct platform_driver mt2701_afe_pcm_driver = {
1474     .driver = {
1475            .name = "mt2701-audio",
1476            .of_match_table = mt2701_afe_pcm_dt_match,
1477            .pm = &mt2701_afe_pm_ops,
1478     },
1479     .probe = mt2701_afe_pcm_dev_probe,
1480     .remove = mt2701_afe_pcm_dev_remove,
1481 };
1482 
1483 module_platform_driver(mt2701_afe_pcm_driver);
1484 
1485 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1486 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1487 MODULE_LICENSE("GPL v2");
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