mediatek/mt2701/mt2701-afe-common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt2701-afe-common.h  --  Mediatek 2701 audio driver definitions
0004  *
0005  * Copyright (c) 2016 MediaTek Inc.
0006  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
0007  */
0008
0009 #ifndef _MT_2701_AFE_COMMON_H_
0010 #define _MT_2701_AFE_COMMON_H_
0011
0012 #include <sound/soc.h>
0013 #include <linux/clk.h>
0014 #include <linux/regmap.h>
0015 #include "mt2701-reg.h"
0016 #include "../common/mtk-base-afe.h"
0017
0018 #define MT2701_PLL_DOMAIN_0_RATE    98304000
0019 #define MT2701_PLL_DOMAIN_1_RATE    90316800
0020
0021 enum {
0022     MT2701_MEMIF_DL1,
0023     MT2701_MEMIF_DL2,
0024     MT2701_MEMIF_DL3,
0025     MT2701_MEMIF_DL4,
0026     MT2701_MEMIF_DL5,
0027     MT2701_MEMIF_DL_SINGLE_NUM,
0028     MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
0029     MT2701_MEMIF_UL1,
0030     MT2701_MEMIF_UL2,
0031     MT2701_MEMIF_UL3,
0032     MT2701_MEMIF_UL4,
0033     MT2701_MEMIF_UL5,
0034     MT2701_MEMIF_DLBT,
0035     MT2701_MEMIF_ULBT,
0036     MT2701_MEMIF_NUM,
0037     MT2701_IO_I2S = MT2701_MEMIF_NUM,
0038     MT2701_IO_2ND_I2S,
0039     MT2701_IO_3RD_I2S,
0040     MT2701_IO_4TH_I2S,
0041     MT2701_IO_5TH_I2S,
0042     MT2701_IO_6TH_I2S,
0043     MT2701_IO_MRG,
0044 };
0045
0046 enum {
0047     MT2701_IRQ_ASYS_IRQ1,
0048     MT2701_IRQ_ASYS_IRQ2,
0049     MT2701_IRQ_ASYS_IRQ3,
0050     MT2701_IRQ_ASYS_END,
0051 };
0052
0053 enum audio_base_clock {
0054     MT2701_INFRA_SYS_AUDIO,
0055     MT2701_TOP_AUD_MCLK_SRC0,
0056     MT2701_TOP_AUD_MCLK_SRC1,
0057     MT2701_TOP_AUD_A1SYS,
0058     MT2701_TOP_AUD_A2SYS,
0059     MT2701_AUDSYS_AFE,
0060     MT2701_AUDSYS_AFE_CONN,
0061     MT2701_AUDSYS_A1SYS,
0062     MT2701_AUDSYS_A2SYS,
0063     MT2701_BASE_CLK_NUM,
0064 };
0065
0066 struct mt2701_i2s_data {
0067     int i2s_ctrl_reg;
0068     int i2s_asrc_fs_shift;
0069     int i2s_asrc_fs_mask;
0070 };
0071
0072 struct mt2701_i2s_path {
0073     int mclk_rate;
0074     int on[MTK_STREAM_NUM];
0075     int occupied[MTK_STREAM_NUM];
0076     const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM];
0077     struct clk *hop_ck[MTK_STREAM_NUM];
0078     struct clk *sel_ck;
0079     struct clk *div_ck;
0080     struct clk *mclk_ck;
0081     struct clk *asrco_ck;
0082 };
0083
0084 struct mt2701_soc_variants {
0085     bool has_one_heart_mode;
0086     int i2s_num;
0087 };
0088
0089 struct mt2701_afe_private {
0090     struct mt2701_i2s_path *i2s_path;
0091     struct clk *base_ck[MT2701_BASE_CLK_NUM];
0092     struct clk *mrgif_ck;
0093     bool mrg_enable[MTK_STREAM_NUM];
0094
0095     const struct mt2701_soc_variants *soc;
0096 };
0097
0098 #endif