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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mt2701-afe-clock-ctrl.c  --  Mediatek 2701 afe clock ctrl
0004  *
0005  * Copyright (c) 2016 MediaTek Inc.
0006  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
0007  *     Ryder Lee <ryder.lee@mediatek.com>
0008  */
0009 
0010 #include "mt2701-afe-common.h"
0011 #include "mt2701-afe-clock-ctrl.h"
0012 
0013 static const char *const base_clks[] = {
0014     [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
0015     [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
0016     [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
0017     [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
0018     [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
0019     [MT2701_AUDSYS_AFE] = "audio_afe_pd",
0020     [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
0021     [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
0022     [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
0023 };
0024 
0025 int mt2701_init_clock(struct mtk_base_afe *afe)
0026 {
0027     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0028     int i;
0029 
0030     for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
0031         afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
0032         if (IS_ERR(afe_priv->base_ck[i])) {
0033             dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
0034             return PTR_ERR(afe_priv->base_ck[i]);
0035         }
0036     }
0037 
0038     /* Get I2S related clocks */
0039     for (i = 0; i < afe_priv->soc->i2s_num; i++) {
0040         struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
0041         struct clk *i2s_ck;
0042         char name[13];
0043 
0044         snprintf(name, sizeof(name), "i2s%d_src_sel", i);
0045         i2s_path->sel_ck = devm_clk_get(afe->dev, name);
0046         if (IS_ERR(i2s_path->sel_ck)) {
0047             dev_err(afe->dev, "failed to get %s\n", name);
0048             return PTR_ERR(i2s_path->sel_ck);
0049         }
0050 
0051         snprintf(name, sizeof(name), "i2s%d_src_div", i);
0052         i2s_path->div_ck = devm_clk_get(afe->dev, name);
0053         if (IS_ERR(i2s_path->div_ck)) {
0054             dev_err(afe->dev, "failed to get %s\n", name);
0055             return PTR_ERR(i2s_path->div_ck);
0056         }
0057 
0058         snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
0059         i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
0060         if (IS_ERR(i2s_path->mclk_ck)) {
0061             dev_err(afe->dev, "failed to get %s\n", name);
0062             return PTR_ERR(i2s_path->mclk_ck);
0063         }
0064 
0065         snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
0066         i2s_ck = devm_clk_get(afe->dev, name);
0067         if (IS_ERR(i2s_ck)) {
0068             dev_err(afe->dev, "failed to get %s\n", name);
0069             return PTR_ERR(i2s_ck);
0070         }
0071         i2s_path->hop_ck[SNDRV_PCM_STREAM_PLAYBACK] = i2s_ck;
0072 
0073         snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
0074         i2s_ck = devm_clk_get(afe->dev, name);
0075         if (IS_ERR(i2s_ck)) {
0076             dev_err(afe->dev, "failed to get %s\n", name);
0077             return PTR_ERR(i2s_ck);
0078         }
0079         i2s_path->hop_ck[SNDRV_PCM_STREAM_CAPTURE] = i2s_ck;
0080 
0081         snprintf(name, sizeof(name), "asrc%d_out_ck", i);
0082         i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
0083         if (IS_ERR(i2s_path->asrco_ck)) {
0084             dev_err(afe->dev, "failed to get %s\n", name);
0085             return PTR_ERR(i2s_path->asrco_ck);
0086         }
0087     }
0088 
0089     /* Some platforms may support BT path */
0090     afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
0091     if (IS_ERR(afe_priv->mrgif_ck)) {
0092         if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
0093             return -EPROBE_DEFER;
0094 
0095         afe_priv->mrgif_ck = NULL;
0096     }
0097 
0098     return 0;
0099 }
0100 
0101 int mt2701_afe_enable_i2s(struct mtk_base_afe *afe,
0102               struct mt2701_i2s_path *i2s_path,
0103               int dir)
0104 {
0105     int ret;
0106 
0107     ret = clk_prepare_enable(i2s_path->asrco_ck);
0108     if (ret) {
0109         dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
0110         return ret;
0111     }
0112 
0113     ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
0114     if (ret) {
0115         dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
0116         goto err_hop_ck;
0117     }
0118 
0119     return 0;
0120 
0121 err_hop_ck:
0122     clk_disable_unprepare(i2s_path->asrco_ck);
0123 
0124     return ret;
0125 }
0126 
0127 void mt2701_afe_disable_i2s(struct mtk_base_afe *afe,
0128                 struct mt2701_i2s_path *i2s_path,
0129                 int dir)
0130 {
0131     clk_disable_unprepare(i2s_path->hop_ck[dir]);
0132     clk_disable_unprepare(i2s_path->asrco_ck);
0133 }
0134 
0135 int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
0136 {
0137     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0138     struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
0139 
0140     return clk_prepare_enable(i2s_path->mclk_ck);
0141 }
0142 
0143 void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
0144 {
0145     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0146     struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
0147 
0148     clk_disable_unprepare(i2s_path->mclk_ck);
0149 }
0150 
0151 int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
0152 {
0153     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0154 
0155     return clk_prepare_enable(afe_priv->mrgif_ck);
0156 }
0157 
0158 void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
0159 {
0160     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0161 
0162     clk_disable_unprepare(afe_priv->mrgif_ck);
0163 }
0164 
0165 static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
0166 {
0167     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0168     int ret;
0169 
0170     /* Enable infra clock gate */
0171     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
0172     if (ret)
0173         return ret;
0174 
0175     /* Enable top a1sys clock gate */
0176     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
0177     if (ret)
0178         goto err_a1sys;
0179 
0180     /* Enable top a2sys clock gate */
0181     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
0182     if (ret)
0183         goto err_a2sys;
0184 
0185     /* Internal clock gates */
0186     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
0187     if (ret)
0188         goto err_afe;
0189 
0190     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
0191     if (ret)
0192         goto err_audio_a1sys;
0193 
0194     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
0195     if (ret)
0196         goto err_audio_a2sys;
0197 
0198     ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
0199     if (ret)
0200         goto err_afe_conn;
0201 
0202     return 0;
0203 
0204 err_afe_conn:
0205     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
0206 err_audio_a2sys:
0207     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
0208 err_audio_a1sys:
0209     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
0210 err_afe:
0211     clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
0212 err_a2sys:
0213     clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
0214 err_a1sys:
0215     clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
0216 
0217     return ret;
0218 }
0219 
0220 static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
0221 {
0222     struct mt2701_afe_private *afe_priv = afe->platform_priv;
0223 
0224     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
0225     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
0226     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
0227     clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
0228     clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
0229     clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
0230     clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
0231 }
0232 
0233 int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
0234 {
0235     int ret;
0236 
0237     /* Enable audio system */
0238     ret = mt2701_afe_enable_audsys(afe);
0239     if (ret) {
0240         dev_err(afe->dev, "failed to enable audio system %d\n", ret);
0241         return ret;
0242     }
0243 
0244     regmap_update_bits(afe->regmap, ASYS_TOP_CON,
0245                ASYS_TOP_CON_ASYS_TIMING_ON,
0246                ASYS_TOP_CON_ASYS_TIMING_ON);
0247     regmap_update_bits(afe->regmap, AFE_DAC_CON0,
0248                AFE_DAC_CON0_AFE_ON,
0249                AFE_DAC_CON0_AFE_ON);
0250 
0251     /* Configure ASRC */
0252     regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
0253     regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
0254 
0255     return 0;
0256 }
0257 
0258 int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
0259 {
0260     regmap_update_bits(afe->regmap, ASYS_TOP_CON,
0261                ASYS_TOP_CON_ASYS_TIMING_ON, 0);
0262     regmap_update_bits(afe->regmap, AFE_DAC_CON0,
0263                AFE_DAC_CON0_AFE_ON, 0);
0264 
0265     mt2701_afe_disable_audsys(afe);
0266 
0267     return 0;
0268 }
0269 
0270 int mt2701_mclk_configuration(struct mtk_base_afe *afe, int id)
0271 
0272 {
0273     struct mt2701_afe_private *priv = afe->platform_priv;
0274     struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
0275     int ret = -EINVAL;
0276 
0277     /* Set mclk source */
0278     if (!(MT2701_PLL_DOMAIN_0_RATE % i2s_path->mclk_rate))
0279         ret = clk_set_parent(i2s_path->sel_ck,
0280                      priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
0281     else if (!(MT2701_PLL_DOMAIN_1_RATE % i2s_path->mclk_rate))
0282         ret = clk_set_parent(i2s_path->sel_ck,
0283                      priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
0284 
0285     if (ret) {
0286         dev_err(afe->dev, "failed to set mclk source\n");
0287         return ret;
0288     }
0289 
0290     /* Set mclk divider */
0291     ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate);
0292     if (ret) {
0293         dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
0294         return ret;
0295     }
0296 
0297     return 0;
0298 }
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