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0006 #include <linux/init.h>
0007 #include <linux/io.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/mod_devicetable.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/slab.h>
0013
0014 #include <linux/clk.h>
0015 #include <linux/delay.h>
0016
0017 #include <linux/dma-mapping.h>
0018
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/initval.h>
0024 #include <sound/dmaengine_pcm.h>
0025
0026 #include "jz4740-i2s.h"
0027
0028 #define JZ_REG_AIC_CONF 0x00
0029 #define JZ_REG_AIC_CTRL 0x04
0030 #define JZ_REG_AIC_I2S_FMT 0x10
0031 #define JZ_REG_AIC_FIFO_STATUS 0x14
0032 #define JZ_REG_AIC_I2S_STATUS 0x1c
0033 #define JZ_REG_AIC_CLK_DIV 0x30
0034 #define JZ_REG_AIC_FIFO 0x34
0035
0036 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
0037 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
0038 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
0039 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
0040 #define JZ_AIC_CONF_I2S BIT(4)
0041 #define JZ_AIC_CONF_RESET BIT(3)
0042 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
0043 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
0044 #define JZ_AIC_CONF_ENABLE BIT(0)
0045
0046 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
0047 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
0048 #define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
0049 #define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
0050
0051 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
0052 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
0053 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
0054 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
0055 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
0056 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
0057 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
0058 #define JZ_AIC_CTRL_FLUSH BIT(8)
0059 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
0060 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
0061 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
0062 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
0063 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
0064 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
0065 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
0066
0067 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
0068 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
0069
0070 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
0071 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
0072 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
0073 #define JZ_AIC_I2S_FMT_MSB BIT(0)
0074
0075 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
0076
0077 #define JZ_AIC_CLK_DIV_MASK 0xf
0078 #define I2SDIV_DV_SHIFT 0
0079 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
0080 #define I2SDIV_IDV_SHIFT 8
0081 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
0082
0083 enum jz47xx_i2s_version {
0084 JZ_I2S_JZ4740,
0085 JZ_I2S_JZ4760,
0086 JZ_I2S_JZ4770,
0087 JZ_I2S_JZ4780,
0088 };
0089
0090 struct i2s_soc_info {
0091 enum jz47xx_i2s_version version;
0092 struct snd_soc_dai_driver *dai;
0093 };
0094
0095 struct jz4740_i2s {
0096 void __iomem *base;
0097
0098 struct clk *clk_aic;
0099 struct clk *clk_i2s;
0100
0101 struct snd_dmaengine_dai_dma_data playback_dma_data;
0102 struct snd_dmaengine_dai_dma_data capture_dma_data;
0103
0104 const struct i2s_soc_info *soc_info;
0105 };
0106
0107 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
0108 unsigned int reg)
0109 {
0110 return readl(i2s->base + reg);
0111 }
0112
0113 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
0114 unsigned int reg, uint32_t value)
0115 {
0116 writel(value, i2s->base + reg);
0117 }
0118
0119 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
0120 struct snd_soc_dai *dai)
0121 {
0122 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0123 uint32_t conf, ctrl;
0124 int ret;
0125
0126 if (snd_soc_dai_active(dai))
0127 return 0;
0128
0129 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
0130 ctrl |= JZ_AIC_CTRL_FLUSH;
0131 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
0132
0133 ret = clk_prepare_enable(i2s->clk_i2s);
0134 if (ret)
0135 return ret;
0136
0137 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
0138 conf |= JZ_AIC_CONF_ENABLE;
0139 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
0140
0141 return 0;
0142 }
0143
0144 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
0145 struct snd_soc_dai *dai)
0146 {
0147 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0148 uint32_t conf;
0149
0150 if (snd_soc_dai_active(dai))
0151 return;
0152
0153 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
0154 conf &= ~JZ_AIC_CONF_ENABLE;
0155 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
0156
0157 clk_disable_unprepare(i2s->clk_i2s);
0158 }
0159
0160 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
0161 struct snd_soc_dai *dai)
0162 {
0163 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0164
0165 uint32_t ctrl;
0166 uint32_t mask;
0167
0168 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0169 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
0170 else
0171 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
0172
0173 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
0174
0175 switch (cmd) {
0176 case SNDRV_PCM_TRIGGER_START:
0177 case SNDRV_PCM_TRIGGER_RESUME:
0178 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0179 ctrl |= mask;
0180 break;
0181 case SNDRV_PCM_TRIGGER_STOP:
0182 case SNDRV_PCM_TRIGGER_SUSPEND:
0183 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0184 ctrl &= ~mask;
0185 break;
0186 default:
0187 return -EINVAL;
0188 }
0189
0190 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
0191
0192 return 0;
0193 }
0194
0195 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0196 {
0197 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0198
0199 uint32_t format = 0;
0200 uint32_t conf;
0201
0202 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
0203
0204 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
0205
0206 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0207 case SND_SOC_DAIFMT_BP_FP:
0208 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
0209 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
0210 break;
0211 case SND_SOC_DAIFMT_BC_FP:
0212 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
0213 break;
0214 case SND_SOC_DAIFMT_BP_FC:
0215 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
0216 break;
0217 case SND_SOC_DAIFMT_BC_FC:
0218 break;
0219 default:
0220 return -EINVAL;
0221 }
0222
0223 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0224 case SND_SOC_DAIFMT_MSB:
0225 format |= JZ_AIC_I2S_FMT_MSB;
0226 break;
0227 case SND_SOC_DAIFMT_I2S:
0228 break;
0229 default:
0230 return -EINVAL;
0231 }
0232
0233 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0234 case SND_SOC_DAIFMT_NB_NF:
0235 break;
0236 default:
0237 return -EINVAL;
0238 }
0239
0240 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
0241 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
0242
0243 return 0;
0244 }
0245
0246 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
0247 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0248 {
0249 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0250 unsigned int sample_size;
0251 uint32_t ctrl, div_reg;
0252 int div;
0253
0254 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
0255
0256 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
0257 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
0258
0259 switch (params_format(params)) {
0260 case SNDRV_PCM_FORMAT_S8:
0261 sample_size = 0;
0262 break;
0263 case SNDRV_PCM_FORMAT_S16:
0264 sample_size = 1;
0265 break;
0266 default:
0267 return -EINVAL;
0268 }
0269
0270 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0271 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
0272 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
0273 if (params_channels(params) == 1)
0274 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
0275 else
0276 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
0277
0278 div_reg &= ~I2SDIV_DV_MASK;
0279 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
0280 } else {
0281 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
0282 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
0283
0284 if (i2s->soc_info->version >= JZ_I2S_JZ4770) {
0285 div_reg &= ~I2SDIV_IDV_MASK;
0286 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
0287 } else {
0288 div_reg &= ~I2SDIV_DV_MASK;
0289 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
0290 }
0291 }
0292
0293 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
0294 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
0295
0296 return 0;
0297 }
0298
0299 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0300 unsigned int freq, int dir)
0301 {
0302 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0303 struct clk *parent;
0304 int ret = 0;
0305
0306 switch (clk_id) {
0307 case JZ4740_I2S_CLKSRC_EXT:
0308 parent = clk_get(NULL, "ext");
0309 if (IS_ERR(parent))
0310 return PTR_ERR(parent);
0311 clk_set_parent(i2s->clk_i2s, parent);
0312 break;
0313 case JZ4740_I2S_CLKSRC_PLL:
0314 parent = clk_get(NULL, "pll half");
0315 if (IS_ERR(parent))
0316 return PTR_ERR(parent);
0317 clk_set_parent(i2s->clk_i2s, parent);
0318 ret = clk_set_rate(i2s->clk_i2s, freq);
0319 break;
0320 default:
0321 return -EINVAL;
0322 }
0323 clk_put(parent);
0324
0325 return ret;
0326 }
0327
0328 static int jz4740_i2s_suspend(struct snd_soc_component *component)
0329 {
0330 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
0331 uint32_t conf;
0332
0333 if (snd_soc_component_active(component)) {
0334 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
0335 conf &= ~JZ_AIC_CONF_ENABLE;
0336 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
0337
0338 clk_disable_unprepare(i2s->clk_i2s);
0339 }
0340
0341 clk_disable_unprepare(i2s->clk_aic);
0342
0343 return 0;
0344 }
0345
0346 static int jz4740_i2s_resume(struct snd_soc_component *component)
0347 {
0348 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
0349 uint32_t conf;
0350 int ret;
0351
0352 ret = clk_prepare_enable(i2s->clk_aic);
0353 if (ret)
0354 return ret;
0355
0356 if (snd_soc_component_active(component)) {
0357 ret = clk_prepare_enable(i2s->clk_i2s);
0358 if (ret) {
0359 clk_disable_unprepare(i2s->clk_aic);
0360 return ret;
0361 }
0362
0363 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
0364 conf |= JZ_AIC_CONF_ENABLE;
0365 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
0366 }
0367
0368 return 0;
0369 }
0370
0371 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
0372 {
0373 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0374 uint32_t conf;
0375 int ret;
0376
0377 ret = clk_prepare_enable(i2s->clk_aic);
0378 if (ret)
0379 return ret;
0380
0381 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
0382 &i2s->capture_dma_data);
0383
0384 if (i2s->soc_info->version >= JZ_I2S_JZ4760) {
0385 conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
0386 (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
0387 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
0388 JZ_AIC_CONF_I2S |
0389 JZ_AIC_CONF_INTERNAL_CODEC;
0390 } else {
0391 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
0392 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
0393 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
0394 JZ_AIC_CONF_I2S |
0395 JZ_AIC_CONF_INTERNAL_CODEC;
0396 }
0397
0398 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
0399 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
0400
0401 return 0;
0402 }
0403
0404 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
0405 {
0406 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0407
0408 clk_disable_unprepare(i2s->clk_aic);
0409 return 0;
0410 }
0411
0412 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
0413 .startup = jz4740_i2s_startup,
0414 .shutdown = jz4740_i2s_shutdown,
0415 .trigger = jz4740_i2s_trigger,
0416 .hw_params = jz4740_i2s_hw_params,
0417 .set_fmt = jz4740_i2s_set_fmt,
0418 .set_sysclk = jz4740_i2s_set_sysclk,
0419 };
0420
0421 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
0422 SNDRV_PCM_FMTBIT_S16_LE)
0423
0424 static struct snd_soc_dai_driver jz4740_i2s_dai = {
0425 .probe = jz4740_i2s_dai_probe,
0426 .remove = jz4740_i2s_dai_remove,
0427 .playback = {
0428 .channels_min = 1,
0429 .channels_max = 2,
0430 .rates = SNDRV_PCM_RATE_8000_48000,
0431 .formats = JZ4740_I2S_FMTS,
0432 },
0433 .capture = {
0434 .channels_min = 2,
0435 .channels_max = 2,
0436 .rates = SNDRV_PCM_RATE_8000_48000,
0437 .formats = JZ4740_I2S_FMTS,
0438 },
0439 .symmetric_rate = 1,
0440 .ops = &jz4740_i2s_dai_ops,
0441 };
0442
0443 static const struct i2s_soc_info jz4740_i2s_soc_info = {
0444 .version = JZ_I2S_JZ4740,
0445 .dai = &jz4740_i2s_dai,
0446 };
0447
0448 static const struct i2s_soc_info jz4760_i2s_soc_info = {
0449 .version = JZ_I2S_JZ4760,
0450 .dai = &jz4740_i2s_dai,
0451 };
0452
0453 static struct snd_soc_dai_driver jz4770_i2s_dai = {
0454 .probe = jz4740_i2s_dai_probe,
0455 .remove = jz4740_i2s_dai_remove,
0456 .playback = {
0457 .channels_min = 1,
0458 .channels_max = 2,
0459 .rates = SNDRV_PCM_RATE_8000_48000,
0460 .formats = JZ4740_I2S_FMTS,
0461 },
0462 .capture = {
0463 .channels_min = 2,
0464 .channels_max = 2,
0465 .rates = SNDRV_PCM_RATE_8000_48000,
0466 .formats = JZ4740_I2S_FMTS,
0467 },
0468 .ops = &jz4740_i2s_dai_ops,
0469 };
0470
0471 static const struct i2s_soc_info jz4770_i2s_soc_info = {
0472 .version = JZ_I2S_JZ4770,
0473 .dai = &jz4770_i2s_dai,
0474 };
0475
0476 static const struct i2s_soc_info jz4780_i2s_soc_info = {
0477 .version = JZ_I2S_JZ4780,
0478 .dai = &jz4770_i2s_dai,
0479 };
0480
0481 static const struct snd_soc_component_driver jz4740_i2s_component = {
0482 .name = "jz4740-i2s",
0483 .suspend = jz4740_i2s_suspend,
0484 .resume = jz4740_i2s_resume,
0485 .legacy_dai_naming = 1,
0486 };
0487
0488 static const struct of_device_id jz4740_of_matches[] = {
0489 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
0490 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
0491 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
0492 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
0493 { }
0494 };
0495 MODULE_DEVICE_TABLE(of, jz4740_of_matches);
0496
0497 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
0498 {
0499 struct device *dev = &pdev->dev;
0500 struct jz4740_i2s *i2s;
0501 struct resource *mem;
0502 int ret;
0503
0504 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
0505 if (!i2s)
0506 return -ENOMEM;
0507
0508 i2s->soc_info = device_get_match_data(dev);
0509
0510 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
0511 if (IS_ERR(i2s->base))
0512 return PTR_ERR(i2s->base);
0513
0514 i2s->playback_dma_data.maxburst = 16;
0515 i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
0516
0517 i2s->capture_dma_data.maxburst = 16;
0518 i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
0519
0520 i2s->clk_aic = devm_clk_get(dev, "aic");
0521 if (IS_ERR(i2s->clk_aic))
0522 return PTR_ERR(i2s->clk_aic);
0523
0524 i2s->clk_i2s = devm_clk_get(dev, "i2s");
0525 if (IS_ERR(i2s->clk_i2s))
0526 return PTR_ERR(i2s->clk_i2s);
0527
0528 platform_set_drvdata(pdev, i2s);
0529
0530 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
0531 i2s->soc_info->dai, 1);
0532 if (ret)
0533 return ret;
0534
0535 return devm_snd_dmaengine_pcm_register(dev, NULL,
0536 SND_DMAENGINE_PCM_FLAG_COMPAT);
0537 }
0538
0539 static struct platform_driver jz4740_i2s_driver = {
0540 .probe = jz4740_i2s_dev_probe,
0541 .driver = {
0542 .name = "jz4740-i2s",
0543 .of_match_table = jz4740_of_matches,
0544 },
0545 };
0546
0547 module_platform_driver(jz4740_i2s_driver);
0548
0549 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
0550 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
0551 MODULE_LICENSE("GPL");
0552 MODULE_ALIAS("platform:jz4740-i2s");
