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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  skl.c - Implementation of ASoC Intel SKL HD Audio driver
0004  *
0005  *  Copyright (C) 2014-2015 Intel Corp
0006  *  Author: Jeeja KP <jeeja.kp@intel.com>
0007  *
0008  *  Derived mostly from Intel HDA driver with following copyrights:
0009  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
0010  *                     PeiSen Hou <pshou@realtek.com.tw>
0011  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0012  *
0013  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0014  */
0015 
0016 #include <linux/module.h>
0017 #include <linux/pci.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/firmware.h>
0021 #include <linux/delay.h>
0022 #include <sound/pcm.h>
0023 #include <sound/soc-acpi.h>
0024 #include <sound/soc-acpi-intel-match.h>
0025 #include <sound/hda_register.h>
0026 #include <sound/hdaudio.h>
0027 #include <sound/hda_i915.h>
0028 #include <sound/hda_codec.h>
0029 #include <sound/intel-nhlt.h>
0030 #include <sound/intel-dsp-config.h>
0031 #include "skl.h"
0032 #include "skl-sst-dsp.h"
0033 #include "skl-sst-ipc.h"
0034 
0035 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
0036 #include "../../../soc/codecs/hdac_hda.h"
0037 #endif
0038 static int skl_pci_binding;
0039 module_param_named(pci_binding, skl_pci_binding, int, 0444);
0040 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
0041 
0042 /*
0043  * initialize the PCI registers
0044  */
0045 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
0046                 unsigned char mask, unsigned char val)
0047 {
0048     unsigned char data;
0049 
0050     pci_read_config_byte(pci, reg, &data);
0051     data &= ~mask;
0052     data |= (val & mask);
0053     pci_write_config_byte(pci, reg, data);
0054 }
0055 
0056 static void skl_init_pci(struct skl_dev *skl)
0057 {
0058     struct hdac_bus *bus = skl_to_bus(skl);
0059 
0060     /*
0061      * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
0062      * TCSEL == Traffic Class Select Register, which sets PCI express QOS
0063      * Ensuring these bits are 0 clears playback static on some HD Audio
0064      * codecs.
0065      * The PCI register TCSEL is defined in the Intel manuals.
0066      */
0067     dev_dbg(bus->dev, "Clearing TCSEL\n");
0068     skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
0069 }
0070 
0071 static void update_pci_dword(struct pci_dev *pci,
0072             unsigned int reg, u32 mask, u32 val)
0073 {
0074     u32 data = 0;
0075 
0076     pci_read_config_dword(pci, reg, &data);
0077     data &= ~mask;
0078     data |= (val & mask);
0079     pci_write_config_dword(pci, reg, data);
0080 }
0081 
0082 /*
0083  * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
0084  *
0085  * @dev: device pointer
0086  * @enable: enable/disable flag
0087  */
0088 static void skl_enable_miscbdcge(struct device *dev, bool enable)
0089 {
0090     struct pci_dev *pci = to_pci_dev(dev);
0091     u32 val;
0092 
0093     val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
0094 
0095     update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
0096 }
0097 
0098 /**
0099  * skl_clock_power_gating: Enable/Disable clock and power gating
0100  *
0101  * @dev: Device pointer
0102  * @enable: Enable/Disable flag
0103  */
0104 static void skl_clock_power_gating(struct device *dev, bool enable)
0105 {
0106     struct pci_dev *pci = to_pci_dev(dev);
0107     struct hdac_bus *bus = pci_get_drvdata(pci);
0108     u32 val;
0109 
0110     /* Update PDCGE bit of CGCTL register */
0111     val = enable ? AZX_CGCTL_ADSPDCGE : 0;
0112     update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
0113 
0114     /* Update L1SEN bit of EM2 register */
0115     val = enable ? AZX_REG_VS_EM2_L1SEN : 0;
0116     snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val);
0117 
0118     /* Update ADSPPGD bit of PGCTL register */
0119     val = enable ? 0 : AZX_PGCTL_ADSPPGD;
0120     update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val);
0121 }
0122 
0123 /*
0124  * While performing reset, controller may not come back properly causing
0125  * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
0126  * (init chip) and then again set CGCTL.MISCBDCGE to 1
0127  */
0128 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
0129 {
0130     struct hdac_ext_link *hlink;
0131     int ret;
0132 
0133     snd_hdac_set_codec_wakeup(bus, true);
0134     skl_enable_miscbdcge(bus->dev, false);
0135     ret = snd_hdac_bus_init_chip(bus, full_reset);
0136 
0137     /* Reset stream-to-link mapping */
0138     list_for_each_entry(hlink, &bus->hlink_list, list)
0139         writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
0140 
0141     skl_enable_miscbdcge(bus->dev, true);
0142     snd_hdac_set_codec_wakeup(bus, false);
0143 
0144     return ret;
0145 }
0146 
0147 void skl_update_d0i3c(struct device *dev, bool enable)
0148 {
0149     struct pci_dev *pci = to_pci_dev(dev);
0150     struct hdac_bus *bus = pci_get_drvdata(pci);
0151     u8 reg;
0152     int timeout = 50;
0153 
0154     reg = snd_hdac_chip_readb(bus, VS_D0I3C);
0155     /* Do not write to D0I3C until command in progress bit is cleared */
0156     while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
0157         udelay(10);
0158         reg = snd_hdac_chip_readb(bus, VS_D0I3C);
0159     }
0160 
0161     /* Highly unlikely. But if it happens, flag error explicitly */
0162     if (!timeout) {
0163         dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
0164         return;
0165     }
0166 
0167     if (enable)
0168         reg = reg | AZX_REG_VS_D0I3C_I3;
0169     else
0170         reg = reg & (~AZX_REG_VS_D0I3C_I3);
0171 
0172     snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
0173 
0174     timeout = 50;
0175     /* Wait for cmd in progress to be cleared before exiting the function */
0176     reg = snd_hdac_chip_readb(bus, VS_D0I3C);
0177     while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
0178         udelay(10);
0179         reg = snd_hdac_chip_readb(bus, VS_D0I3C);
0180     }
0181 
0182     /* Highly unlikely. But if it happens, flag error explicitly */
0183     if (!timeout) {
0184         dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
0185         return;
0186     }
0187 
0188     dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
0189             snd_hdac_chip_readb(bus, VS_D0I3C));
0190 }
0191 
0192 /**
0193  * skl_dum_set - set DUM bit in EM2 register
0194  * @bus: HD-audio core bus
0195  *
0196  * Addresses incorrect position reporting for capture streams.
0197  * Used on device power up.
0198  */
0199 static void skl_dum_set(struct hdac_bus *bus)
0200 {
0201     /* For the DUM bit to be set, CRST needs to be out of reset state */
0202     if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) {
0203         skl_enable_miscbdcge(bus->dev, false);
0204         snd_hdac_bus_exit_link_reset(bus);
0205         skl_enable_miscbdcge(bus->dev, true);
0206     }
0207 
0208     snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
0209 }
0210 
0211 /* called from IRQ */
0212 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
0213 {
0214     snd_pcm_period_elapsed(hstr->substream);
0215 }
0216 
0217 static irqreturn_t skl_interrupt(int irq, void *dev_id)
0218 {
0219     struct hdac_bus *bus = dev_id;
0220     u32 status;
0221 
0222     if (!pm_runtime_active(bus->dev))
0223         return IRQ_NONE;
0224 
0225     spin_lock(&bus->reg_lock);
0226 
0227     status = snd_hdac_chip_readl(bus, INTSTS);
0228     if (status == 0 || status == 0xffffffff) {
0229         spin_unlock(&bus->reg_lock);
0230         return IRQ_NONE;
0231     }
0232 
0233     /* clear rirb int */
0234     status = snd_hdac_chip_readb(bus, RIRBSTS);
0235     if (status & RIRB_INT_MASK) {
0236         if (status & RIRB_INT_RESPONSE)
0237             snd_hdac_bus_update_rirb(bus);
0238         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
0239     }
0240 
0241     spin_unlock(&bus->reg_lock);
0242 
0243     return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
0244 }
0245 
0246 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
0247 {
0248     struct hdac_bus *bus = dev_id;
0249     u32 status;
0250 
0251     status = snd_hdac_chip_readl(bus, INTSTS);
0252 
0253     snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
0254 
0255     return IRQ_HANDLED;
0256 }
0257 
0258 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect)
0259 {
0260     struct skl_dev *skl = bus_to_skl(bus);
0261     int ret;
0262 
0263     ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
0264             skl_threaded_handler,
0265             IRQF_SHARED,
0266             KBUILD_MODNAME, bus);
0267     if (ret) {
0268         dev_err(bus->dev,
0269             "unable to grab IRQ %d, disabling device\n",
0270             skl->pci->irq);
0271         return ret;
0272     }
0273 
0274     bus->irq = skl->pci->irq;
0275     pci_intx(skl->pci, 1);
0276 
0277     return 0;
0278 }
0279 
0280 static int skl_suspend_late(struct device *dev)
0281 {
0282     struct pci_dev *pci = to_pci_dev(dev);
0283     struct hdac_bus *bus = pci_get_drvdata(pci);
0284     struct skl_dev *skl = bus_to_skl(bus);
0285 
0286     return skl_suspend_late_dsp(skl);
0287 }
0288 
0289 #ifdef CONFIG_PM
0290 static int _skl_suspend(struct hdac_bus *bus)
0291 {
0292     struct skl_dev *skl = bus_to_skl(bus);
0293     struct pci_dev *pci = to_pci_dev(bus->dev);
0294     int ret;
0295 
0296     snd_hdac_ext_bus_link_power_down_all(bus);
0297 
0298     ret = skl_suspend_dsp(skl);
0299     if (ret < 0)
0300         return ret;
0301 
0302     snd_hdac_bus_stop_chip(bus);
0303     update_pci_dword(pci, AZX_PCIREG_PGCTL,
0304         AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
0305     skl_enable_miscbdcge(bus->dev, false);
0306     snd_hdac_bus_enter_link_reset(bus);
0307     skl_enable_miscbdcge(bus->dev, true);
0308     skl_cleanup_resources(skl);
0309 
0310     return 0;
0311 }
0312 
0313 static int _skl_resume(struct hdac_bus *bus)
0314 {
0315     struct skl_dev *skl = bus_to_skl(bus);
0316 
0317     skl_init_pci(skl);
0318     skl_dum_set(bus);
0319     skl_init_chip(bus, true);
0320 
0321     return skl_resume_dsp(skl);
0322 }
0323 #endif
0324 
0325 #ifdef CONFIG_PM_SLEEP
0326 /*
0327  * power management
0328  */
0329 static int skl_suspend(struct device *dev)
0330 {
0331     struct pci_dev *pci = to_pci_dev(dev);
0332     struct hdac_bus *bus = pci_get_drvdata(pci);
0333     struct skl_dev *skl  = bus_to_skl(bus);
0334     int ret;
0335 
0336     /*
0337      * Do not suspend if streams which are marked ignore suspend are
0338      * running, we need to save the state for these and continue
0339      */
0340     if (skl->supend_active) {
0341         /* turn off the links and stop the CORB/RIRB DMA if it is On */
0342         snd_hdac_ext_bus_link_power_down_all(bus);
0343 
0344         if (bus->cmd_dma_state)
0345             snd_hdac_bus_stop_cmd_io(bus);
0346 
0347         enable_irq_wake(bus->irq);
0348         pci_save_state(pci);
0349     } else {
0350         ret = _skl_suspend(bus);
0351         if (ret < 0)
0352             return ret;
0353         skl->fw_loaded = false;
0354     }
0355 
0356     return 0;
0357 }
0358 
0359 static int skl_resume(struct device *dev)
0360 {
0361     struct pci_dev *pci = to_pci_dev(dev);
0362     struct hdac_bus *bus = pci_get_drvdata(pci);
0363     struct skl_dev *skl  = bus_to_skl(bus);
0364     struct hdac_ext_link *hlink;
0365     int ret;
0366 
0367     /*
0368      * resume only when we are not in suspend active, otherwise need to
0369      * restore the device
0370      */
0371     if (skl->supend_active) {
0372         pci_restore_state(pci);
0373         snd_hdac_ext_bus_link_power_up_all(bus);
0374         disable_irq_wake(bus->irq);
0375         /*
0376          * turn On the links which are On before active suspend
0377          * and start the CORB/RIRB DMA if On before
0378          * active suspend.
0379          */
0380         list_for_each_entry(hlink, &bus->hlink_list, list) {
0381             if (hlink->ref_count)
0382                 snd_hdac_ext_bus_link_power_up(hlink);
0383         }
0384 
0385         ret = 0;
0386         if (bus->cmd_dma_state)
0387             snd_hdac_bus_init_cmd_io(bus);
0388     } else {
0389         ret = _skl_resume(bus);
0390 
0391         /* turn off the links which are off before suspend */
0392         list_for_each_entry(hlink, &bus->hlink_list, list) {
0393             if (!hlink->ref_count)
0394                 snd_hdac_ext_bus_link_power_down(hlink);
0395         }
0396 
0397         if (!bus->cmd_dma_state)
0398             snd_hdac_bus_stop_cmd_io(bus);
0399     }
0400 
0401     return ret;
0402 }
0403 #endif /* CONFIG_PM_SLEEP */
0404 
0405 #ifdef CONFIG_PM
0406 static int skl_runtime_suspend(struct device *dev)
0407 {
0408     struct pci_dev *pci = to_pci_dev(dev);
0409     struct hdac_bus *bus = pci_get_drvdata(pci);
0410 
0411     dev_dbg(bus->dev, "in %s\n", __func__);
0412 
0413     return _skl_suspend(bus);
0414 }
0415 
0416 static int skl_runtime_resume(struct device *dev)
0417 {
0418     struct pci_dev *pci = to_pci_dev(dev);
0419     struct hdac_bus *bus = pci_get_drvdata(pci);
0420 
0421     dev_dbg(bus->dev, "in %s\n", __func__);
0422 
0423     return _skl_resume(bus);
0424 }
0425 #endif /* CONFIG_PM */
0426 
0427 static const struct dev_pm_ops skl_pm = {
0428     SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
0429     SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
0430     .suspend_late = skl_suspend_late,
0431 };
0432 
0433 /*
0434  * destructor
0435  */
0436 static int skl_free(struct hdac_bus *bus)
0437 {
0438     struct skl_dev *skl  = bus_to_skl(bus);
0439 
0440     skl->init_done = 0; /* to be sure */
0441 
0442     snd_hdac_stop_streams_and_chip(bus);
0443 
0444     if (bus->irq >= 0)
0445         free_irq(bus->irq, (void *)bus);
0446     snd_hdac_bus_free_stream_pages(bus);
0447     snd_hdac_stream_free_all(bus);
0448     snd_hdac_link_free_all(bus);
0449 
0450     if (bus->remap_addr)
0451         iounmap(bus->remap_addr);
0452 
0453     pci_release_regions(skl->pci);
0454     pci_disable_device(skl->pci);
0455 
0456     snd_hdac_ext_bus_exit(bus);
0457 
0458     if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
0459         snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
0460         snd_hdac_i915_exit(bus);
0461     }
0462 
0463     return 0;
0464 }
0465 
0466 /*
0467  * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
0468  * e.g. for ssp0, clocks will be named as
0469  *      "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
0470  * So for skl+, there are 6 ssps, so 18 clocks will be created.
0471  */
0472 static struct skl_ssp_clk skl_ssp_clks[] = {
0473     {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"},
0474     {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"},
0475     {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"},
0476     {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"},
0477     {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"},
0478                         {.name = "ssp2_sclkfs"},
0479     {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"},
0480                         {.name = "ssp5_sclkfs"},
0481 };
0482 
0483 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl,
0484                     struct snd_soc_acpi_mach *machines)
0485 {
0486     struct snd_soc_acpi_mach *mach;
0487 
0488     /* point to common table */
0489     mach = snd_soc_acpi_intel_hda_machines;
0490 
0491     /* all entries in the machine table use the same firmware */
0492     mach->fw_filename = machines->fw_filename;
0493 
0494     return mach;
0495 }
0496 
0497 static int skl_find_machine(struct skl_dev *skl, void *driver_data)
0498 {
0499     struct hdac_bus *bus = skl_to_bus(skl);
0500     struct snd_soc_acpi_mach *mach = driver_data;
0501     struct skl_machine_pdata *pdata;
0502 
0503     mach = snd_soc_acpi_find_machine(mach);
0504     if (!mach) {
0505         dev_dbg(bus->dev, "No matching I2S machine driver found\n");
0506         mach = skl_find_hda_machine(skl, driver_data);
0507         if (!mach) {
0508             dev_err(bus->dev, "No matching machine driver found\n");
0509             return -ENODEV;
0510         }
0511     }
0512 
0513     skl->mach = mach;
0514     skl->fw_name = mach->fw_filename;
0515     pdata = mach->pdata;
0516 
0517     if (pdata) {
0518         skl->use_tplg_pcm = pdata->use_tplg_pcm;
0519         mach->mach_params.dmic_num =
0520             intel_nhlt_get_dmic_geo(&skl->pci->dev,
0521                         skl->nhlt);
0522     }
0523 
0524     return 0;
0525 }
0526 
0527 static int skl_machine_device_register(struct skl_dev *skl)
0528 {
0529     struct snd_soc_acpi_mach *mach = skl->mach;
0530     struct hdac_bus *bus = skl_to_bus(skl);
0531     struct platform_device *pdev;
0532     int ret;
0533 
0534     pdev = platform_device_alloc(mach->drv_name, -1);
0535     if (pdev == NULL) {
0536         dev_err(bus->dev, "platform device alloc failed\n");
0537         return -EIO;
0538     }
0539 
0540     mach->mach_params.platform = dev_name(bus->dev);
0541     mach->mach_params.codec_mask = bus->codec_mask;
0542 
0543     ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach));
0544     if (ret) {
0545         dev_err(bus->dev, "failed to add machine device platform data\n");
0546         platform_device_put(pdev);
0547         return ret;
0548     }
0549 
0550     ret = platform_device_add(pdev);
0551     if (ret) {
0552         dev_err(bus->dev, "failed to add machine device\n");
0553         platform_device_put(pdev);
0554         return -EIO;
0555     }
0556 
0557 
0558     skl->i2s_dev = pdev;
0559 
0560     return 0;
0561 }
0562 
0563 static void skl_machine_device_unregister(struct skl_dev *skl)
0564 {
0565     if (skl->i2s_dev)
0566         platform_device_unregister(skl->i2s_dev);
0567 }
0568 
0569 static int skl_dmic_device_register(struct skl_dev *skl)
0570 {
0571     struct hdac_bus *bus = skl_to_bus(skl);
0572     struct platform_device *pdev;
0573     int ret;
0574 
0575     /* SKL has one dmic port, so allocate dmic device for this */
0576     pdev = platform_device_alloc("dmic-codec", -1);
0577     if (!pdev) {
0578         dev_err(bus->dev, "failed to allocate dmic device\n");
0579         return -ENOMEM;
0580     }
0581 
0582     ret = platform_device_add(pdev);
0583     if (ret) {
0584         dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
0585         platform_device_put(pdev);
0586         return ret;
0587     }
0588     skl->dmic_dev = pdev;
0589 
0590     return 0;
0591 }
0592 
0593 static void skl_dmic_device_unregister(struct skl_dev *skl)
0594 {
0595     if (skl->dmic_dev)
0596         platform_device_unregister(skl->dmic_dev);
0597 }
0598 
0599 static struct skl_clk_parent_src skl_clk_src[] = {
0600     { .clk_id = SKL_XTAL, .name = "xtal" },
0601     { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 },
0602     { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 },
0603 };
0604 
0605 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id)
0606 {
0607     unsigned int i;
0608 
0609     for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) {
0610         if (skl_clk_src[i].clk_id == clk_id)
0611             return &skl_clk_src[i];
0612     }
0613 
0614     return NULL;
0615 }
0616 
0617 static void init_skl_xtal_rate(int pci_id)
0618 {
0619     switch (pci_id) {
0620     case 0x9d70:
0621     case 0x9d71:
0622         skl_clk_src[0].rate = 24000000;
0623         return;
0624 
0625     default:
0626         skl_clk_src[0].rate = 19200000;
0627         return;
0628     }
0629 }
0630 
0631 static int skl_clock_device_register(struct skl_dev *skl)
0632 {
0633     struct platform_device_info pdevinfo = {NULL};
0634     struct skl_clk_pdata *clk_pdata;
0635 
0636     if (!skl->nhlt)
0637         return 0;
0638 
0639     clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata),
0640                             GFP_KERNEL);
0641     if (!clk_pdata)
0642         return -ENOMEM;
0643 
0644     init_skl_xtal_rate(skl->pci->device);
0645 
0646     clk_pdata->parent_clks = skl_clk_src;
0647     clk_pdata->ssp_clks = skl_ssp_clks;
0648     clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks);
0649 
0650     /* Query NHLT to fill the rates and parent */
0651     skl_get_clks(skl, clk_pdata->ssp_clks);
0652     clk_pdata->pvt_data = skl;
0653 
0654     /* Register Platform device */
0655     pdevinfo.parent = &skl->pci->dev;
0656     pdevinfo.id = -1;
0657     pdevinfo.name = "skl-ssp-clk";
0658     pdevinfo.data = clk_pdata;
0659     pdevinfo.size_data = sizeof(*clk_pdata);
0660     skl->clk_dev = platform_device_register_full(&pdevinfo);
0661     return PTR_ERR_OR_ZERO(skl->clk_dev);
0662 }
0663 
0664 static void skl_clock_device_unregister(struct skl_dev *skl)
0665 {
0666     if (skl->clk_dev)
0667         platform_device_unregister(skl->clk_dev);
0668 }
0669 
0670 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
0671 
0672 #define IDISP_INTEL_VENDOR_ID   0x80860000
0673 
0674 /*
0675  * load the legacy codec driver
0676  */
0677 static void load_codec_module(struct hda_codec *codec)
0678 {
0679 #ifdef MODULE
0680     char modalias[MODULE_NAME_LEN];
0681     const char *mod = NULL;
0682 
0683     snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias));
0684     mod = modalias;
0685     dev_dbg(&codec->core.dev, "loading %s codec module\n", mod);
0686     request_module(mod);
0687 #endif
0688 }
0689 
0690 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
0691 
0692 /*
0693  * Probe the given codec address
0694  */
0695 static int probe_codec(struct hdac_bus *bus, int addr)
0696 {
0697     unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
0698         (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
0699     unsigned int res = -1;
0700     struct skl_dev *skl = bus_to_skl(bus);
0701 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
0702     struct hdac_hda_priv *hda_codec;
0703     int err;
0704 #endif
0705     struct hdac_device *hdev;
0706 
0707     mutex_lock(&bus->cmd_mutex);
0708     snd_hdac_bus_send_cmd(bus, cmd);
0709     snd_hdac_bus_get_response(bus, addr, &res);
0710     mutex_unlock(&bus->cmd_mutex);
0711     if (res == -1)
0712         return -EIO;
0713     dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res);
0714 
0715 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
0716     hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec),
0717                  GFP_KERNEL);
0718     if (!hda_codec)
0719         return -ENOMEM;
0720 
0721     hda_codec->codec.bus = skl_to_hbus(skl);
0722     hdev = &hda_codec->codec.core;
0723 
0724     err = snd_hdac_ext_bus_device_init(bus, addr, hdev, HDA_DEV_ASOC);
0725     if (err < 0)
0726         return err;
0727 
0728     /* use legacy bus only for HDA codecs, idisp uses ext bus */
0729     if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) {
0730         hdev->type = HDA_DEV_LEGACY;
0731         load_codec_module(&hda_codec->codec);
0732     }
0733     return 0;
0734 #else
0735     hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL);
0736     if (!hdev)
0737         return -ENOMEM;
0738 
0739     return snd_hdac_ext_bus_device_init(bus, addr, hdev, HDA_DEV_ASOC);
0740 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
0741 }
0742 
0743 /* Codec initialization */
0744 static void skl_codec_create(struct hdac_bus *bus)
0745 {
0746     int c, max_slots;
0747 
0748     max_slots = HDA_MAX_CODECS;
0749 
0750     /* First try to probe all given codec slots */
0751     for (c = 0; c < max_slots; c++) {
0752         if ((bus->codec_mask & (1 << c))) {
0753             if (probe_codec(bus, c) < 0) {
0754                 /*
0755                  * Some BIOSen give you wrong codec addresses
0756                  * that don't exist
0757                  */
0758                 dev_warn(bus->dev,
0759                      "Codec #%d probe error; disabling it...\n", c);
0760                 bus->codec_mask &= ~(1 << c);
0761                 /*
0762                  * More badly, accessing to a non-existing
0763                  * codec often screws up the controller bus,
0764                  * and disturbs the further communications.
0765                  * Thus if an error occurs during probing,
0766                  * better to reset the controller bus to get
0767                  * back to the sanity state.
0768                  */
0769                 snd_hdac_bus_stop_chip(bus);
0770                 skl_init_chip(bus, true);
0771             }
0772         }
0773     }
0774 }
0775 
0776 static int skl_i915_init(struct hdac_bus *bus)
0777 {
0778     int err;
0779 
0780     /*
0781      * The HDMI codec is in GPU so we need to ensure that it is powered
0782      * up and ready for probe
0783      */
0784     err = snd_hdac_i915_init(bus);
0785     if (err < 0)
0786         return err;
0787 
0788     snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
0789 
0790     return 0;
0791 }
0792 
0793 static void skl_probe_work(struct work_struct *work)
0794 {
0795     struct skl_dev *skl = container_of(work, struct skl_dev, probe_work);
0796     struct hdac_bus *bus = skl_to_bus(skl);
0797     struct hdac_ext_link *hlink;
0798     int err;
0799 
0800     if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
0801         err = skl_i915_init(bus);
0802         if (err < 0)
0803             return;
0804     }
0805 
0806     skl_init_pci(skl);
0807     skl_dum_set(bus);
0808 
0809     err = skl_init_chip(bus, true);
0810     if (err < 0) {
0811         dev_err(bus->dev, "Init chip failed with err: %d\n", err);
0812         goto out_err;
0813     }
0814 
0815     /* codec detection */
0816     if (!bus->codec_mask)
0817         dev_info(bus->dev, "no hda codecs found!\n");
0818 
0819     /* create codec instances */
0820     skl_codec_create(bus);
0821 
0822     /* register platform dai and controls */
0823     err = skl_platform_register(bus->dev);
0824     if (err < 0) {
0825         dev_err(bus->dev, "platform register failed: %d\n", err);
0826         goto out_err;
0827     }
0828 
0829     err = skl_machine_device_register(skl);
0830     if (err < 0) {
0831         dev_err(bus->dev, "machine register failed: %d\n", err);
0832         goto out_err;
0833     }
0834 
0835     /*
0836      * we are done probing so decrement link counts
0837      */
0838     list_for_each_entry(hlink, &bus->hlink_list, list)
0839         snd_hdac_ext_bus_link_put(bus, hlink);
0840 
0841     if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
0842         snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
0843 
0844     /* configure PM */
0845     pm_runtime_put_noidle(bus->dev);
0846     pm_runtime_allow(bus->dev);
0847     skl->init_done = 1;
0848 
0849     return;
0850 
0851 out_err:
0852     if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
0853         snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
0854 }
0855 
0856 /*
0857  * constructor
0858  */
0859 static int skl_create(struct pci_dev *pci,
0860               struct skl_dev **rskl)
0861 {
0862     struct hdac_ext_bus_ops *ext_ops = NULL;
0863     struct skl_dev *skl;
0864     struct hdac_bus *bus;
0865     struct hda_bus *hbus;
0866     int err;
0867 
0868     *rskl = NULL;
0869 
0870     err = pci_enable_device(pci);
0871     if (err < 0)
0872         return err;
0873 
0874     skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
0875     if (!skl) {
0876         pci_disable_device(pci);
0877         return -ENOMEM;
0878     }
0879 
0880     hbus = skl_to_hbus(skl);
0881     bus = skl_to_bus(skl);
0882 
0883     INIT_LIST_HEAD(&skl->ppl_list);
0884     INIT_LIST_HEAD(&skl->bind_list);
0885 
0886 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
0887     ext_ops = snd_soc_hdac_hda_get_ops();
0888 #endif
0889     snd_hdac_ext_bus_init(bus, &pci->dev, NULL, ext_ops);
0890     bus->use_posbuf = 1;
0891     skl->pci = pci;
0892     INIT_WORK(&skl->probe_work, skl_probe_work);
0893     bus->bdl_pos_adj = 0;
0894 
0895     mutex_init(&hbus->prepare_mutex);
0896     hbus->pci = pci;
0897     hbus->mixer_assigned = -1;
0898     hbus->modelname = "sklbus";
0899 
0900     *rskl = skl;
0901 
0902     return 0;
0903 }
0904 
0905 static int skl_first_init(struct hdac_bus *bus)
0906 {
0907     struct skl_dev *skl = bus_to_skl(bus);
0908     struct pci_dev *pci = skl->pci;
0909     int err;
0910     unsigned short gcap;
0911     int cp_streams, pb_streams, start_idx;
0912 
0913     err = pci_request_regions(pci, "Skylake HD audio");
0914     if (err < 0)
0915         return err;
0916 
0917     bus->addr = pci_resource_start(pci, 0);
0918     bus->remap_addr = pci_ioremap_bar(pci, 0);
0919     if (bus->remap_addr == NULL) {
0920         dev_err(bus->dev, "ioremap error\n");
0921         return -ENXIO;
0922     }
0923 
0924     snd_hdac_bus_parse_capabilities(bus);
0925 
0926     /* check if PPCAP exists */
0927     if (!bus->ppcap) {
0928         dev_err(bus->dev, "bus ppcap not set, HDAudio or DSP not present?\n");
0929         return -ENODEV;
0930     }
0931 
0932     if (skl_acquire_irq(bus, 0) < 0)
0933         return -EBUSY;
0934 
0935     pci_set_master(pci);
0936     synchronize_irq(bus->irq);
0937 
0938     gcap = snd_hdac_chip_readw(bus, GCAP);
0939     dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
0940 
0941     /* read number of streams from GCAP register */
0942     cp_streams = (gcap >> 8) & 0x0f;
0943     pb_streams = (gcap >> 12) & 0x0f;
0944 
0945     if (!pb_streams && !cp_streams) {
0946         dev_err(bus->dev, "no streams found in GCAP definitions?\n");
0947         return -EIO;
0948     }
0949 
0950     bus->num_streams = cp_streams + pb_streams;
0951 
0952     /* allow 64bit DMA address if supported by H/W */
0953     if (dma_set_mask_and_coherent(bus->dev, DMA_BIT_MASK(64)))
0954         dma_set_mask_and_coherent(bus->dev, DMA_BIT_MASK(32));
0955     dma_set_max_seg_size(bus->dev, UINT_MAX);
0956 
0957     /* initialize streams */
0958     snd_hdac_ext_stream_init_all
0959         (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
0960     start_idx = cp_streams;
0961     snd_hdac_ext_stream_init_all
0962         (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
0963 
0964     err = snd_hdac_bus_alloc_stream_pages(bus);
0965     if (err < 0)
0966         return err;
0967 
0968     return 0;
0969 }
0970 
0971 static int skl_probe(struct pci_dev *pci,
0972              const struct pci_device_id *pci_id)
0973 {
0974     struct skl_dev *skl;
0975     struct hdac_bus *bus = NULL;
0976     int err;
0977 
0978     switch (skl_pci_binding) {
0979     case SND_SKL_PCI_BIND_AUTO:
0980         err = snd_intel_dsp_driver_probe(pci);
0981         if (err != SND_INTEL_DSP_DRIVER_ANY &&
0982             err != SND_INTEL_DSP_DRIVER_SST)
0983             return -ENODEV;
0984         break;
0985     case SND_SKL_PCI_BIND_LEGACY:
0986         dev_info(&pci->dev, "Module parameter forced binding with HDAudio legacy, aborting probe\n");
0987         return -ENODEV;
0988     case SND_SKL_PCI_BIND_ASOC:
0989         dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n");
0990         break;
0991     default:
0992         dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n");
0993         break;
0994     }
0995 
0996     /* we use ext core ops, so provide NULL for ops here */
0997     err = skl_create(pci, &skl);
0998     if (err < 0)
0999         return err;
1000 
1001     bus = skl_to_bus(skl);
1002 
1003     err = skl_first_init(bus);
1004     if (err < 0) {
1005         dev_err(bus->dev, "skl_first_init failed with err: %d\n", err);
1006         goto out_free;
1007     }
1008 
1009     skl->pci_id = pci->device;
1010 
1011     device_disable_async_suspend(bus->dev);
1012 
1013     skl->nhlt = intel_nhlt_init(bus->dev);
1014 
1015     if (skl->nhlt == NULL) {
1016 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
1017         dev_err(bus->dev, "no nhlt info found\n");
1018         err = -ENODEV;
1019         goto out_free;
1020 #else
1021         dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDAudio codec\n");
1022 #endif
1023     } else {
1024 
1025         err = skl_nhlt_create_sysfs(skl);
1026         if (err < 0) {
1027             dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err);
1028             goto out_nhlt_free;
1029         }
1030 
1031         skl_nhlt_update_topology_bin(skl);
1032 
1033         /* create device for dsp clk */
1034         err = skl_clock_device_register(skl);
1035         if (err < 0) {
1036             dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err);
1037             goto out_clk_free;
1038         }
1039     }
1040 
1041     pci_set_drvdata(skl->pci, bus);
1042 
1043 
1044     err = skl_find_machine(skl, (void *)pci_id->driver_data);
1045     if (err < 0) {
1046         dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err);
1047         goto out_nhlt_free;
1048     }
1049 
1050     err = skl_init_dsp(skl);
1051     if (err < 0) {
1052         dev_dbg(bus->dev, "error failed to register dsp\n");
1053         goto out_nhlt_free;
1054     }
1055     skl->enable_miscbdcge = skl_enable_miscbdcge;
1056     skl->clock_power_gating = skl_clock_power_gating;
1057 
1058     if (bus->mlcap)
1059         snd_hdac_ext_bus_get_ml_capabilities(bus);
1060 
1061     /* create device for soc dmic */
1062     err = skl_dmic_device_register(skl);
1063     if (err < 0) {
1064         dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err);
1065         goto out_dsp_free;
1066     }
1067 
1068     schedule_work(&skl->probe_work);
1069 
1070     return 0;
1071 
1072 out_dsp_free:
1073     skl_free_dsp(skl);
1074 out_clk_free:
1075     skl_clock_device_unregister(skl);
1076 out_nhlt_free:
1077     if (skl->nhlt)
1078         intel_nhlt_free(skl->nhlt);
1079 out_free:
1080     skl_free(bus);
1081 
1082     return err;
1083 }
1084 
1085 static void skl_shutdown(struct pci_dev *pci)
1086 {
1087     struct hdac_bus *bus = pci_get_drvdata(pci);
1088     struct hdac_stream *s;
1089     struct hdac_ext_stream *stream;
1090     struct skl_dev *skl;
1091 
1092     if (!bus)
1093         return;
1094 
1095     skl = bus_to_skl(bus);
1096 
1097     if (!skl->init_done)
1098         return;
1099 
1100     snd_hdac_stop_streams_and_chip(bus);
1101     list_for_each_entry(s, &bus->stream_list, list) {
1102         stream = stream_to_hdac_ext_stream(s);
1103         snd_hdac_ext_stream_decouple(bus, stream, false);
1104     }
1105 
1106     snd_hdac_bus_stop_chip(bus);
1107 }
1108 
1109 static void skl_remove(struct pci_dev *pci)
1110 {
1111     struct hdac_bus *bus = pci_get_drvdata(pci);
1112     struct skl_dev *skl = bus_to_skl(bus);
1113 
1114     cancel_work_sync(&skl->probe_work);
1115 
1116     pm_runtime_get_noresume(&pci->dev);
1117 
1118     /* codec removal, invoke bus_device_remove */
1119     snd_hdac_ext_bus_device_remove(bus);
1120 
1121     skl_platform_unregister(&pci->dev);
1122     skl_free_dsp(skl);
1123     skl_machine_device_unregister(skl);
1124     skl_dmic_device_unregister(skl);
1125     skl_clock_device_unregister(skl);
1126     skl_nhlt_remove_sysfs(skl);
1127     if (skl->nhlt)
1128         intel_nhlt_free(skl->nhlt);
1129     skl_free(bus);
1130     dev_set_drvdata(&pci->dev, NULL);
1131 }
1132 
1133 /* PCI IDs */
1134 static const struct pci_device_id skl_ids[] = {
1135 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL)
1136     /* Sunrise Point-LP */
1137     { PCI_DEVICE(0x8086, 0x9d70),
1138         .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines},
1139 #endif
1140 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL)
1141     /* BXT-P */
1142     { PCI_DEVICE(0x8086, 0x5a98),
1143         .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines},
1144 #endif
1145 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL)
1146     /* KBL */
1147     { PCI_DEVICE(0x8086, 0x9D71),
1148         .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines},
1149 #endif
1150 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK)
1151     /* GLK */
1152     { PCI_DEVICE(0x8086, 0x3198),
1153         .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines},
1154 #endif
1155 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL)
1156     /* CNL */
1157     { PCI_DEVICE(0x8086, 0x9dc8),
1158         .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1159 #endif
1160 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL)
1161     /* CFL */
1162     { PCI_DEVICE(0x8086, 0xa348),
1163         .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1164 #endif
1165 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP)
1166     /* CML-LP */
1167     { PCI_DEVICE(0x8086, 0x02c8),
1168         .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1169 #endif
1170 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H)
1171     /* CML-H */
1172     { PCI_DEVICE(0x8086, 0x06c8),
1173         .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1174 #endif
1175     { 0, }
1176 };
1177 MODULE_DEVICE_TABLE(pci, skl_ids);
1178 
1179 /* pci_driver definition */
1180 static struct pci_driver skl_driver = {
1181     .name = KBUILD_MODNAME,
1182     .id_table = skl_ids,
1183     .probe = skl_probe,
1184     .remove = skl_remove,
1185     .shutdown = skl_shutdown,
1186     .driver = {
1187         .pm = &skl_pm,
1188     },
1189 };
1190 module_pci_driver(skl_driver);
1191 
1192 MODULE_LICENSE("GPL v2");
1193 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");
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