intel/skylake/skl-topology.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  skl_topology.h - Intel HDA Platform topology header file
0004  *
0005  *  Copyright (C) 2014-15 Intel Corp
0006  *  Author: Jeeja KP <jeeja.kp@intel.com>
0007  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0008  *
0009  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0010  */
0011
0012 #ifndef __SKL_TOPOLOGY_H__
0013 #define __SKL_TOPOLOGY_H__
0014
0015 #include <linux/types.h>
0016
0017 #include <sound/hdaudio_ext.h>
0018 #include <sound/soc.h>
0019 #include <uapi/sound/skl-tplg-interface.h>
0020 #include "skl.h"
0021
0022 #define BITS_PER_BYTE 8
0023 #define MAX_TS_GROUPS 8
0024 #define MAX_DMIC_TS_GROUPS 4
0025 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
0026
0027 /* Maximum number of coefficients up down mixer module */
0028 #define UP_DOWN_MIXER_MAX_COEFF     8
0029
0030 #define MODULE_MAX_IN_PINS  8
0031 #define MODULE_MAX_OUT_PINS 8
0032
0033 #define SKL_MIC_CH_SUPPORT  4
0034 #define SKL_MIC_MAX_CH_SUPPORT  8
0035 #define SKL_DEFAULT_MIC_SEL_GAIN    0x3FF
0036 #define SKL_MIC_SEL_SWITCH  0x3
0037
0038 #define SKL_OUTPUT_PIN      0
0039 #define SKL_INPUT_PIN       1
0040 #define SKL_MAX_PATH_CONFIGS    8
0041 #define SKL_MAX_MODULES_IN_PIPE 8
0042 #define SKL_MAX_MODULE_FORMATS      32
0043 #define SKL_MAX_MODULE_RESOURCES    32
0044
0045 enum skl_channel_index {
0046     SKL_CHANNEL_LEFT = 0,
0047     SKL_CHANNEL_RIGHT = 1,
0048     SKL_CHANNEL_CENTER = 2,
0049     SKL_CHANNEL_LEFT_SURROUND = 3,
0050     SKL_CHANNEL_CENTER_SURROUND = 3,
0051     SKL_CHANNEL_RIGHT_SURROUND = 4,
0052     SKL_CHANNEL_LFE = 7,
0053     SKL_CHANNEL_INVALID = 0xF,
0054 };
0055
0056 enum skl_bitdepth {
0057     SKL_DEPTH_8BIT = 8,
0058     SKL_DEPTH_16BIT = 16,
0059     SKL_DEPTH_24BIT = 24,
0060     SKL_DEPTH_32BIT = 32,
0061     SKL_DEPTH_INVALID
0062 };
0063
0064
0065 enum skl_s_freq {
0066     SKL_FS_8000 = 8000,
0067     SKL_FS_11025 = 11025,
0068     SKL_FS_12000 = 12000,
0069     SKL_FS_16000 = 16000,
0070     SKL_FS_22050 = 22050,
0071     SKL_FS_24000 = 24000,
0072     SKL_FS_32000 = 32000,
0073     SKL_FS_44100 = 44100,
0074     SKL_FS_48000 = 48000,
0075     SKL_FS_64000 = 64000,
0076     SKL_FS_88200 = 88200,
0077     SKL_FS_96000 = 96000,
0078     SKL_FS_128000 = 128000,
0079     SKL_FS_176400 = 176400,
0080     SKL_FS_192000 = 192000,
0081     SKL_FS_INVALID
0082 };
0083
0084 #define SKL_MAX_PARAMS_TYPES    4
0085
0086 enum skl_widget_type {
0087     SKL_WIDGET_VMIXER = 1,
0088     SKL_WIDGET_MIXER = 2,
0089     SKL_WIDGET_PGA = 3,
0090     SKL_WIDGET_MUX = 4
0091 };
0092
0093 struct skl_audio_data_format {
0094     enum skl_s_freq s_freq;
0095     enum skl_bitdepth bit_depth;
0096     u32 channel_map;
0097     enum skl_ch_cfg ch_cfg;
0098     enum skl_interleaving interleaving;
0099     u8 number_of_channels;
0100     u8 valid_bit_depth;
0101     u8 sample_type;
0102     u8 reserved;
0103 } __packed;
0104
0105 struct skl_base_cfg {
0106     u32 cpc;
0107     u32 ibs;
0108     u32 obs;
0109     u32 is_pages;
0110     struct skl_audio_data_format audio_fmt;
0111 };
0112
0113 struct skl_cpr_gtw_cfg {
0114     u32 node_id;
0115     u32 dma_buffer_size;
0116     u32 config_length;
0117     /* not mandatory; required only for DMIC/I2S */
0118     u32 config_data[1];
0119 } __packed;
0120
0121 struct skl_dma_control {
0122     u32 node_id;
0123     u32 config_length;
0124     u32 config_data[];
0125 } __packed;
0126
0127 struct skl_cpr_cfg {
0128     struct skl_base_cfg base_cfg;
0129     struct skl_audio_data_format out_fmt;
0130     u32 cpr_feature_mask;
0131     struct skl_cpr_gtw_cfg gtw_cfg;
0132 } __packed;
0133
0134 struct skl_cpr_pin_fmt {
0135     u32 sink_id;
0136     struct skl_audio_data_format src_fmt;
0137     struct skl_audio_data_format dst_fmt;
0138 } __packed;
0139
0140 struct skl_src_module_cfg {
0141     struct skl_base_cfg base_cfg;
0142     enum skl_s_freq src_cfg;
0143 } __packed;
0144
0145 struct skl_up_down_mixer_cfg {
0146     struct skl_base_cfg base_cfg;
0147     enum skl_ch_cfg out_ch_cfg;
0148     /* This should be set to 1 if user coefficients are required */
0149     u32 coeff_sel;
0150     /* Pass the user coeff in this array */
0151     s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
0152     u32 ch_map;
0153 } __packed;
0154
0155 struct skl_pin_format {
0156     u32 pin_idx;
0157     u32 buf_size;
0158     struct skl_audio_data_format audio_fmt;
0159 } __packed;
0160
0161 struct skl_base_cfg_ext {
0162     u16 nr_input_pins;
0163     u16 nr_output_pins;
0164     u8 reserved[8];
0165     u32 priv_param_length;
0166     /* Input pin formats followed by output ones. */
0167     struct skl_pin_format pins_fmt[];
0168 } __packed;
0169
0170 struct skl_algo_cfg {
0171     struct skl_base_cfg  base_cfg;
0172     char params[];
0173 } __packed;
0174
0175 struct skl_base_outfmt_cfg {
0176     struct skl_base_cfg base_cfg;
0177     struct skl_audio_data_format out_fmt;
0178 } __packed;
0179
0180 enum skl_dma_type {
0181     SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
0182     SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
0183     SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
0184     SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
0185     SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
0186     SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
0187     SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
0188     SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
0189     SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
0190 };
0191
0192 union skl_ssp_dma_node {
0193     u8 val;
0194     struct {
0195         u8 time_slot_index:4;
0196         u8 i2s_instance:4;
0197     } dma_node;
0198 };
0199
0200 union skl_connector_node_id {
0201     u32 val;
0202     struct {
0203         u32 vindex:8;
0204         u32 dma_type:4;
0205         u32 rsvd:20;
0206     } node;
0207 };
0208
0209 struct skl_module_fmt {
0210     u32 channels;
0211     u32 s_freq;
0212     u32 bit_depth;
0213     u32 valid_bit_depth;
0214     u32 ch_cfg;
0215     u32 interleaving_style;
0216     u32 sample_type;
0217     u32 ch_map;
0218 };
0219
0220 struct skl_module_cfg;
0221
0222 struct skl_mod_inst_map {
0223     u16 mod_id;
0224     u16 inst_id;
0225 };
0226
0227 struct skl_uuid_inst_map {
0228     u16 inst_id;
0229     u16 reserved;
0230     guid_t mod_uuid;
0231 } __packed;
0232
0233 struct skl_kpb_params {
0234     u32 num_modules;
0235     union {
0236         struct skl_mod_inst_map map[0];
0237         struct skl_uuid_inst_map map_uuid[0];
0238     } u;
0239 };
0240
0241 struct skl_module_inst_id {
0242     guid_t mod_uuid;
0243     int module_id;
0244     u32 instance_id;
0245     int pvt_id;
0246 };
0247
0248 enum skl_module_pin_state {
0249     SKL_PIN_UNBIND = 0,
0250     SKL_PIN_BIND_DONE = 1,
0251 };
0252
0253 struct skl_module_pin {
0254     struct skl_module_inst_id id;
0255     bool is_dynamic;
0256     bool in_use;
0257     enum skl_module_pin_state pin_state;
0258     struct skl_module_cfg *tgt_mcfg;
0259 };
0260
0261 struct skl_specific_cfg {
0262     u32 set_params;
0263     u32 param_id;
0264     u32 caps_size;
0265     u32 *caps;
0266 };
0267
0268 enum skl_pipe_state {
0269     SKL_PIPE_INVALID = 0,
0270     SKL_PIPE_CREATED = 1,
0271     SKL_PIPE_PAUSED = 2,
0272     SKL_PIPE_STARTED = 3,
0273     SKL_PIPE_RESET = 4
0274 };
0275
0276 struct skl_pipe_module {
0277     struct snd_soc_dapm_widget *w;
0278     struct list_head node;
0279 };
0280
0281 struct skl_pipe_params {
0282     u8 host_dma_id;
0283     u8 link_dma_id;
0284     u32 ch;
0285     u32 s_freq;
0286     u32 s_fmt;
0287     u32 s_cont;
0288     u8 linktype;
0289     snd_pcm_format_t format;
0290     int link_index;
0291     int stream;
0292     unsigned int host_bps;
0293     unsigned int link_bps;
0294 };
0295
0296 struct skl_pipe_fmt {
0297     u32 freq;
0298     u8 channels;
0299     u8 bps;
0300 };
0301
0302 struct skl_pipe_mcfg {
0303     u8 res_idx;
0304     u8 fmt_idx;
0305 };
0306
0307 struct skl_path_config {
0308     u8 mem_pages;
0309     struct skl_pipe_fmt in_fmt;
0310     struct skl_pipe_fmt out_fmt;
0311 };
0312
0313 struct skl_pipe {
0314     u8 ppl_id;
0315     u8 pipe_priority;
0316     u16 conn_type;
0317     u32 memory_pages;
0318     u8 lp_mode;
0319     struct skl_pipe_params *p_params;
0320     enum skl_pipe_state state;
0321     u8 direction;
0322     u8 cur_config_idx;
0323     u8 nr_cfgs;
0324     struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
0325     struct list_head w_list;
0326     bool passthru;
0327     u32 pipe_config_idx;
0328 };
0329
0330 enum skl_module_state {
0331     SKL_MODULE_UNINIT = 0,
0332     SKL_MODULE_INIT_DONE = 1,
0333     SKL_MODULE_BIND_DONE = 2,
0334 };
0335
0336 enum d0i3_capability {
0337     SKL_D0I3_NONE = 0,
0338     SKL_D0I3_STREAMING = 1,
0339     SKL_D0I3_NON_STREAMING = 2,
0340 };
0341
0342 struct skl_module_pin_fmt {
0343     u8 id;
0344     struct skl_module_fmt fmt;
0345 };
0346
0347 struct skl_module_iface {
0348     u8 fmt_idx;
0349     u8 nr_in_fmt;
0350     u8 nr_out_fmt;
0351     struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
0352     struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
0353 };
0354
0355 struct skl_module_pin_resources {
0356     u8 pin_index;
0357     u32 buf_size;
0358 };
0359
0360 struct skl_module_res {
0361     u8 id;
0362     u32 is_pages;
0363     u32 ibs;
0364     u32 obs;
0365     u32 dma_buffer_size;
0366     u32 cpc;
0367     u8 nr_input_pins;
0368     u8 nr_output_pins;
0369     struct skl_module_pin_resources input[MAX_IN_QUEUE];
0370     struct skl_module_pin_resources output[MAX_OUT_QUEUE];
0371 };
0372
0373 struct skl_module {
0374     guid_t uuid;
0375     u8 loadable;
0376     u8 input_pin_type;
0377     u8 output_pin_type;
0378     u8 max_input_pins;
0379     u8 max_output_pins;
0380     u8 nr_resources;
0381     u8 nr_interfaces;
0382     struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
0383     struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
0384 };
0385
0386 struct skl_module_cfg {
0387     u8 guid[16];
0388     struct skl_module_inst_id id;
0389     struct skl_module *module;
0390     int res_idx;
0391     int fmt_idx;
0392     int fmt_cfg_idx;
0393     u8 domain;
0394     bool homogenous_inputs;
0395     bool homogenous_outputs;
0396     struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
0397     struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
0398     u8 max_in_queue;
0399     u8 max_out_queue;
0400     u8 in_queue_mask;
0401     u8 out_queue_mask;
0402     u8 in_queue;
0403     u8 out_queue;
0404     u8 is_loadable;
0405     u8 core_id;
0406     u8 dev_type;
0407     u8 dma_id;
0408     u8 time_slot;
0409     u8 dmic_ch_combo_index;
0410     u32 dmic_ch_type;
0411     u32 params_fixup;
0412     u32 converter;
0413     u32 vbus_id;
0414     u32 mem_pages;
0415     enum d0i3_capability d0i3_caps;
0416     u32 dma_buffer_size; /* in milli seconds */
0417     struct skl_module_pin *m_in_pin;
0418     struct skl_module_pin *m_out_pin;
0419     enum skl_module_type m_type;
0420     enum skl_hw_conn_type  hw_conn_type;
0421     enum skl_module_state m_state;
0422     struct skl_pipe *pipe;
0423     struct skl_specific_cfg formats_config[SKL_MAX_PARAMS_TYPES];
0424     struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
0425 };
0426
0427 struct skl_algo_data {
0428     u32 param_id;
0429     u32 set_params;
0430     u32 max;
0431     u32 size;
0432     char *params;
0433 };
0434
0435 struct skl_pipeline {
0436     struct skl_pipe *pipe;
0437     struct list_head node;
0438 };
0439
0440 struct skl_module_deferred_bind {
0441     struct skl_module_cfg *src;
0442     struct skl_module_cfg *dst;
0443     struct list_head node;
0444 };
0445
0446 struct skl_mic_sel_config {
0447     u16 mic_switch;
0448     u16 flags;
0449     u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
0450 } __packed;
0451
0452 enum skl_channel {
0453     SKL_CH_MONO = 1,
0454     SKL_CH_STEREO = 2,
0455     SKL_CH_TRIO = 3,
0456     SKL_CH_QUATRO = 4,
0457 };
0458
0459 static inline struct skl_dev *get_skl_ctx(struct device *dev)
0460 {
0461     struct hdac_bus *bus = dev_get_drvdata(dev);
0462
0463     return bus_to_skl(bus);
0464 }
0465
0466 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
0467     struct skl_pipe_params *params);
0468 int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
0469             u32 caps_size, u32 node_id);
0470 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
0471     struct skl_pipe_params *params, int stream);
0472 int skl_tplg_init(struct snd_soc_component *component,
0473                 struct hdac_bus *bus);
0474 void skl_tplg_exit(struct snd_soc_component *component,
0475                 struct hdac_bus *bus);
0476 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
0477         struct snd_soc_dai *dai, int stream);
0478 int skl_tplg_update_pipe_params(struct device *dev,
0479         struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
0480
0481 void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps);
0482 void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps);
0483
0484 int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe);
0485
0486 int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
0487
0488 int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
0489
0490 int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
0491
0492 int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
0493
0494 int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
0495
0496 int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig);
0497
0498 int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg
0499     *src_mcfg, struct skl_module_cfg *dst_mcfg);
0500
0501 int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg
0502     *src_mcfg, struct skl_module_cfg *dst_mcfg);
0503
0504 int skl_set_module_params(struct skl_dev *skl, u32 *params, int size,
0505             u32 param_id, struct skl_module_cfg *mcfg);
0506 int skl_get_module_params(struct skl_dev *skl, u32 *params, int size,
0507               u32 param_id, struct skl_module_cfg *mcfg);
0508
0509 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
0510                                 int stream);
0511 enum skl_bitdepth skl_get_bit_depth(int params);
0512 int skl_pcm_host_dma_prepare(struct device *dev,
0513             struct skl_pipe_params *params);
0514 int skl_pcm_link_dma_prepare(struct device *dev,
0515             struct skl_pipe_params *params);
0516
0517 int skl_dai_load(struct snd_soc_component *cmp, int index,
0518         struct snd_soc_dai_driver *dai_drv,
0519         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
0520 void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl,
0521                 struct snd_soc_dapm_widget *w);
0522 #endif