intel/skylake/skl-sst-cldma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Intel Code Loader DMA support
0004  *
0005  * Copyright (C) 2015, Intel Corporation.
0006  */
0007
0008 #ifndef SKL_SST_CLDMA_H_
0009 #define SKL_SST_CLDMA_H_
0010
0011 #define FW_CL_STREAM_NUMBER     0x1
0012
0013 #define DMA_ADDRESS_128_BITS_ALIGNMENT  7
0014 #define BDL_ALIGN(x)            (x >> DMA_ADDRESS_128_BITS_ALIGNMENT)
0015
0016 #define SKL_ADSPIC_CL_DMA           0x2
0017 #define SKL_ADSPIS_CL_DMA           0x2
0018 #define SKL_CL_DMA_SD_INT_DESC_ERR      0x10 /* Descriptor error interrupt */
0019 #define SKL_CL_DMA_SD_INT_FIFO_ERR      0x08 /* FIFO error interrupt */
0020 #define SKL_CL_DMA_SD_INT_COMPLETE      0x04 /* Buffer completion interrupt */
0021
0022 /* Intel HD Audio Code Loader DMA Registers */
0023
0024 #define HDA_ADSP_LOADER_BASE        0x80
0025
0026 /* Stream Registers */
0027 #define SKL_ADSP_REG_CL_SD_CTL          (HDA_ADSP_LOADER_BASE + 0x00)
0028 #define SKL_ADSP_REG_CL_SD_STS          (HDA_ADSP_LOADER_BASE + 0x03)
0029 #define SKL_ADSP_REG_CL_SD_LPIB         (HDA_ADSP_LOADER_BASE + 0x04)
0030 #define SKL_ADSP_REG_CL_SD_CBL          (HDA_ADSP_LOADER_BASE + 0x08)
0031 #define SKL_ADSP_REG_CL_SD_LVI          (HDA_ADSP_LOADER_BASE + 0x0c)
0032 #define SKL_ADSP_REG_CL_SD_FIFOW        (HDA_ADSP_LOADER_BASE + 0x0e)
0033 #define SKL_ADSP_REG_CL_SD_FIFOSIZE     (HDA_ADSP_LOADER_BASE + 0x10)
0034 #define SKL_ADSP_REG_CL_SD_FORMAT       (HDA_ADSP_LOADER_BASE + 0x12)
0035 #define SKL_ADSP_REG_CL_SD_FIFOL        (HDA_ADSP_LOADER_BASE + 0x14)
0036 #define SKL_ADSP_REG_CL_SD_BDLPL        (HDA_ADSP_LOADER_BASE + 0x18)
0037 #define SKL_ADSP_REG_CL_SD_BDLPU        (HDA_ADSP_LOADER_BASE + 0x1c)
0038
0039 /* CL: Software Position Based FIFO Capability Registers */
0040 #define SKL_ADSP_REG_CL_SPBFIFO         (HDA_ADSP_LOADER_BASE + 0x20)
0041 #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCH      (SKL_ADSP_REG_CL_SPBFIFO + 0x0)
0042 #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL    (SKL_ADSP_REG_CL_SPBFIFO + 0x4)
0043 #define SKL_ADSP_REG_CL_SPBFIFO_SPIB        (SKL_ADSP_REG_CL_SPBFIFO + 0x8)
0044 #define SKL_ADSP_REG_CL_SPBFIFO_MAXFIFOS    (SKL_ADSP_REG_CL_SPBFIFO + 0xc)
0045
0046 /* CL: Stream Descriptor x Control */
0047
0048 /* Stream Reset */
0049 #define CL_SD_CTL_SRST_SHIFT        0
0050 #define CL_SD_CTL_SRST_MASK     (1 << CL_SD_CTL_SRST_SHIFT)
0051 #define CL_SD_CTL_SRST(x)       \
0052             ((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK)
0053
0054 /* Stream Run */
0055 #define CL_SD_CTL_RUN_SHIFT     1
0056 #define CL_SD_CTL_RUN_MASK      (1 << CL_SD_CTL_RUN_SHIFT)
0057 #define CL_SD_CTL_RUN(x)        \
0058             ((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK)
0059
0060 /* Interrupt On Completion Enable */
0061 #define CL_SD_CTL_IOCE_SHIFT        2
0062 #define CL_SD_CTL_IOCE_MASK     (1 << CL_SD_CTL_IOCE_SHIFT)
0063 #define CL_SD_CTL_IOCE(x)       \
0064             ((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK)
0065
0066 /* FIFO Error Interrupt Enable */
0067 #define CL_SD_CTL_FEIE_SHIFT        3
0068 #define CL_SD_CTL_FEIE_MASK     (1 << CL_SD_CTL_FEIE_SHIFT)
0069 #define CL_SD_CTL_FEIE(x)       \
0070             ((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK)
0071
0072 /* Descriptor Error Interrupt Enable */
0073 #define CL_SD_CTL_DEIE_SHIFT        4
0074 #define CL_SD_CTL_DEIE_MASK     (1 << CL_SD_CTL_DEIE_SHIFT)
0075 #define CL_SD_CTL_DEIE(x)       \
0076             ((x << CL_SD_CTL_DEIE_SHIFT) & CL_SD_CTL_DEIE_MASK)
0077
0078 /* FIFO Limit Change */
0079 #define CL_SD_CTL_FIFOLC_SHIFT      5
0080 #define CL_SD_CTL_FIFOLC_MASK       (1 << CL_SD_CTL_FIFOLC_SHIFT)
0081 #define CL_SD_CTL_FIFOLC(x)     \
0082             ((x << CL_SD_CTL_FIFOLC_SHIFT) & CL_SD_CTL_FIFOLC_MASK)
0083
0084 /* Stripe Control */
0085 #define CL_SD_CTL_STRIPE_SHIFT      16
0086 #define CL_SD_CTL_STRIPE_MASK       (0x3 << CL_SD_CTL_STRIPE_SHIFT)
0087 #define CL_SD_CTL_STRIPE(x)     \
0088             ((x << CL_SD_CTL_STRIPE_SHIFT) & CL_SD_CTL_STRIPE_MASK)
0089
0090 /* Traffic Priority */
0091 #define CL_SD_CTL_TP_SHIFT      18
0092 #define CL_SD_CTL_TP_MASK       (1 << CL_SD_CTL_TP_SHIFT)
0093 #define CL_SD_CTL_TP(x)         \
0094             ((x << CL_SD_CTL_TP_SHIFT) & CL_SD_CTL_TP_MASK)
0095
0096 /* Bidirectional Direction Control */
0097 #define CL_SD_CTL_DIR_SHIFT     19
0098 #define CL_SD_CTL_DIR_MASK      (1 << CL_SD_CTL_DIR_SHIFT)
0099 #define CL_SD_CTL_DIR(x)        \
0100             ((x << CL_SD_CTL_DIR_SHIFT) & CL_SD_CTL_DIR_MASK)
0101
0102 /* Stream Number */
0103 #define CL_SD_CTL_STRM_SHIFT        20
0104 #define CL_SD_CTL_STRM_MASK     (0xf << CL_SD_CTL_STRM_SHIFT)
0105 #define CL_SD_CTL_STRM(x)       \
0106             ((x << CL_SD_CTL_STRM_SHIFT) & CL_SD_CTL_STRM_MASK)
0107
0108 /* CL: Stream Descriptor x Status */
0109
0110 /* Buffer Completion Interrupt Status */
0111 #define CL_SD_STS_BCIS(x)       CL_SD_CTL_IOCE(x)
0112
0113 /* FIFO Error */
0114 #define CL_SD_STS_FIFOE(x)      CL_SD_CTL_FEIE(x)
0115
0116 /* Descriptor Error */
0117 #define CL_SD_STS_DESE(x)       CL_SD_CTL_DEIE(x)
0118
0119 /* FIFO Ready */
0120 #define CL_SD_STS_FIFORDY(x)    CL_SD_CTL_FIFOLC(x)
0121
0122
0123 /* CL: Stream Descriptor x Last Valid Index */
0124 #define CL_SD_LVI_SHIFT         0
0125 #define CL_SD_LVI_MASK          (0xff << CL_SD_LVI_SHIFT)
0126 #define CL_SD_LVI(x)            ((x << CL_SD_LVI_SHIFT) & CL_SD_LVI_MASK)
0127
0128 /* CL: Stream Descriptor x FIFO Eviction Watermark */
0129 #define CL_SD_FIFOW_SHIFT       0
0130 #define CL_SD_FIFOW_MASK        (0x7 << CL_SD_FIFOW_SHIFT)
0131 #define CL_SD_FIFOW(x)          \
0132             ((x << CL_SD_FIFOW_SHIFT) & CL_SD_FIFOW_MASK)
0133
0134 /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
0135
0136 /* Protect Bits */
0137 #define CL_SD_BDLPLBA_PROT_SHIFT    0
0138 #define CL_SD_BDLPLBA_PROT_MASK     (1 << CL_SD_BDLPLBA_PROT_SHIFT)
0139 #define CL_SD_BDLPLBA_PROT(x)       \
0140         ((x << CL_SD_BDLPLBA_PROT_SHIFT) & CL_SD_BDLPLBA_PROT_MASK)
0141
0142 /* Buffer Descriptor List Lower Base Address */
0143 #define CL_SD_BDLPLBA_SHIFT     7
0144 #define CL_SD_BDLPLBA_MASK      (0x1ffffff << CL_SD_BDLPLBA_SHIFT)
0145 #define CL_SD_BDLPLBA(x)        \
0146     ((BDL_ALIGN(lower_32_bits(x)) << CL_SD_BDLPLBA_SHIFT) & CL_SD_BDLPLBA_MASK)
0147
0148 /* Buffer Descriptor List Upper Base Address */
0149 #define CL_SD_BDLPUBA_SHIFT     0
0150 #define CL_SD_BDLPUBA_MASK      (0xffffffff << CL_SD_BDLPUBA_SHIFT)
0151 #define CL_SD_BDLPUBA(x)        \
0152         ((upper_32_bits(x) << CL_SD_BDLPUBA_SHIFT) & CL_SD_BDLPUBA_MASK)
0153
0154 /*
0155  * Code Loader - Software Position Based FIFO
0156  * Capability Registers x Software Position Based FIFO Header
0157  */
0158
0159 /* Next Capability Pointer */
0160 #define CL_SPBFIFO_SPBFCH_PTR_SHIFT 0
0161 #define CL_SPBFIFO_SPBFCH_PTR_MASK  (0xff << CL_SPBFIFO_SPBFCH_PTR_SHIFT)
0162 #define CL_SPBFIFO_SPBFCH_PTR(x)    \
0163         ((x << CL_SPBFIFO_SPBFCH_PTR_SHIFT) & CL_SPBFIFO_SPBFCH_PTR_MASK)
0164
0165 /* Capability Identifier */
0166 #define CL_SPBFIFO_SPBFCH_ID_SHIFT  16
0167 #define CL_SPBFIFO_SPBFCH_ID_MASK   (0xfff << CL_SPBFIFO_SPBFCH_ID_SHIFT)
0168 #define CL_SPBFIFO_SPBFCH_ID(x)     \
0169         ((x << CL_SPBFIFO_SPBFCH_ID_SHIFT) & CL_SPBFIFO_SPBFCH_ID_MASK)
0170
0171 /* Capability Version */
0172 #define CL_SPBFIFO_SPBFCH_VER_SHIFT 28
0173 #define CL_SPBFIFO_SPBFCH_VER_MASK  (0xf << CL_SPBFIFO_SPBFCH_VER_SHIFT)
0174 #define CL_SPBFIFO_SPBFCH_VER(x)    \
0175     ((x << CL_SPBFIFO_SPBFCH_VER_SHIFT) & CL_SPBFIFO_SPBFCH_VER_MASK)
0176
0177 /* Software Position in Buffer Enable */
0178 #define CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT 0
0179 #define CL_SPBFIFO_SPBFCCTL_SPIBE_MASK  (1 << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
0180 #define CL_SPBFIFO_SPBFCCTL_SPIBE(x)    \
0181     ((x << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)
0182
0183 /* SST IPC SKL defines */
0184 #define SKL_WAIT_TIMEOUT        500 /* 500 msec */
0185 #define SKL_MAX_BUFFER_SIZE     (32 * PAGE_SIZE)
0186
0187 enum skl_cl_dma_wake_states {
0188     SKL_CL_DMA_STATUS_NONE = 0,
0189     SKL_CL_DMA_BUF_COMPLETE,
0190     SKL_CL_DMA_ERR, /* TODO: Expand the error states */
0191 };
0192
0193 struct sst_dsp;
0194
0195 struct skl_cl_dev_ops {
0196     void (*cl_setup_bdle)(struct sst_dsp *ctx,
0197             struct snd_dma_buffer *dmab_data,
0198             __le32 **bdlp, int size, int with_ioc);
0199     void (*cl_setup_controller)(struct sst_dsp *ctx,
0200             struct snd_dma_buffer *dmab_bdl,
0201             unsigned int max_size, u32 page_count);
0202     void (*cl_setup_spb)(struct sst_dsp  *ctx,
0203             unsigned int size, bool enable);
0204     void (*cl_cleanup_spb)(struct sst_dsp  *ctx);
0205     void (*cl_trigger)(struct sst_dsp  *ctx, bool enable);
0206     void (*cl_cleanup_controller)(struct sst_dsp  *ctx);
0207     int (*cl_copy_to_dmabuf)(struct sst_dsp *ctx,
0208             const void *bin, u32 size, bool wait);
0209     void (*cl_stop_dma)(struct sst_dsp *ctx);
0210 };
0211
0212 /**
0213  * skl_cl_dev - holds information for code loader dma transfer
0214  *
0215  * @dmab_data: buffer pointer
0216  * @dmab_bdl: buffer descriptor list
0217  * @bufsize: ring buffer size
0218  * @frags: Last valid buffer descriptor index in the BDL
0219  * @curr_spib_pos: Current position in ring buffer
0220  * @dma_buffer_offset: dma buffer offset
0221  * @ops: operations supported on CL dma
0222  * @wait_queue: wait queue to wake for wake event
0223  * @wake_status: DMA wake status
0224  * @wait_condition: condition to wait on wait queue
0225  * @cl_dma_lock: for synchronized access to cldma
0226  */
0227 struct skl_cl_dev {
0228     struct snd_dma_buffer dmab_data;
0229     struct snd_dma_buffer dmab_bdl;
0230
0231     unsigned int bufsize;
0232     unsigned int frags;
0233
0234     unsigned int curr_spib_pos;
0235     unsigned int dma_buffer_offset;
0236     struct skl_cl_dev_ops ops;
0237
0238     wait_queue_head_t wait_queue;
0239     int wake_status;
0240     bool wait_condition;
0241 };
0242
0243 #endif /* SKL_SST_CLDMA_H_ */