intel/skylake/skl-sst-cldma.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * skl-sst-cldma.c - Code Loader DMA handler
0004  *
0005  * Copyright (C) 2015, Intel Corporation.
0006  * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
0007  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0008  */
0009
0010 #include <linux/device.h>
0011 #include <linux/io.h>
0012 #include <linux/mm.h>
0013 #include <linux/delay.h>
0014 #include "../common/sst-dsp.h"
0015 #include "../common/sst-dsp-priv.h"
0016
0017 static void skl_cldma_int_enable(struct sst_dsp *ctx)
0018 {
0019     sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
0020                 SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
0021 }
0022
0023 void skl_cldma_int_disable(struct sst_dsp *ctx)
0024 {
0025     sst_dsp_shim_update_bits_unlocked(ctx,
0026             SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
0027 }
0028
0029 static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
0030 {
0031     unsigned char val;
0032     int timeout;
0033
0034     sst_dsp_shim_update_bits_unlocked(ctx,
0035             SKL_ADSP_REG_CL_SD_CTL,
0036             CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
0037
0038     udelay(3);
0039     timeout = 300;
0040     do {
0041         /* waiting for hardware to report that the stream Run bit set */
0042         val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
0043             CL_SD_CTL_RUN_MASK;
0044         if (enable && val)
0045             break;
0046         else if (!enable && !val)
0047             break;
0048         udelay(3);
0049     } while (--timeout);
0050
0051     if (timeout == 0)
0052         dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
0053 }
0054
0055 static void skl_cldma_stream_clear(struct sst_dsp  *ctx)
0056 {
0057     /* make sure Run bit is cleared before setting stream register */
0058     skl_cldma_stream_run(ctx, 0);
0059
0060     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0061                 CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
0062     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0063                 CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
0064     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0065                 CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
0066     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0067                 CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
0068
0069     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
0070     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
0071
0072     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
0073     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
0074 }
0075
0076 /* Code loader helper APIs */
0077 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
0078         struct snd_dma_buffer *dmab_data,
0079         __le32 **bdlp, int size, int with_ioc)
0080 {
0081     __le32 *bdl = *bdlp;
0082
0083     ctx->cl_dev.frags = 0;
0084     while (size > 0) {
0085         phys_addr_t addr = virt_to_phys(dmab_data->area +
0086                 (ctx->cl_dev.frags * ctx->cl_dev.bufsize));
0087
0088         bdl[0] = cpu_to_le32(lower_32_bits(addr));
0089         bdl[1] = cpu_to_le32(upper_32_bits(addr));
0090
0091         bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
0092
0093         size -= ctx->cl_dev.bufsize;
0094         bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
0095
0096         bdl += 4;
0097         ctx->cl_dev.frags++;
0098     }
0099 }
0100
0101 /*
0102  * Setup controller
0103  * Configure the registers to update the dma buffer address and
0104  * enable interrupts.
0105  * Note: Using the channel 1 for transfer
0106  */
0107 static void skl_cldma_setup_controller(struct sst_dsp  *ctx,
0108         struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
0109         u32 count)
0110 {
0111     skl_cldma_stream_clear(ctx);
0112     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
0113             CL_SD_BDLPLBA(dmab_bdl->addr));
0114     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
0115             CL_SD_BDLPUBA(dmab_bdl->addr));
0116
0117     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
0118     sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
0119     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0120             CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
0121     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0122             CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
0123     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0124             CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
0125     sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
0126             CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
0127 }
0128
0129 static void skl_cldma_setup_spb(struct sst_dsp  *ctx,
0130         unsigned int size, bool enable)
0131 {
0132     if (enable)
0133         sst_dsp_shim_update_bits_unlocked(ctx,
0134                 SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
0135                 CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
0136                 CL_SPBFIFO_SPBFCCTL_SPIBE(1));
0137
0138     sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
0139 }
0140
0141 static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
0142 {
0143     sst_dsp_shim_update_bits_unlocked(ctx,
0144             SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
0145             CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
0146             CL_SPBFIFO_SPBFCCTL_SPIBE(0));
0147
0148     sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
0149 }
0150
0151 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
0152 {
0153     skl_cldma_cleanup_spb(ctx);
0154     skl_cldma_stream_clear(ctx);
0155
0156     ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
0157     ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
0158 }
0159
0160 int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
0161 {
0162     int ret = 0;
0163
0164     if (!wait_event_timeout(ctx->cl_dev.wait_queue,
0165                 ctx->cl_dev.wait_condition,
0166                 msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
0167         dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
0168         ret = -EIO;
0169         goto cleanup;
0170     }
0171
0172     dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
0173     if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
0174         dev_err(ctx->dev, "%s: DMA Error\n", __func__);
0175         ret = -EIO;
0176     }
0177
0178 cleanup:
0179     ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
0180     return ret;
0181 }
0182
0183 static void skl_cldma_stop(struct sst_dsp *ctx)
0184 {
0185     skl_cldma_stream_run(ctx, false);
0186 }
0187
0188 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
0189         const void *curr_pos, bool intr_enable, bool trigger)
0190 {
0191     dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
0192     dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
0193             ctx->cl_dev.dma_buffer_offset, trigger);
0194     dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
0195
0196     /*
0197      * Check if the size exceeds buffer boundary. If it exceeds
0198      * max_buffer size, then copy till buffer size and then copy
0199      * remaining buffer from the start of ring buffer.
0200      */
0201     if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
0202         unsigned int size_b = ctx->cl_dev.bufsize -
0203                     ctx->cl_dev.dma_buffer_offset;
0204         memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
0205             curr_pos, size_b);
0206         size -= size_b;
0207         curr_pos += size_b;
0208         ctx->cl_dev.dma_buffer_offset = 0;
0209     }
0210
0211     memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
0212             curr_pos, size);
0213
0214     if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
0215         ctx->cl_dev.dma_buffer_offset = 0;
0216     else
0217         ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
0218
0219     ctx->cl_dev.wait_condition = false;
0220
0221     if (intr_enable)
0222         skl_cldma_int_enable(ctx);
0223
0224     ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
0225     if (trigger)
0226         ctx->cl_dev.ops.cl_trigger(ctx, true);
0227 }
0228
0229 /*
0230  * The CL dma doesn't have any way to update the transfer status until a BDL
0231  * buffer is fully transferred
0232  *
0233  * So Copying is divided in two parts.
0234  * 1. Interrupt on buffer done where the size to be transferred is more than
0235  *    ring buffer size.
0236  * 2. Polling on fw register to identify if data left to transferred doesn't
0237  *    fill the ring buffer. Caller takes care of polling the required status
0238  *    register to identify the transfer status.
0239  * 3. if wait flag is set, waits for DBL interrupt to copy the next chunk till
0240  *    bytes_left is 0.
0241  *    if wait flag is not set, doesn't wait for BDL interrupt. after ccopying
0242  *    the first chunk return the no of bytes_left to be copied.
0243  */
0244 static int
0245 skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
0246             u32 total_size, bool wait)
0247 {
0248     int ret;
0249     bool start = true;
0250     unsigned int excess_bytes;
0251     u32 size;
0252     unsigned int bytes_left = total_size;
0253     const void *curr_pos = bin;
0254
0255     if (total_size <= 0)
0256         return -EINVAL;
0257
0258     dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
0259
0260     while (bytes_left) {
0261         if (bytes_left > ctx->cl_dev.bufsize) {
0262
0263             /*
0264              * dma transfers only till the write pointer as
0265              * updated in spib
0266              */
0267             if (ctx->cl_dev.curr_spib_pos == 0)
0268                 ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
0269
0270             size = ctx->cl_dev.bufsize;
0271             skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
0272
0273             if (wait) {
0274                 start = false;
0275                 ret = skl_cldma_wait_interruptible(ctx);
0276                 if (ret < 0) {
0277                     skl_cldma_stop(ctx);
0278                     return ret;
0279                 }
0280             }
0281         } else {
0282             skl_cldma_int_disable(ctx);
0283
0284             if ((ctx->cl_dev.curr_spib_pos + bytes_left)
0285                             <= ctx->cl_dev.bufsize) {
0286                 ctx->cl_dev.curr_spib_pos += bytes_left;
0287             } else {
0288                 excess_bytes = bytes_left -
0289                     (ctx->cl_dev.bufsize -
0290                     ctx->cl_dev.curr_spib_pos);
0291                 ctx->cl_dev.curr_spib_pos = excess_bytes;
0292             }
0293
0294             size = bytes_left;
0295             skl_cldma_fill_buffer(ctx, size,
0296                     curr_pos, false, start);
0297         }
0298         bytes_left -= size;
0299         curr_pos = curr_pos + size;
0300         if (!wait)
0301             return bytes_left;
0302     }
0303
0304     return bytes_left;
0305 }
0306
0307 void skl_cldma_process_intr(struct sst_dsp *ctx)
0308 {
0309     u8 cl_dma_intr_status;
0310
0311     cl_dma_intr_status =
0312         sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
0313
0314     if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
0315         ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
0316     else
0317         ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
0318
0319     ctx->cl_dev.wait_condition = true;
0320     wake_up(&ctx->cl_dev.wait_queue);
0321 }
0322
0323 int skl_cldma_prepare(struct sst_dsp *ctx)
0324 {
0325     int ret;
0326     __le32 *bdl;
0327
0328     ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
0329
0330     /* Allocate cl ops */
0331     ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
0332     ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
0333     ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
0334     ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
0335     ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
0336     ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
0337     ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
0338     ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
0339
0340     /* Allocate buffer*/
0341     ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
0342             &ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
0343     if (ret < 0) {
0344         dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
0345         return ret;
0346     }
0347     /* Setup Code loader BDL */
0348     ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
0349             &ctx->cl_dev.dmab_bdl, PAGE_SIZE);
0350     if (ret < 0) {
0351         dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
0352         ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
0353         return ret;
0354     }
0355     bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
0356
0357     /* Allocate BDLs */
0358     ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
0359             &bdl, ctx->cl_dev.bufsize, 1);
0360     ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
0361             ctx->cl_dev.bufsize, ctx->cl_dev.frags);
0362
0363     ctx->cl_dev.curr_spib_pos = 0;
0364     ctx->cl_dev.dma_buffer_offset = 0;
0365     init_waitqueue_head(&ctx->cl_dev.wait_queue);
0366
0367     return ret;
0368 }