intel/skylake/skl-ssp-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  skl-ssp-clk.h - Skylake ssp clock information and ipc structure
0004  *
0005  *  Copyright (C) 2017 Intel Corp
0006  *  Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
0007  *  Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
0008  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0009  *
0010  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0011  */
0012
0013 #ifndef SOUND_SOC_SKL_SSP_CLK_H
0014 #define SOUND_SOC_SKL_SSP_CLK_H
0015
0016 #define SKL_MAX_SSP     6
0017 /* xtal/cardinal/pll, parent of ssp clocks and mclk */
0018 #define SKL_MAX_CLK_SRC     3
0019 #define SKL_MAX_SSP_CLK_TYPES   3 /* mclk, sclk, sclkfs */
0020
0021 #define SKL_MAX_CLK_CNT     (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
0022
0023 /* Max number of configurations supported for each clock */
0024 #define SKL_MAX_CLK_RATES   10
0025
0026 #define SKL_SCLK_OFS        SKL_MAX_SSP
0027 #define SKL_SCLKFS_OFS      (SKL_SCLK_OFS + SKL_MAX_SSP)
0028
0029 enum skl_clk_type {
0030     SKL_MCLK,
0031     SKL_SCLK,
0032     SKL_SCLK_FS,
0033 };
0034
0035 enum skl_clk_src_type {
0036     SKL_XTAL,
0037     SKL_CARDINAL,
0038     SKL_PLL,
0039 };
0040
0041 struct skl_clk_parent_src {
0042     u8 clk_id;
0043     const char *name;
0044     unsigned long rate;
0045     const char *parent_name;
0046 };
0047
0048 struct skl_tlv_hdr {
0049     u32 type;
0050     u32 size;
0051 };
0052
0053 struct skl_dmactrl_mclk_cfg {
0054     struct skl_tlv_hdr hdr;
0055     /* DMA Clk TLV params */
0056     u32 clk_warm_up:16;
0057     u32 mclk:1;
0058     u32 warm_up_over:1;
0059     u32 rsvd0:14;
0060     u32 clk_stop_delay:16;
0061     u32 keep_running:1;
0062     u32 clk_stop_over:1;
0063     u32 rsvd1:14;
0064 };
0065
0066 struct skl_dmactrl_sclkfs_cfg {
0067     struct skl_tlv_hdr hdr;
0068     /* DMA SClk&FS  TLV params */
0069     u32 sampling_frequency;
0070     u32 bit_depth;
0071     u32 channel_map;
0072     u32 channel_config;
0073     u32 interleaving_style;
0074     u32 number_of_channels : 8;
0075     u32 valid_bit_depth : 8;
0076     u32 sample_type : 8;
0077     u32 reserved : 8;
0078 };
0079
0080 union skl_clk_ctrl_ipc {
0081     struct skl_dmactrl_mclk_cfg mclk;
0082     struct skl_dmactrl_sclkfs_cfg sclk_fs;
0083 };
0084
0085 struct skl_clk_rate_cfg_table {
0086     unsigned long rate;
0087     union skl_clk_ctrl_ipc dma_ctl_ipc;
0088     void *config;
0089 };
0090
0091 /*
0092  * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
0093  * all possible clocks ssp can generate for that platform.
0094  */
0095 struct skl_ssp_clk {
0096     const char *name;
0097     const char *parent_name;
0098     struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
0099 };
0100
0101 struct skl_clk_pdata {
0102     struct skl_clk_parent_src *parent_clks;
0103     int num_clks;
0104     struct skl_ssp_clk *ssp_clks;
0105     void *pvt_data;
0106 };
0107
0108 #endif /* SOUND_SOC_SKL_SSP_CLK_H */