Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
0004  *
0005  *  Copyright (C) 2014-2015 Intel Corp
0006  *  Author:  Jeeja KP <jeeja.kp@intel.com>
0007  *
0008  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0009  *
0010  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0011  */
0012 
0013 #include <linux/pci.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/delay.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/soc.h>
0018 #include "skl.h"
0019 #include "skl-topology.h"
0020 #include "skl-sst-dsp.h"
0021 #include "skl-sst-ipc.h"
0022 
0023 #define HDA_MONO 1
0024 #define HDA_STEREO 2
0025 #define HDA_QUAD 4
0026 #define HDA_MAX 8
0027 
0028 static const struct snd_pcm_hardware azx_pcm_hw = {
0029     .info =         (SNDRV_PCM_INFO_MMAP |
0030                  SNDRV_PCM_INFO_INTERLEAVED |
0031                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
0032                  SNDRV_PCM_INFO_MMAP_VALID |
0033                  SNDRV_PCM_INFO_PAUSE |
0034                  SNDRV_PCM_INFO_RESUME |
0035                  SNDRV_PCM_INFO_SYNC_START |
0036                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
0037                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
0038                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
0039     .formats =      SNDRV_PCM_FMTBIT_S16_LE |
0040                 SNDRV_PCM_FMTBIT_S32_LE |
0041                 SNDRV_PCM_FMTBIT_S24_LE,
0042     .rates =        SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
0043                 SNDRV_PCM_RATE_8000,
0044     .rate_min =     8000,
0045     .rate_max =     48000,
0046     .channels_min =     1,
0047     .channels_max =     8,
0048     .buffer_bytes_max = AZX_MAX_BUF_SIZE,
0049     .period_bytes_min = 128,
0050     .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
0051     .periods_min =      2,
0052     .periods_max =      AZX_MAX_FRAG,
0053     .fifo_size =        0,
0054 };
0055 
0056 static inline
0057 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
0058 {
0059     return substream->runtime->private_data;
0060 }
0061 
0062 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
0063 {
0064     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0065     struct hdac_stream *hstream = hdac_stream(stream);
0066     struct hdac_bus *bus = hstream->bus;
0067     return bus;
0068 }
0069 
0070 static int skl_substream_alloc_pages(struct hdac_bus *bus,
0071                  struct snd_pcm_substream *substream,
0072                  size_t size)
0073 {
0074     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0075 
0076     hdac_stream(stream)->bufsize = 0;
0077     hdac_stream(stream)->period_bytes = 0;
0078     hdac_stream(stream)->format_val = 0;
0079 
0080     return 0;
0081 }
0082 
0083 static void skl_set_pcm_constrains(struct hdac_bus *bus,
0084                  struct snd_pcm_runtime *runtime)
0085 {
0086     snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
0087 
0088     /* avoid wrap-around with wall-clock */
0089     snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
0090                      20, 178000000);
0091 }
0092 
0093 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
0094 {
0095     if (bus->ppcap)
0096         return HDAC_EXT_STREAM_TYPE_HOST;
0097     else
0098         return HDAC_EXT_STREAM_TYPE_COUPLED;
0099 }
0100 
0101 /*
0102  * check if the stream opened is marked as ignore_suspend by machine, if so
0103  * then enable suspend_active refcount
0104  *
0105  * The count supend_active does not need lock as it is used in open/close
0106  * and suspend context
0107  */
0108 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
0109                      struct snd_soc_dai *dai, bool enable)
0110 {
0111     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
0112     struct snd_soc_dapm_widget *w;
0113     struct skl_dev *skl = bus_to_skl(bus);
0114 
0115     w = snd_soc_dai_get_widget(dai, substream->stream);
0116 
0117     if (w->ignore_suspend && enable)
0118         skl->supend_active++;
0119     else if (w->ignore_suspend && !enable)
0120         skl->supend_active--;
0121 }
0122 
0123 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
0124 {
0125     struct hdac_bus *bus = dev_get_drvdata(dev);
0126     struct skl_dev *skl = bus_to_skl(bus);
0127     unsigned int format_val;
0128     struct hdac_stream *hstream;
0129     struct hdac_ext_stream *stream;
0130     int err;
0131 
0132     hstream = snd_hdac_get_stream(bus, params->stream,
0133                     params->host_dma_id + 1);
0134     if (!hstream)
0135         return -EINVAL;
0136 
0137     stream = stream_to_hdac_ext_stream(hstream);
0138     snd_hdac_ext_stream_decouple(bus, stream, true);
0139 
0140     format_val = snd_hdac_calc_stream_format(params->s_freq,
0141             params->ch, params->format, params->host_bps, 0);
0142 
0143     dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
0144         format_val, params->s_freq, params->ch, params->format);
0145 
0146     snd_hdac_stream_reset(hdac_stream(stream));
0147     err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
0148     if (err < 0)
0149         return err;
0150 
0151     /*
0152      * The recommended SDxFMT programming sequence for BXT
0153      * platforms is to couple the stream before writing the format
0154      */
0155     if (IS_BXT(skl->pci)) {
0156         snd_hdac_ext_stream_decouple(bus, stream, false);
0157         err = snd_hdac_stream_setup(hdac_stream(stream));
0158         snd_hdac_ext_stream_decouple(bus, stream, true);
0159     } else {
0160         err = snd_hdac_stream_setup(hdac_stream(stream));
0161     }
0162 
0163     if (err < 0)
0164         return err;
0165 
0166     hdac_stream(stream)->prepared = 1;
0167 
0168     return 0;
0169 }
0170 
0171 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
0172 {
0173     struct hdac_bus *bus = dev_get_drvdata(dev);
0174     unsigned int format_val;
0175     struct hdac_stream *hstream;
0176     struct hdac_ext_stream *stream;
0177     struct hdac_ext_link *link;
0178     unsigned char stream_tag;
0179 
0180     hstream = snd_hdac_get_stream(bus, params->stream,
0181                     params->link_dma_id + 1);
0182     if (!hstream)
0183         return -EINVAL;
0184 
0185     stream = stream_to_hdac_ext_stream(hstream);
0186     snd_hdac_ext_stream_decouple(bus, stream, true);
0187     format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
0188                     params->format, params->link_bps, 0);
0189 
0190     dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
0191         format_val, params->s_freq, params->ch, params->format);
0192 
0193     snd_hdac_ext_link_stream_reset(stream);
0194 
0195     snd_hdac_ext_link_stream_setup(stream, format_val);
0196 
0197     stream_tag = hstream->stream_tag;
0198     if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
0199         list_for_each_entry(link, &bus->hlink_list, list) {
0200             if (link->index == params->link_index)
0201                 snd_hdac_ext_link_set_stream_id(link,
0202                                 stream_tag);
0203         }
0204     }
0205 
0206     stream->link_prepared = 1;
0207 
0208     return 0;
0209 }
0210 
0211 static int skl_pcm_open(struct snd_pcm_substream *substream,
0212         struct snd_soc_dai *dai)
0213 {
0214     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
0215     struct hdac_ext_stream *stream;
0216     struct snd_pcm_runtime *runtime = substream->runtime;
0217     struct skl_dma_params *dma_params;
0218     struct skl_dev *skl = get_skl_ctx(dai->dev);
0219     struct skl_module_cfg *mconfig;
0220 
0221     dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
0222 
0223     stream = snd_hdac_ext_stream_assign(bus, substream,
0224                     skl_get_host_stream_type(bus));
0225     if (stream == NULL)
0226         return -EBUSY;
0227 
0228     skl_set_pcm_constrains(bus, runtime);
0229 
0230     /*
0231      * disable WALLCLOCK timestamps for capture streams
0232      * until we figure out how to handle digital inputs
0233      */
0234     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
0235         runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
0236         runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
0237     }
0238 
0239     runtime->private_data = stream;
0240 
0241     dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
0242     if (!dma_params)
0243         return -ENOMEM;
0244 
0245     dma_params->stream_tag = hdac_stream(stream)->stream_tag;
0246     snd_soc_dai_set_dma_data(dai, substream, dma_params);
0247 
0248     dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
0249                  dma_params->stream_tag);
0250     skl_set_suspend_active(substream, dai, true);
0251     snd_pcm_set_sync(substream);
0252 
0253     mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
0254     if (!mconfig)
0255         return -EINVAL;
0256 
0257     skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
0258 
0259     return 0;
0260 }
0261 
0262 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
0263         struct snd_soc_dai *dai)
0264 {
0265     struct skl_dev *skl = get_skl_ctx(dai->dev);
0266     struct skl_module_cfg *mconfig;
0267     int ret;
0268 
0269     dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
0270 
0271     mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
0272 
0273     /*
0274      * In case of XRUN recovery or in the case when the application
0275      * calls prepare another time, reset the FW pipe to clean state
0276      */
0277     if (mconfig &&
0278         (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
0279          mconfig->pipe->state == SKL_PIPE_CREATED ||
0280          mconfig->pipe->state == SKL_PIPE_PAUSED)) {
0281 
0282         ret = skl_reset_pipe(skl, mconfig->pipe);
0283 
0284         if (ret < 0)
0285             return ret;
0286 
0287         ret = skl_pcm_host_dma_prepare(dai->dev,
0288                     mconfig->pipe->p_params);
0289         if (ret < 0)
0290             return ret;
0291     }
0292 
0293     return 0;
0294 }
0295 
0296 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
0297                 struct snd_pcm_hw_params *params,
0298                 struct snd_soc_dai *dai)
0299 {
0300     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
0301     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0302     struct snd_pcm_runtime *runtime = substream->runtime;
0303     struct skl_pipe_params p_params = {0};
0304     struct skl_module_cfg *m_cfg;
0305     int ret, dma_id;
0306 
0307     dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
0308     ret = skl_substream_alloc_pages(bus, substream,
0309                       params_buffer_bytes(params));
0310     if (ret < 0)
0311         return ret;
0312 
0313     dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
0314             runtime->rate, runtime->channels, runtime->format);
0315 
0316     dma_id = hdac_stream(stream)->stream_tag - 1;
0317     dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
0318 
0319     p_params.s_fmt = snd_pcm_format_width(params_format(params));
0320     p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
0321     p_params.ch = params_channels(params);
0322     p_params.s_freq = params_rate(params);
0323     p_params.host_dma_id = dma_id;
0324     p_params.stream = substream->stream;
0325     p_params.format = params_format(params);
0326     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0327         p_params.host_bps = dai->driver->playback.sig_bits;
0328     else
0329         p_params.host_bps = dai->driver->capture.sig_bits;
0330 
0331 
0332     m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
0333     if (m_cfg)
0334         skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
0335 
0336     return 0;
0337 }
0338 
0339 static void skl_pcm_close(struct snd_pcm_substream *substream,
0340         struct snd_soc_dai *dai)
0341 {
0342     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0343     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
0344     struct skl_dma_params *dma_params = NULL;
0345     struct skl_dev *skl = bus_to_skl(bus);
0346     struct skl_module_cfg *mconfig;
0347 
0348     dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
0349 
0350     snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
0351 
0352     dma_params = snd_soc_dai_get_dma_data(dai, substream);
0353     /*
0354      * now we should set this to NULL as we are freeing by the
0355      * dma_params
0356      */
0357     snd_soc_dai_set_dma_data(dai, substream, NULL);
0358     skl_set_suspend_active(substream, dai, false);
0359 
0360     /*
0361      * check if close is for "Reference Pin" and set back the
0362      * CGCTL.MISCBDCGE if disabled by driver
0363      */
0364     if (!strncmp(dai->name, "Reference Pin", 13) &&
0365             skl->miscbdcg_disabled) {
0366         skl->enable_miscbdcge(dai->dev, true);
0367         skl->miscbdcg_disabled = false;
0368     }
0369 
0370     mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
0371     if (mconfig)
0372         skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
0373 
0374     kfree(dma_params);
0375 }
0376 
0377 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
0378         struct snd_soc_dai *dai)
0379 {
0380     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0381     struct skl_dev *skl = get_skl_ctx(dai->dev);
0382     struct skl_module_cfg *mconfig;
0383     int ret;
0384 
0385     dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
0386 
0387     mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
0388 
0389     if (mconfig) {
0390         ret = skl_reset_pipe(skl, mconfig->pipe);
0391         if (ret < 0)
0392             dev_err(dai->dev, "%s:Reset failed ret =%d",
0393                         __func__, ret);
0394     }
0395 
0396     snd_hdac_stream_cleanup(hdac_stream(stream));
0397     hdac_stream(stream)->prepared = 0;
0398 
0399     return 0;
0400 }
0401 
0402 static int skl_be_hw_params(struct snd_pcm_substream *substream,
0403                 struct snd_pcm_hw_params *params,
0404                 struct snd_soc_dai *dai)
0405 {
0406     struct skl_pipe_params p_params = {0};
0407 
0408     p_params.s_fmt = snd_pcm_format_width(params_format(params));
0409     p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
0410     p_params.ch = params_channels(params);
0411     p_params.s_freq = params_rate(params);
0412     p_params.stream = substream->stream;
0413 
0414     return skl_tplg_be_update_params(dai, &p_params);
0415 }
0416 
0417 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
0418         int cmd)
0419 {
0420     struct hdac_bus *bus = get_bus_ctx(substream);
0421     struct hdac_ext_stream *stream;
0422     int start;
0423     unsigned long cookie;
0424     struct hdac_stream *hstr;
0425 
0426     stream = get_hdac_ext_stream(substream);
0427     hstr = hdac_stream(stream);
0428 
0429     if (!hstr->prepared)
0430         return -EPIPE;
0431 
0432     switch (cmd) {
0433     case SNDRV_PCM_TRIGGER_START:
0434     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0435     case SNDRV_PCM_TRIGGER_RESUME:
0436         start = 1;
0437         break;
0438 
0439     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0440     case SNDRV_PCM_TRIGGER_SUSPEND:
0441     case SNDRV_PCM_TRIGGER_STOP:
0442         start = 0;
0443         break;
0444 
0445     default:
0446         return -EINVAL;
0447     }
0448 
0449     spin_lock_irqsave(&bus->reg_lock, cookie);
0450 
0451     if (start) {
0452         snd_hdac_stream_start(hdac_stream(stream), true);
0453         snd_hdac_stream_timecounter_init(hstr, 0);
0454     } else {
0455         snd_hdac_stream_stop(hdac_stream(stream));
0456     }
0457 
0458     spin_unlock_irqrestore(&bus->reg_lock, cookie);
0459 
0460     return 0;
0461 }
0462 
0463 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
0464         struct snd_soc_dai *dai)
0465 {
0466     struct skl_dev *skl = get_skl_ctx(dai->dev);
0467     struct skl_module_cfg *mconfig;
0468     struct hdac_bus *bus = get_bus_ctx(substream);
0469     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0470     struct snd_soc_dapm_widget *w;
0471     int ret;
0472 
0473     mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
0474     if (!mconfig)
0475         return -EIO;
0476 
0477     w = snd_soc_dai_get_widget(dai, substream->stream);
0478 
0479     switch (cmd) {
0480     case SNDRV_PCM_TRIGGER_RESUME:
0481         if (!w->ignore_suspend) {
0482             /*
0483              * enable DMA Resume enable bit for the stream, set the
0484              * dpib & lpib position to resume before starting the
0485              * DMA
0486              */
0487             snd_hdac_ext_stream_drsm_enable(bus, true,
0488                         hdac_stream(stream)->index);
0489             snd_hdac_ext_stream_set_dpibr(bus, stream,
0490                             stream->lpib);
0491             snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
0492         }
0493         fallthrough;
0494 
0495     case SNDRV_PCM_TRIGGER_START:
0496     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0497         /*
0498          * Start HOST DMA and Start FE Pipe.This is to make sure that
0499          * there are no underrun/overrun in the case when the FE
0500          * pipeline is started but there is a delay in starting the
0501          * DMA channel on the host.
0502          */
0503         ret = skl_decoupled_trigger(substream, cmd);
0504         if (ret < 0)
0505             return ret;
0506         return skl_run_pipe(skl, mconfig->pipe);
0507 
0508     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0509     case SNDRV_PCM_TRIGGER_SUSPEND:
0510     case SNDRV_PCM_TRIGGER_STOP:
0511         /*
0512          * Stop FE Pipe first and stop DMA. This is to make sure that
0513          * there are no underrun/overrun in the case if there is a delay
0514          * between the two operations.
0515          */
0516         ret = skl_stop_pipe(skl, mconfig->pipe);
0517         if (ret < 0)
0518             return ret;
0519 
0520         ret = skl_decoupled_trigger(substream, cmd);
0521         if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
0522             /* save the dpib and lpib positions */
0523             stream->dpib = readl(bus->remap_addr +
0524                     AZX_REG_VS_SDXDPIB_XBASE +
0525                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
0526                     hdac_stream(stream)->index));
0527 
0528             stream->lpib = snd_hdac_stream_get_pos_lpib(
0529                             hdac_stream(stream));
0530             snd_hdac_ext_stream_decouple(bus, stream, false);
0531         }
0532         break;
0533 
0534     default:
0535         return -EINVAL;
0536     }
0537 
0538     return 0;
0539 }
0540 
0541 
0542 static int skl_link_hw_params(struct snd_pcm_substream *substream,
0543                 struct snd_pcm_hw_params *params,
0544                 struct snd_soc_dai *dai)
0545 {
0546     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
0547     struct hdac_ext_stream *link_dev;
0548     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0549     struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
0550     struct skl_pipe_params p_params = {0};
0551     struct hdac_ext_link *link;
0552     int stream_tag;
0553 
0554     link_dev = snd_hdac_ext_stream_assign(bus, substream,
0555                     HDAC_EXT_STREAM_TYPE_LINK);
0556     if (!link_dev)
0557         return -EBUSY;
0558 
0559     snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
0560 
0561     link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
0562     if (!link)
0563         return -EINVAL;
0564 
0565     stream_tag = hdac_stream(link_dev)->stream_tag;
0566 
0567     /* set the hdac_stream in the codec dai */
0568     snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
0569 
0570     p_params.s_fmt = snd_pcm_format_width(params_format(params));
0571     p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
0572     p_params.ch = params_channels(params);
0573     p_params.s_freq = params_rate(params);
0574     p_params.stream = substream->stream;
0575     p_params.link_dma_id = stream_tag - 1;
0576     p_params.link_index = link->index;
0577     p_params.format = params_format(params);
0578 
0579     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0580         p_params.link_bps = codec_dai->driver->playback.sig_bits;
0581     else
0582         p_params.link_bps = codec_dai->driver->capture.sig_bits;
0583 
0584     return skl_tplg_be_update_params(dai, &p_params);
0585 }
0586 
0587 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
0588         struct snd_soc_dai *dai)
0589 {
0590     struct skl_dev *skl = get_skl_ctx(dai->dev);
0591     struct skl_module_cfg *mconfig = NULL;
0592 
0593     /* In case of XRUN recovery, reset the FW pipe to clean state */
0594     mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
0595     if (mconfig && !mconfig->pipe->passthru &&
0596         (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
0597         skl_reset_pipe(skl, mconfig->pipe);
0598 
0599     return 0;
0600 }
0601 
0602 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
0603     int cmd, struct snd_soc_dai *dai)
0604 {
0605     struct hdac_ext_stream *link_dev =
0606                 snd_soc_dai_get_dma_data(dai, substream);
0607     struct hdac_bus *bus = get_bus_ctx(substream);
0608     struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
0609 
0610     dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
0611     switch (cmd) {
0612     case SNDRV_PCM_TRIGGER_RESUME:
0613     case SNDRV_PCM_TRIGGER_START:
0614     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0615         snd_hdac_ext_link_stream_start(link_dev);
0616         break;
0617 
0618     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0619     case SNDRV_PCM_TRIGGER_SUSPEND:
0620     case SNDRV_PCM_TRIGGER_STOP:
0621         snd_hdac_ext_link_stream_clear(link_dev);
0622         if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
0623             snd_hdac_ext_stream_decouple(bus, stream, false);
0624         break;
0625 
0626     default:
0627         return -EINVAL;
0628     }
0629     return 0;
0630 }
0631 
0632 static int skl_link_hw_free(struct snd_pcm_substream *substream,
0633         struct snd_soc_dai *dai)
0634 {
0635     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
0636     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0637     struct hdac_ext_stream *link_dev =
0638                 snd_soc_dai_get_dma_data(dai, substream);
0639     struct hdac_ext_link *link;
0640     unsigned char stream_tag;
0641 
0642     dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
0643 
0644     link_dev->link_prepared = 0;
0645 
0646     link = snd_hdac_ext_bus_get_link(bus, asoc_rtd_to_codec(rtd, 0)->component->name);
0647     if (!link)
0648         return -EINVAL;
0649 
0650     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0651         stream_tag = hdac_stream(link_dev)->stream_tag;
0652         snd_hdac_ext_link_clear_stream_id(link, stream_tag);
0653     }
0654 
0655     snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
0656     return 0;
0657 }
0658 
0659 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
0660     .startup = skl_pcm_open,
0661     .shutdown = skl_pcm_close,
0662     .prepare = skl_pcm_prepare,
0663     .hw_params = skl_pcm_hw_params,
0664     .hw_free = skl_pcm_hw_free,
0665     .trigger = skl_pcm_trigger,
0666 };
0667 
0668 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
0669     .hw_params = skl_be_hw_params,
0670 };
0671 
0672 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
0673     .hw_params = skl_be_hw_params,
0674 };
0675 
0676 static const struct snd_soc_dai_ops skl_link_dai_ops = {
0677     .prepare = skl_link_pcm_prepare,
0678     .hw_params = skl_link_hw_params,
0679     .hw_free = skl_link_hw_free,
0680     .trigger = skl_link_pcm_trigger,
0681 };
0682 
0683 static struct snd_soc_dai_driver skl_fe_dai[] = {
0684 {
0685     .name = "System Pin",
0686     .ops = &skl_pcm_dai_ops,
0687     .playback = {
0688         .stream_name = "System Playback",
0689         .channels_min = HDA_MONO,
0690         .channels_max = HDA_STEREO,
0691         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
0692         .formats = SNDRV_PCM_FMTBIT_S16_LE |
0693             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0694         .sig_bits = 32,
0695     },
0696     .capture = {
0697         .stream_name = "System Capture",
0698         .channels_min = HDA_MONO,
0699         .channels_max = HDA_STEREO,
0700         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
0701         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
0702         .sig_bits = 32,
0703     },
0704 },
0705 {
0706     .name = "System Pin2",
0707     .ops = &skl_pcm_dai_ops,
0708     .playback = {
0709         .stream_name = "Headset Playback",
0710         .channels_min = HDA_MONO,
0711         .channels_max = HDA_STEREO,
0712         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
0713             SNDRV_PCM_RATE_8000,
0714         .formats = SNDRV_PCM_FMTBIT_S16_LE |
0715             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0716     },
0717 },
0718 {
0719     .name = "Echoref Pin",
0720     .ops = &skl_pcm_dai_ops,
0721     .capture = {
0722         .stream_name = "Echoreference Capture",
0723         .channels_min = HDA_STEREO,
0724         .channels_max = HDA_STEREO,
0725         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
0726             SNDRV_PCM_RATE_8000,
0727         .formats = SNDRV_PCM_FMTBIT_S16_LE |
0728             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0729     },
0730 },
0731 {
0732     .name = "Reference Pin",
0733     .ops = &skl_pcm_dai_ops,
0734     .capture = {
0735         .stream_name = "Reference Capture",
0736         .channels_min = HDA_MONO,
0737         .channels_max = HDA_QUAD,
0738         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
0739         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
0740         .sig_bits = 32,
0741     },
0742 },
0743 {
0744     .name = "Deepbuffer Pin",
0745     .ops = &skl_pcm_dai_ops,
0746     .playback = {
0747         .stream_name = "Deepbuffer Playback",
0748         .channels_min = HDA_STEREO,
0749         .channels_max = HDA_STEREO,
0750         .rates = SNDRV_PCM_RATE_48000,
0751         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
0752         .sig_bits = 32,
0753     },
0754 },
0755 {
0756     .name = "LowLatency Pin",
0757     .ops = &skl_pcm_dai_ops,
0758     .playback = {
0759         .stream_name = "Low Latency Playback",
0760         .channels_min = HDA_STEREO,
0761         .channels_max = HDA_STEREO,
0762         .rates = SNDRV_PCM_RATE_48000,
0763         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
0764         .sig_bits = 32,
0765     },
0766 },
0767 {
0768     .name = "DMIC Pin",
0769     .ops = &skl_pcm_dai_ops,
0770     .capture = {
0771         .stream_name = "DMIC Capture",
0772         .channels_min = HDA_MONO,
0773         .channels_max = HDA_QUAD,
0774         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
0775         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
0776         .sig_bits = 32,
0777     },
0778 },
0779 {
0780     .name = "HDMI1 Pin",
0781     .ops = &skl_pcm_dai_ops,
0782     .playback = {
0783         .stream_name = "HDMI1 Playback",
0784         .channels_min = HDA_STEREO,
0785         .channels_max = 8,
0786         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
0787             SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
0788             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
0789             SNDRV_PCM_RATE_192000,
0790         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
0791             SNDRV_PCM_FMTBIT_S32_LE,
0792         .sig_bits = 32,
0793     },
0794 },
0795 {
0796     .name = "HDMI2 Pin",
0797     .ops = &skl_pcm_dai_ops,
0798     .playback = {
0799         .stream_name = "HDMI2 Playback",
0800         .channels_min = HDA_STEREO,
0801         .channels_max = 8,
0802         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
0803             SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
0804             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
0805             SNDRV_PCM_RATE_192000,
0806         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
0807             SNDRV_PCM_FMTBIT_S32_LE,
0808         .sig_bits = 32,
0809     },
0810 },
0811 {
0812     .name = "HDMI3 Pin",
0813     .ops = &skl_pcm_dai_ops,
0814     .playback = {
0815         .stream_name = "HDMI3 Playback",
0816         .channels_min = HDA_STEREO,
0817         .channels_max = 8,
0818         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
0819             SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
0820             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
0821             SNDRV_PCM_RATE_192000,
0822         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
0823             SNDRV_PCM_FMTBIT_S32_LE,
0824         .sig_bits = 32,
0825     },
0826 },
0827 };
0828 
0829 /* BE CPU  Dais */
0830 static struct snd_soc_dai_driver skl_platform_dai[] = {
0831 {
0832     .name = "SSP0 Pin",
0833     .ops = &skl_be_ssp_dai_ops,
0834     .playback = {
0835         .stream_name = "ssp0 Tx",
0836         .channels_min = HDA_STEREO,
0837         .channels_max = HDA_STEREO,
0838         .rates = SNDRV_PCM_RATE_48000,
0839         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0840     },
0841     .capture = {
0842         .stream_name = "ssp0 Rx",
0843         .channels_min = HDA_STEREO,
0844         .channels_max = HDA_STEREO,
0845         .rates = SNDRV_PCM_RATE_48000,
0846         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0847     },
0848 },
0849 {
0850     .name = "SSP1 Pin",
0851     .ops = &skl_be_ssp_dai_ops,
0852     .playback = {
0853         .stream_name = "ssp1 Tx",
0854         .channels_min = HDA_STEREO,
0855         .channels_max = HDA_STEREO,
0856         .rates = SNDRV_PCM_RATE_48000,
0857         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0858     },
0859     .capture = {
0860         .stream_name = "ssp1 Rx",
0861         .channels_min = HDA_STEREO,
0862         .channels_max = HDA_STEREO,
0863         .rates = SNDRV_PCM_RATE_48000,
0864         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0865     },
0866 },
0867 {
0868     .name = "SSP2 Pin",
0869     .ops = &skl_be_ssp_dai_ops,
0870     .playback = {
0871         .stream_name = "ssp2 Tx",
0872         .channels_min = HDA_STEREO,
0873         .channels_max = HDA_STEREO,
0874         .rates = SNDRV_PCM_RATE_48000,
0875         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0876     },
0877     .capture = {
0878         .stream_name = "ssp2 Rx",
0879         .channels_min = HDA_STEREO,
0880         .channels_max = HDA_STEREO,
0881         .rates = SNDRV_PCM_RATE_48000,
0882         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0883     },
0884 },
0885 {
0886     .name = "SSP3 Pin",
0887     .ops = &skl_be_ssp_dai_ops,
0888     .playback = {
0889         .stream_name = "ssp3 Tx",
0890         .channels_min = HDA_STEREO,
0891         .channels_max = HDA_STEREO,
0892         .rates = SNDRV_PCM_RATE_48000,
0893         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0894     },
0895     .capture = {
0896         .stream_name = "ssp3 Rx",
0897         .channels_min = HDA_STEREO,
0898         .channels_max = HDA_STEREO,
0899         .rates = SNDRV_PCM_RATE_48000,
0900         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0901     },
0902 },
0903 {
0904     .name = "SSP4 Pin",
0905     .ops = &skl_be_ssp_dai_ops,
0906     .playback = {
0907         .stream_name = "ssp4 Tx",
0908         .channels_min = HDA_STEREO,
0909         .channels_max = HDA_STEREO,
0910         .rates = SNDRV_PCM_RATE_48000,
0911         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0912     },
0913     .capture = {
0914         .stream_name = "ssp4 Rx",
0915         .channels_min = HDA_STEREO,
0916         .channels_max = HDA_STEREO,
0917         .rates = SNDRV_PCM_RATE_48000,
0918         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0919     },
0920 },
0921 {
0922     .name = "SSP5 Pin",
0923     .ops = &skl_be_ssp_dai_ops,
0924     .playback = {
0925         .stream_name = "ssp5 Tx",
0926         .channels_min = HDA_STEREO,
0927         .channels_max = HDA_STEREO,
0928         .rates = SNDRV_PCM_RATE_48000,
0929         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0930     },
0931     .capture = {
0932         .stream_name = "ssp5 Rx",
0933         .channels_min = HDA_STEREO,
0934         .channels_max = HDA_STEREO,
0935         .rates = SNDRV_PCM_RATE_48000,
0936         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0937     },
0938 },
0939 {
0940     .name = "iDisp1 Pin",
0941     .ops = &skl_link_dai_ops,
0942     .playback = {
0943         .stream_name = "iDisp1 Tx",
0944         .channels_min = HDA_STEREO,
0945         .channels_max = 8,
0946         .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
0947         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
0948             SNDRV_PCM_FMTBIT_S24_LE,
0949     },
0950 },
0951 {
0952     .name = "iDisp2 Pin",
0953     .ops = &skl_link_dai_ops,
0954     .playback = {
0955         .stream_name = "iDisp2 Tx",
0956         .channels_min = HDA_STEREO,
0957         .channels_max = 8,
0958         .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
0959             SNDRV_PCM_RATE_48000,
0960         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
0961             SNDRV_PCM_FMTBIT_S24_LE,
0962     },
0963 },
0964 {
0965     .name = "iDisp3 Pin",
0966     .ops = &skl_link_dai_ops,
0967     .playback = {
0968         .stream_name = "iDisp3 Tx",
0969         .channels_min = HDA_STEREO,
0970         .channels_max = 8,
0971         .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
0972             SNDRV_PCM_RATE_48000,
0973         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
0974             SNDRV_PCM_FMTBIT_S24_LE,
0975     },
0976 },
0977 {
0978     .name = "DMIC01 Pin",
0979     .ops = &skl_dmic_dai_ops,
0980     .capture = {
0981         .stream_name = "DMIC01 Rx",
0982         .channels_min = HDA_MONO,
0983         .channels_max = HDA_QUAD,
0984         .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
0985         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
0986     },
0987 },
0988 {
0989     .name = "DMIC16k Pin",
0990     .ops = &skl_dmic_dai_ops,
0991     .capture = {
0992         .stream_name = "DMIC16k Rx",
0993         .channels_min = HDA_MONO,
0994         .channels_max = HDA_QUAD,
0995         .rates = SNDRV_PCM_RATE_16000,
0996         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0997     },
0998 },
0999 {
1000     .name = "Analog CPU DAI",
1001     .ops = &skl_link_dai_ops,
1002     .playback = {
1003         .stream_name = "Analog CPU Playback",
1004         .channels_min = HDA_MONO,
1005         .channels_max = HDA_MAX,
1006         .rates = SNDRV_PCM_RATE_8000_192000,
1007         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1008             SNDRV_PCM_FMTBIT_S32_LE,
1009     },
1010     .capture = {
1011         .stream_name = "Analog CPU Capture",
1012         .channels_min = HDA_MONO,
1013         .channels_max = HDA_MAX,
1014         .rates = SNDRV_PCM_RATE_8000_192000,
1015         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1016             SNDRV_PCM_FMTBIT_S32_LE,
1017     },
1018 },
1019 {
1020     .name = "Alt Analog CPU DAI",
1021     .ops = &skl_link_dai_ops,
1022     .playback = {
1023         .stream_name = "Alt Analog CPU Playback",
1024         .channels_min = HDA_MONO,
1025         .channels_max = HDA_MAX,
1026         .rates = SNDRV_PCM_RATE_8000_192000,
1027         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1028             SNDRV_PCM_FMTBIT_S32_LE,
1029     },
1030     .capture = {
1031         .stream_name = "Alt Analog CPU Capture",
1032         .channels_min = HDA_MONO,
1033         .channels_max = HDA_MAX,
1034         .rates = SNDRV_PCM_RATE_8000_192000,
1035         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1036             SNDRV_PCM_FMTBIT_S32_LE,
1037     },
1038 },
1039 {
1040     .name = "Digital CPU DAI",
1041     .ops = &skl_link_dai_ops,
1042     .playback = {
1043         .stream_name = "Digital CPU Playback",
1044         .channels_min = HDA_MONO,
1045         .channels_max = HDA_MAX,
1046         .rates = SNDRV_PCM_RATE_8000_192000,
1047         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1048             SNDRV_PCM_FMTBIT_S32_LE,
1049     },
1050     .capture = {
1051         .stream_name = "Digital CPU Capture",
1052         .channels_min = HDA_MONO,
1053         .channels_max = HDA_MAX,
1054         .rates = SNDRV_PCM_RATE_8000_192000,
1055         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1056             SNDRV_PCM_FMTBIT_S32_LE,
1057     },
1058 },
1059 };
1060 
1061 int skl_dai_load(struct snd_soc_component *cmp, int index,
1062             struct snd_soc_dai_driver *dai_drv,
1063             struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1064 {
1065     dai_drv->ops = &skl_pcm_dai_ops;
1066 
1067     return 0;
1068 }
1069 
1070 static int skl_platform_soc_open(struct snd_soc_component *component,
1071                  struct snd_pcm_substream *substream)
1072 {
1073     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1074     struct snd_soc_dai_link *dai_link = rtd->dai_link;
1075 
1076     dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1077                     dai_link->cpus->dai_name);
1078 
1079     snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1080 
1081     return 0;
1082 }
1083 
1084 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1085                     int cmd)
1086 {
1087     struct hdac_bus *bus = get_bus_ctx(substream);
1088     struct hdac_ext_stream *stream;
1089     struct snd_pcm_substream *s;
1090     bool start;
1091     int sbits = 0;
1092     unsigned long cookie;
1093     struct hdac_stream *hstr;
1094 
1095     stream = get_hdac_ext_stream(substream);
1096     hstr = hdac_stream(stream);
1097 
1098     dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1099 
1100     if (!hstr->prepared)
1101         return -EPIPE;
1102 
1103     switch (cmd) {
1104     case SNDRV_PCM_TRIGGER_START:
1105     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1106     case SNDRV_PCM_TRIGGER_RESUME:
1107         start = true;
1108         break;
1109 
1110     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1111     case SNDRV_PCM_TRIGGER_SUSPEND:
1112     case SNDRV_PCM_TRIGGER_STOP:
1113         start = false;
1114         break;
1115 
1116     default:
1117         return -EINVAL;
1118     }
1119 
1120     snd_pcm_group_for_each_entry(s, substream) {
1121         if (s->pcm->card != substream->pcm->card)
1122             continue;
1123         stream = get_hdac_ext_stream(s);
1124         sbits |= 1 << hdac_stream(stream)->index;
1125         snd_pcm_trigger_done(s, substream);
1126     }
1127 
1128     spin_lock_irqsave(&bus->reg_lock, cookie);
1129 
1130     /* first, set SYNC bits of corresponding streams */
1131     snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1132 
1133     snd_pcm_group_for_each_entry(s, substream) {
1134         if (s->pcm->card != substream->pcm->card)
1135             continue;
1136         stream = get_hdac_ext_stream(s);
1137         if (start)
1138             snd_hdac_stream_start(hdac_stream(stream), true);
1139         else
1140             snd_hdac_stream_stop(hdac_stream(stream));
1141     }
1142     spin_unlock_irqrestore(&bus->reg_lock, cookie);
1143 
1144     snd_hdac_stream_sync(hstr, start, sbits);
1145 
1146     spin_lock_irqsave(&bus->reg_lock, cookie);
1147 
1148     /* reset SYNC bits */
1149     snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1150     if (start)
1151         snd_hdac_stream_timecounter_init(hstr, sbits);
1152     spin_unlock_irqrestore(&bus->reg_lock, cookie);
1153 
1154     return 0;
1155 }
1156 
1157 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1158                     struct snd_pcm_substream *substream,
1159                     int cmd)
1160 {
1161     struct hdac_bus *bus = get_bus_ctx(substream);
1162 
1163     if (!bus->ppcap)
1164         return skl_coupled_trigger(substream, cmd);
1165 
1166     return 0;
1167 }
1168 
1169 static snd_pcm_uframes_t skl_platform_soc_pointer(
1170     struct snd_soc_component *component,
1171     struct snd_pcm_substream *substream)
1172 {
1173     struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1174     struct hdac_bus *bus = get_bus_ctx(substream);
1175     unsigned int pos;
1176 
1177     /*
1178      * Use DPIB for Playback stream as the periodic DMA Position-in-
1179      * Buffer Writes may be scheduled at the same time or later than
1180      * the MSI and does not guarantee to reflect the Position of the
1181      * last buffer that was transferred. Whereas DPIB register in
1182      * HAD space reflects the actual data that is transferred.
1183      * Use the position buffer for capture, as DPIB write gets
1184      * completed earlier than the actual data written to the DDR.
1185      *
1186      * For capture stream following workaround is required to fix the
1187      * incorrect position reporting.
1188      *
1189      * 1. Wait for 20us before reading the DMA position in buffer once
1190      * the interrupt is generated for stream completion as update happens
1191      * on the HDA frame boundary i.e. 20.833uSec.
1192      * 2. Read DPIB register to flush the DMA position value. This dummy
1193      * read is required to flush DMA position value.
1194      * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1195      * or greater than period boundary.
1196      */
1197 
1198     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1199         pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1200                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1201                 hdac_stream(hstream)->index));
1202     } else {
1203         udelay(20);
1204         readl(bus->remap_addr +
1205                 AZX_REG_VS_SDXDPIB_XBASE +
1206                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1207                  hdac_stream(hstream)->index));
1208         pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1209     }
1210 
1211     if (pos >= hdac_stream(hstream)->bufsize)
1212         pos = 0;
1213 
1214     return bytes_to_frames(substream->runtime, pos);
1215 }
1216 
1217 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1218                 u64 nsec)
1219 {
1220     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1221     struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
1222     u64 codec_frames, codec_nsecs;
1223 
1224     if (!codec_dai->driver->ops->delay)
1225         return nsec;
1226 
1227     codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1228     codec_nsecs = div_u64(codec_frames * 1000000000LL,
1229                   substream->runtime->rate);
1230 
1231     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1232         return nsec + codec_nsecs;
1233 
1234     return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1235 }
1236 
1237 static int skl_platform_soc_get_time_info(
1238             struct snd_soc_component *component,
1239             struct snd_pcm_substream *substream,
1240             struct timespec64 *system_ts, struct timespec64 *audio_ts,
1241             struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1242             struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1243 {
1244     struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1245     struct hdac_stream *hstr = hdac_stream(sstream);
1246     u64 nsec;
1247 
1248     if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1249         (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1250 
1251         snd_pcm_gettime(substream->runtime, system_ts);
1252 
1253         nsec = timecounter_read(&hstr->tc);
1254         if (audio_tstamp_config->report_delay)
1255             nsec = skl_adjust_codec_delay(substream, nsec);
1256 
1257         *audio_ts = ns_to_timespec64(nsec);
1258 
1259         audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1260         audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1261         audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1262 
1263     } else {
1264         audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1265     }
1266 
1267     return 0;
1268 }
1269 
1270 #define MAX_PREALLOC_SIZE   (32 * 1024 * 1024)
1271 
1272 static int skl_platform_soc_new(struct snd_soc_component *component,
1273                 struct snd_soc_pcm_runtime *rtd)
1274 {
1275     struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
1276     struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1277     struct snd_pcm *pcm = rtd->pcm;
1278     unsigned int size;
1279     struct skl_dev *skl = bus_to_skl(bus);
1280 
1281     if (dai->driver->playback.channels_min ||
1282         dai->driver->capture.channels_min) {
1283         /* buffer pre-allocation */
1284         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1285         if (size > MAX_PREALLOC_SIZE)
1286             size = MAX_PREALLOC_SIZE;
1287         snd_pcm_set_managed_buffer_all(pcm,
1288                            SNDRV_DMA_TYPE_DEV_SG,
1289                            &skl->pci->dev,
1290                            size, MAX_PREALLOC_SIZE);
1291     }
1292 
1293     return 0;
1294 }
1295 
1296 static int skl_get_module_info(struct skl_dev *skl,
1297         struct skl_module_cfg *mconfig)
1298 {
1299     struct skl_module_inst_id *pin_id;
1300     guid_t *uuid_mod, *uuid_tplg;
1301     struct skl_module *skl_module;
1302     struct uuid_module *module;
1303     int i, ret = -EIO;
1304 
1305     uuid_mod = (guid_t *)mconfig->guid;
1306 
1307     if (list_empty(&skl->uuid_list)) {
1308         dev_err(skl->dev, "Module list is empty\n");
1309         return -EIO;
1310     }
1311 
1312     for (i = 0; i < skl->nr_modules; i++) {
1313         skl_module = skl->modules[i];
1314         uuid_tplg = &skl_module->uuid;
1315         if (guid_equal(uuid_mod, uuid_tplg)) {
1316             mconfig->module = skl_module;
1317             ret = 0;
1318             break;
1319         }
1320     }
1321 
1322     if (skl->nr_modules && ret)
1323         return ret;
1324 
1325     ret = -EIO;
1326     list_for_each_entry(module, &skl->uuid_list, list) {
1327         if (guid_equal(uuid_mod, &module->uuid)) {
1328             mconfig->id.module_id = module->id;
1329             mconfig->module->loadable = module->is_loadable;
1330             ret = 0;
1331         }
1332 
1333         for (i = 0; i < MAX_IN_QUEUE; i++) {
1334             pin_id = &mconfig->m_in_pin[i].id;
1335             if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1336                 pin_id->module_id = module->id;
1337         }
1338 
1339         for (i = 0; i < MAX_OUT_QUEUE; i++) {
1340             pin_id = &mconfig->m_out_pin[i].id;
1341             if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1342                 pin_id->module_id = module->id;
1343         }
1344     }
1345 
1346     return ret;
1347 }
1348 
1349 static int skl_populate_modules(struct skl_dev *skl)
1350 {
1351     struct skl_pipeline *p;
1352     struct skl_pipe_module *m;
1353     struct snd_soc_dapm_widget *w;
1354     struct skl_module_cfg *mconfig;
1355     int ret = 0;
1356 
1357     list_for_each_entry(p, &skl->ppl_list, node) {
1358         list_for_each_entry(m, &p->pipe->w_list, node) {
1359             w = m->w;
1360             mconfig = w->priv;
1361 
1362             ret = skl_get_module_info(skl, mconfig);
1363             if (ret < 0) {
1364                 dev_err(skl->dev,
1365                     "query module info failed\n");
1366                 return ret;
1367             }
1368 
1369             skl_tplg_add_moduleid_in_bind_params(skl, w);
1370         }
1371     }
1372 
1373     return ret;
1374 }
1375 
1376 static int skl_platform_soc_probe(struct snd_soc_component *component)
1377 {
1378     struct hdac_bus *bus = dev_get_drvdata(component->dev);
1379     struct skl_dev *skl = bus_to_skl(bus);
1380     const struct skl_dsp_ops *ops;
1381     int ret;
1382 
1383     ret = pm_runtime_resume_and_get(component->dev);
1384     if (ret < 0 && ret != -EACCES)
1385         return ret;
1386 
1387     if (bus->ppcap) {
1388         skl->component = component;
1389 
1390         /* init debugfs */
1391         skl->debugfs = skl_debugfs_init(skl);
1392 
1393         ret = skl_tplg_init(component, bus);
1394         if (ret < 0) {
1395             dev_err(component->dev, "Failed to init topology!\n");
1396             return ret;
1397         }
1398 
1399         /* load the firmwares, since all is set */
1400         ops = skl_get_dsp_ops(skl->pci->device);
1401         if (!ops)
1402             return -EIO;
1403 
1404         /*
1405          * Disable dynamic clock and power gating during firmware
1406          * and library download
1407          */
1408         skl->enable_miscbdcge(component->dev, false);
1409         skl->clock_power_gating(component->dev, false);
1410 
1411         ret = ops->init_fw(component->dev, skl);
1412         skl->enable_miscbdcge(component->dev, true);
1413         skl->clock_power_gating(component->dev, true);
1414         if (ret < 0) {
1415             dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1416             return ret;
1417         }
1418         skl_populate_modules(skl);
1419         skl->update_d0i3c = skl_update_d0i3c;
1420 
1421         if (skl->cfg.astate_cfg != NULL) {
1422             skl_dsp_set_astate_cfg(skl,
1423                     skl->cfg.astate_cfg->count,
1424                     skl->cfg.astate_cfg);
1425         }
1426     }
1427     pm_runtime_mark_last_busy(component->dev);
1428     pm_runtime_put_autosuspend(component->dev);
1429 
1430     return 0;
1431 }
1432 
1433 static void skl_platform_soc_remove(struct snd_soc_component *component)
1434 {
1435     struct hdac_bus *bus = dev_get_drvdata(component->dev);
1436     struct skl_dev *skl = bus_to_skl(bus);
1437 
1438     skl_tplg_exit(component, bus);
1439 
1440     skl_debugfs_exit(skl);
1441 }
1442 
1443 static const struct snd_soc_component_driver skl_component  = {
1444     .name       = "pcm",
1445     .probe      = skl_platform_soc_probe,
1446     .remove     = skl_platform_soc_remove,
1447     .open       = skl_platform_soc_open,
1448     .trigger    = skl_platform_soc_trigger,
1449     .pointer    = skl_platform_soc_pointer,
1450     .get_time_info  = skl_platform_soc_get_time_info,
1451     .pcm_construct  = skl_platform_soc_new,
1452     .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1453 };
1454 
1455 int skl_platform_register(struct device *dev)
1456 {
1457     int ret;
1458     struct snd_soc_dai_driver *dais;
1459     int num_dais = ARRAY_SIZE(skl_platform_dai);
1460     struct hdac_bus *bus = dev_get_drvdata(dev);
1461     struct skl_dev *skl = bus_to_skl(bus);
1462 
1463     skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1464                 GFP_KERNEL);
1465     if (!skl->dais) {
1466         ret = -ENOMEM;
1467         goto err;
1468     }
1469 
1470     if (!skl->use_tplg_pcm) {
1471         dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1472                 sizeof(skl_platform_dai), GFP_KERNEL);
1473         if (!dais) {
1474             ret = -ENOMEM;
1475             goto err;
1476         }
1477 
1478         skl->dais = dais;
1479         memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1480                sizeof(skl_fe_dai));
1481         num_dais += ARRAY_SIZE(skl_fe_dai);
1482     }
1483 
1484     ret = devm_snd_soc_register_component(dev, &skl_component,
1485                      skl->dais, num_dais);
1486     if (ret)
1487         dev_err(dev, "soc component registration failed %d\n", ret);
1488 err:
1489     return ret;
1490 }
1491 
1492 int skl_platform_unregister(struct device *dev)
1493 {
1494     struct hdac_bus *bus = dev_get_drvdata(dev);
1495     struct skl_dev *skl = bus_to_skl(bus);
1496     struct skl_module_deferred_bind *modules, *tmp;
1497 
1498     list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1499         list_del(&modules->node);
1500         kfree(modules);
1501     }
1502 
1503     kfree(skl->dais);
1504 
1505     return 0;
1506 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!