intel/skylake/skl-i2s.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  skl-i2s.h - i2s blob mapping
0004  *
0005  *  Copyright (C) 2017 Intel Corp
0006  *  Author: Subhransu S. Prusty < subhransu.s.prusty@intel.com>
0007  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0008  *
0009  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0010  */
0011
0012 #ifndef __SOUND_SOC_SKL_I2S_H
0013 #define __SOUND_SOC_SKL_I2S_H
0014
0015 #define SKL_I2S_MAX_TIME_SLOTS      8
0016 #define SKL_MCLK_DIV_CLK_SRC_MASK   GENMASK(17, 16)
0017
0018 #define SKL_MNDSS_DIV_CLK_SRC_MASK  GENMASK(21, 20)
0019 #define SKL_SHIFT(x)            (ffs(x) - 1)
0020 #define SKL_MCLK_DIV_RATIO_MASK     GENMASK(11, 0)
0021
0022 #define is_legacy_blob(x) (x.signature != 0xEE)
0023 #define ext_to_legacy_blob(i2s_config_blob_ext) \
0024     ((struct skl_i2s_config_blob_legacy *) i2s_config_blob_ext)
0025
0026 #define get_clk_src(mclk, mask) \
0027         ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask))
0028 struct skl_i2s_config {
0029     u32 ssc0;
0030     u32 ssc1;
0031     u32 sscto;
0032     u32 sspsp;
0033     u32 sstsa;
0034     u32 ssrsa;
0035     u32 ssc2;
0036     u32 sspsp2;
0037     u32 ssc3;
0038     u32 ssioc;
0039 } __packed;
0040
0041 struct skl_i2s_config_mclk {
0042     u32 mdivctrl;
0043     u32 mdivr;
0044 };
0045
0046 struct skl_i2s_config_mclk_ext {
0047     u32 mdivctrl;
0048     u32 mdivr_count;
0049     u32 mdivr[];
0050 } __packed;
0051
0052 struct skl_i2s_config_blob_signature {
0053     u32 minor_ver : 8;
0054     u32 major_ver : 8;
0055     u32 resvdz : 8;
0056     u32 signature : 8;
0057 } __packed;
0058
0059 struct skl_i2s_config_blob_header {
0060     struct skl_i2s_config_blob_signature sig;
0061     u32 size;
0062 };
0063
0064 /**
0065  * struct skl_i2s_config_blob_legacy - Structure defines I2S Gateway
0066  * configuration legacy blob
0067  *
0068  * @gtw_attr:       Gateway attribute for the I2S Gateway
0069  * @tdm_ts_group:   TDM slot mapping against channels in the Gateway.
0070  * @i2s_cfg:        I2S HW registers
0071  * @mclk:       MCLK clock source and divider values
0072  */
0073 struct skl_i2s_config_blob_legacy {
0074     u32 gtw_attr;
0075     u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS];
0076     struct skl_i2s_config i2s_cfg;
0077     struct skl_i2s_config_mclk mclk;
0078 };
0079
0080 struct skl_i2s_config_blob_ext {
0081     u32 gtw_attr;
0082     struct skl_i2s_config_blob_header hdr;
0083     u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS];
0084     struct skl_i2s_config i2s_cfg;
0085     struct skl_i2s_config_mclk_ext mclk;
0086 } __packed;
0087 #endif /* __SOUND_SOC_SKL_I2S_H */